From: Will Deacon <will@kernel.org>
To: Andy Lutomirski <luto@kernel.org>
Cc: Nicholas Piggin <npiggin@gmail.com>,
Mathieu Desnoyers <mathieu.desnoyers@efficios.com>,
X86 ML <x86@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Catalin Marinas <catalin.marinas@arm.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Paul Mackerras <paulus@samba.org>,
stable <stable@vger.kernel.org>
Subject: Re: [RFC please help] membarrier: Rewrite sync_core_before_usermode()
Date: Tue, 5 Jan 2021 13:26:23 +0000 [thread overview]
Message-ID: <20210105132623.GB11108@willie-the-truck> (raw)
In-Reply-To: <CALCETrX4v1KEf6ikVtFg6juh3Z_esJ-+6PLT1A21JJeTVh2k8g@mail.gmail.com>
Hi Andy,
Sorry for the slow reply, I was socially distanced from my keyboard.
On Mon, Dec 28, 2020 at 04:36:11PM -0800, Andy Lutomirski wrote:
> On Mon, Dec 28, 2020 at 4:11 PM Nicholas Piggin <npiggin@gmail.com> wrote:
> > > +static inline void membarrier_sync_core_before_usermode(void)
> > > +{
> > > + /*
> > > + * XXX: I know basically nothing about powerpc cache management.
> > > + * Is this correct?
> > > + */
> > > + isync();
> >
> > This is not about memory ordering or cache management, it's about
> > pipeline management. Powerpc's return to user mode serializes the
> > CPU (aka the hardware thread, _not_ the core; another wrongness of
> > the name, but AFAIKS the HW thread is what is required for
> > membarrier). So this is wrong, powerpc needs nothing here.
>
> Fair enough. I'm happy to defer to you on the powerpc details. In
> any case, this just illustrates that we need feedback from a person
> who knows more about ARM64 than I do.
I think we're in a very similar boat to PowerPC, fwiw. Roughly speaking:
1. SYNC_CORE does _not_ perform any cache management; that is the
responsibility of userspace, either by executing the relevant
maintenance instructions (arm64) or a system call (arm32). Crucially,
the hardware will ensure that this cache maintenance is broadcast
to all other CPUs.
2. Even with all the cache maintenance in the world, a CPU could have
speculatively fetched stale instructions into its "pipeline" ahead of
time, and these are _not_ flushed by the broadcast maintenance instructions
in (1). SYNC_CORE provides a means for userspace to discard these stale
instructions.
3. The context synchronization event on exception entry/exit is
sufficient here. The Arm ARM isn't very good at describing what it
does, because it's in denial about the existence of a pipeline, but
it does have snippets such as:
(s/PE/CPU/)
| For all types of memory:
| The PE might have fetched the instructions from memory at any time
| since the last Context synchronization event on that PE.
Interestingly, the architecture recently added a control bit to remove
this synchronisation from exception return, so if we set that then we'd
have a problem with SYNC_CORE and adding an ISB would be necessary (and
we could probable then make kernel->kernel returns cheaper, but I
suspect we're relying on this implicit synchronisation in other places
too).
Are you seeing a problem in practice, or did this come up while trying to
decipher the semantics of SYNC_CORE?
Will
next prev parent reply other threads:[~2021-01-05 13:27 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-27 18:28 [RFC please help] membarrier: Rewrite sync_core_before_usermode() Andy Lutomirski
2020-12-27 20:18 ` Mathieu Desnoyers
2020-12-27 21:36 ` Andy Lutomirski
2020-12-28 10:25 ` Russell King - ARM Linux admin
2020-12-28 17:14 ` Andy Lutomirski
2020-12-28 17:23 ` Russell King - ARM Linux admin
2020-12-28 18:10 ` Andy Lutomirski
2020-12-28 18:29 ` Jann Horn
2020-12-28 18:50 ` Andy Lutomirski
2020-12-28 19:08 ` Russell King - ARM Linux admin
2020-12-28 19:44 ` Andy Lutomirski
2020-12-28 20:24 ` Russell King - ARM Linux admin
2020-12-28 20:40 ` Mathieu Desnoyers
2020-12-28 20:32 ` Mathieu Desnoyers
2020-12-28 21:06 ` Andy Lutomirski
2020-12-28 21:26 ` Mathieu Desnoyers
2020-12-29 0:36 ` Nicholas Piggin
2020-12-29 0:56 ` Andy Lutomirski
2020-12-29 3:09 ` Nicholas Piggin
2020-12-29 10:44 ` Russell King - ARM Linux admin
2020-12-30 2:33 ` Nicholas Piggin
2020-12-30 10:00 ` Russell King - ARM Linux admin
2020-12-30 10:58 ` Russell King - ARM Linux admin
2020-12-30 11:57 ` Nicholas Piggin
2020-12-28 21:09 ` Mathieu Desnoyers
2020-12-29 0:30 ` Andy Lutomirski
2020-12-29 0:11 ` Nicholas Piggin
2020-12-29 0:36 ` Andy Lutomirski
2020-12-29 3:31 ` Nicholas Piggin
2021-01-01 18:33 ` David Laight
2021-01-05 13:26 ` Will Deacon [this message]
2021-01-05 16:20 ` Andy Lutomirski
2021-01-05 16:37 ` Peter Zijlstra
2021-01-05 22:41 ` Will Deacon
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