* [PATCH v2 0/2] Add support for USB3 PHY on SDX55
@ 2021-01-11 11:30 Manivannan Sadhasivam
2021-01-11 11:30 ` [PATCH v2 1/2] dt-bindings: phy: qcom,qmp: Add SDX55 USB PHY binding Manivannan Sadhasivam
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Manivannan Sadhasivam @ 2021-01-11 11:30 UTC (permalink / raw)
To: kishon, vkoul, robh+dt
Cc: bjorn.andersson, agross, linux-arm-msm, linux-kernel, devicetree,
Manivannan Sadhasivam
Hello,
This series adds USB3 PHY support for SDX55 platform. The USB3 PHY is of
type QMP and revision 4.0.0. In this revision, "com_aux" clock is not
utilized.
This series has been tested on SDX55-MTP along with the relevant DT node.
Thanks,
Mani
Changes in v2:
* Fixed the binding to use only 3 clocks
Manivannan Sadhasivam (2):
dt-bindings: phy: qcom,qmp: Add SDX55 USB PHY binding
phy: qcom-qmp: Add support for SDX55 QMP PHY
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 27 ++++++
drivers/phy/qualcomm/phy-qcom-qmp.c | 83 +++++++++++++++++++
2 files changed, 110 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] dt-bindings: phy: qcom,qmp: Add SDX55 USB PHY binding
2021-01-11 11:30 [PATCH v2 0/2] Add support for USB3 PHY on SDX55 Manivannan Sadhasivam
@ 2021-01-11 11:30 ` Manivannan Sadhasivam
2021-01-14 19:29 ` Rob Herring
2021-01-11 11:30 ` [PATCH v2 2/2] phy: qcom-qmp: Add support for SDX55 QMP PHY Manivannan Sadhasivam
2021-01-17 6:55 ` [PATCH v2 0/2] Add support for USB3 PHY on SDX55 Vinod Koul
2 siblings, 1 reply; 5+ messages in thread
From: Manivannan Sadhasivam @ 2021-01-11 11:30 UTC (permalink / raw)
To: kishon, vkoul, robh+dt
Cc: bjorn.andersson, agross, linux-arm-msm, linux-kernel, devicetree,
Manivannan Sadhasivam
Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found
in SDX55.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index ec05db374645..0f00d82461fd 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -34,6 +34,7 @@ properties:
- qcom,sm8250-qmp-gen3x1-pcie-phy
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
+ - qcom,sdx55-qmp-usb3-uni-phy
reg:
items:
@@ -131,6 +132,32 @@ allOf:
items:
- const: phy
- const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdx55-qmp-usb3-uni-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
- if:
properties:
compatible:
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] phy: qcom-qmp: Add support for SDX55 QMP PHY
2021-01-11 11:30 [PATCH v2 0/2] Add support for USB3 PHY on SDX55 Manivannan Sadhasivam
2021-01-11 11:30 ` [PATCH v2 1/2] dt-bindings: phy: qcom,qmp: Add SDX55 USB PHY binding Manivannan Sadhasivam
@ 2021-01-11 11:30 ` Manivannan Sadhasivam
2021-01-17 6:55 ` [PATCH v2 0/2] Add support for USB3 PHY on SDX55 Vinod Koul
2 siblings, 0 replies; 5+ messages in thread
From: Manivannan Sadhasivam @ 2021-01-11 11:30 UTC (permalink / raw)
To: kishon, vkoul, robh+dt
Cc: bjorn.andersson, agross, linux-arm-msm, linux-kernel, devicetree,
Manivannan Sadhasivam
Add support for USB3 QMP PHY found in SDX55 platform. SDX55 uses
version 4.0.0 of the QMP PHY IP and doesn't make use of "com_aux" clock.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 83 +++++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 0939a9e9d448..bdcb8bf6225d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1974,6 +1974,53 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
};
+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
+};
+
+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
+};
+
/* struct qmp_phy_cfg - per-PHY initialization config */
struct qmp_phy_cfg {
/* phy-type - PCIE/UFS/USB */
@@ -2183,6 +2230,11 @@ static const char * const sdm845_ufs_phy_clk_l[] = {
"ref", "ref_aux",
};
+/* usb3 phy on sdx55 doesn't have com_aux clock */
+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
+ "aux", "cfg_ahb", "ref"
+};
+
/* list of resets */
static const char * const msm8996_pciephy_reset_l[] = {
"phy", "common", "cfg",
@@ -2824,6 +2876,34 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
};
+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+
+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
+ .reset_list = msm8996_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = qmp_v4_usb3_uniphy_regs_layout,
+
+ .start_ctrl = SERDES_START | PCS_START,
+ .pwrdn_ctrl = SW_PWRDN,
+
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+};
+
static void qcom_qmp_phy_configure_lane(void __iomem *base,
const unsigned int *regs,
const struct qmp_phy_init_tbl tbl[],
@@ -4173,6 +4253,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
}, {
.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
+ }, {
+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
+ .data = &sdx55_usb3_uniphy_cfg,
},
{ },
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: phy: qcom,qmp: Add SDX55 USB PHY binding
2021-01-11 11:30 ` [PATCH v2 1/2] dt-bindings: phy: qcom,qmp: Add SDX55 USB PHY binding Manivannan Sadhasivam
@ 2021-01-14 19:29 ` Rob Herring
0 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2021-01-14 19:29 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: vkoul, linux-kernel, linux-arm-msm, robh+dt, agross, kishon,
bjorn.andersson, devicetree
On Mon, 11 Jan 2021 17:00:09 +0530, Manivannan Sadhasivam wrote:
> Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found
> in SDX55.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 0/2] Add support for USB3 PHY on SDX55
2021-01-11 11:30 [PATCH v2 0/2] Add support for USB3 PHY on SDX55 Manivannan Sadhasivam
2021-01-11 11:30 ` [PATCH v2 1/2] dt-bindings: phy: qcom,qmp: Add SDX55 USB PHY binding Manivannan Sadhasivam
2021-01-11 11:30 ` [PATCH v2 2/2] phy: qcom-qmp: Add support for SDX55 QMP PHY Manivannan Sadhasivam
@ 2021-01-17 6:55 ` Vinod Koul
2 siblings, 0 replies; 5+ messages in thread
From: Vinod Koul @ 2021-01-17 6:55 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: kishon, robh+dt, bjorn.andersson, agross, linux-arm-msm,
linux-kernel, devicetree
On 11-01-21, 17:00, Manivannan Sadhasivam wrote:
> Hello,
>
> This series adds USB3 PHY support for SDX55 platform. The USB3 PHY is of
> type QMP and revision 4.0.0. In this revision, "com_aux" clock is not
> utilized.
>
> This series has been tested on SDX55-MTP along with the relevant DT node.
Applied, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-01-17 6:58 UTC | newest]
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2021-01-11 11:30 [PATCH v2 0/2] Add support for USB3 PHY on SDX55 Manivannan Sadhasivam
2021-01-11 11:30 ` [PATCH v2 1/2] dt-bindings: phy: qcom,qmp: Add SDX55 USB PHY binding Manivannan Sadhasivam
2021-01-14 19:29 ` Rob Herring
2021-01-11 11:30 ` [PATCH v2 2/2] phy: qcom-qmp: Add support for SDX55 QMP PHY Manivannan Sadhasivam
2021-01-17 6:55 ` [PATCH v2 0/2] Add support for USB3 PHY on SDX55 Vinod Koul
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