* [PATCH 1/2] arm64: dts: imx8mn: Add fspi node
@ 2021-01-19 13:42 Adam Ford
2021-01-19 13:42 ` [PATCH 2/2] arm64: dts: imx8mn-beacon-som: Enable QSPI on SOM Adam Ford
0 siblings, 1 reply; 3+ messages in thread
From: Adam Ford @ 2021-01-19 13:42 UTC (permalink / raw)
To: linux-arm-kernel
Cc: aford, Adam Ford, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
devicetree, linux-kernel
The i.MX8M Nano has the same Flexspi controller used in the i.MX8M
Mini. Add the node and disable it by default.
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 3fac73779fdd..16ea50089567 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -889,6 +889,19 @@ usdhc3: mmc@30b60000 {
status = "disabled";
};
+ flexspi: spi@30bb0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imx8mm-fspi";
+ reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
+ <&clk IMX8MN_CLK_QSPI_ROOT>;
+ clock-names = "fspi", "fspi_en";
+ status = "disabled";
+ };
+
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
reg = <0x30bd0000 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] arm64: dts: imx8mn-beacon-som: Enable QSPI on SOM
2021-01-19 13:42 [PATCH 1/2] arm64: dts: imx8mn: Add fspi node Adam Ford
@ 2021-01-19 13:42 ` Adam Ford
2021-01-25 19:19 ` Krzysztof Kozlowski
0 siblings, 1 reply; 3+ messages in thread
From: Adam Ford @ 2021-01-19 13:42 UTC (permalink / raw)
To: linux-arm-kernel
Cc: aford, Adam Ford, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
devicetree, linux-kernel
There is a QSPI chip connected to the FlexSPI bus. Enable it.
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
index 2120e6485393..9f575184d899 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
@@ -7,6 +7,7 @@ / {
aliases {
rtc0 = &rtc;
rtc1 = &snvs_rtc;
+ spi0 = &flexspi;
};
usdhc1_pwrseq: usdhc1_pwrseq {
@@ -89,6 +90,22 @@ ethphy0: ethernet-phy@0 {
};
};
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi>;
+ status = "okay";
+
+ flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -318,6 +335,18 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
+ pinctrl_flexspi: flexspigrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
+ MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+ >;
+ };
+
+
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8mn-beacon-som: Enable QSPI on SOM
2021-01-19 13:42 ` [PATCH 2/2] arm64: dts: imx8mn-beacon-som: Enable QSPI on SOM Adam Ford
@ 2021-01-25 19:19 ` Krzysztof Kozlowski
0 siblings, 0 replies; 3+ messages in thread
From: Krzysztof Kozlowski @ 2021-01-25 19:19 UTC (permalink / raw)
To: Adam Ford
Cc: linux-arm-kernel, aford, Rob Herring, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
devicetree, linux-kernel
On Tue, Jan 19, 2021 at 07:42:58AM -0600, Adam Ford wrote:
> There is a QSPI chip connected to the FlexSPI bus. Enable it.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
> index 2120e6485393..9f575184d899 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
> @@ -7,6 +7,7 @@ / {
> aliases {
> rtc0 = &rtc;
> rtc1 = &snvs_rtc;
> + spi0 = &flexspi;
> };
>
> usdhc1_pwrseq: usdhc1_pwrseq {
> @@ -89,6 +90,22 @@ ethphy0: ethernet-phy@0 {
> };
> };
>
> +&flexspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexspi>;
> + status = "okay";
> +
> + flash@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <80000000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + };
> +};
> +
> &i2c1 {
> clock-frequency = <400000>;
> pinctrl-names = "default";
> @@ -318,6 +335,18 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
> >;
> };
>
> + pinctrl_flexspi: flexspigrp {
> + fsl,pins = <
> + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
> + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
> + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
> + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
> + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
> + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
> + >;
> + };
> +
> +
Double line break. Beside that:
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-01-19 13:42 [PATCH 1/2] arm64: dts: imx8mn: Add fspi node Adam Ford
2021-01-19 13:42 ` [PATCH 2/2] arm64: dts: imx8mn-beacon-som: Enable QSPI on SOM Adam Ford
2021-01-25 19:19 ` Krzysztof Kozlowski
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