* [PATCH 01/11] fix: arm64: dts: replace wrong regulator on ap emmc
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
@ 2021-02-03 13:31 ` kostap
2021-02-03 13:31 ` [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings kostap
` (9 subsequent siblings)
10 siblings, 0 replies; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Konstantin Porotchkin <kostap@marvell.com>
Replace wrong regulator in AP0 eMMC definition on MacchiatoBIN
board with 3.3V regulator.
The MacchiatoBIN board has no 1.8V regulator connected to AP0
eMMC (ap0_sdhci0) interface.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index cbcb210cb6d8..73733b4126e2 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -119,7 +119,7 @@
no-sdio;
non-removable;
status = "okay";
- vqmmc-supply = <&v_vddo_h>;
+ vqmmc-supply = <&v_3_3>;
};
&cp0_i2c0 {
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
2021-02-03 13:31 ` [PATCH 01/11] fix: arm64: dts: replace wrong regulator on ap emmc kostap
@ 2021-02-03 13:31 ` kostap
2021-02-03 13:58 ` Baruch Siach
2021-02-03 13:31 ` [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce kostap
` (8 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Konstantin Porotchkin <kostap@marvell.com>
Update the settings for AP806 SDHCI interface according to
latest Xenon drivers changes.
- no need to select the PHY slow mode anymore
- recommended to add HS400 support at 1.8V signalling on AP806-B0
- fix the bus witdth for A8040 DB from 4 to 8 bits.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 11 ++++++++++-
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 5 -----
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 1 -
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 09fb5256f1db..6362e654a823 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -347,7 +347,16 @@
&ap_sdhci0 {
status = "okay";
- bus-width = <4>;
+ bus-width = <8>;
+ /* The below property should be added to boards with AP806-B0
+ * for enabling HS400 speed mode. Otherwise the device highest
+ * speed mode will be HS200.
+ * Should not be added to boards with earlier release of AP806
+ * since it will cause SDHCI driver to fail upon initialization.
+ * Reference - HWE-7296210 (errata for releases A0/A1/A2)
+ *
+ * mmc-hs400-1_8v;
+ */
non-removable;
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index 73733b4126e2..69653de998e2 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -109,11 +109,6 @@
&ap_sdhci0 {
bus-width = <8>;
- /*
- * Not stable in HS modes - phy needs "more calibration", so add
- * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
- */
- marvell,xenon-phy-slow-mode;
no-1-8-v;
no-sd;
no-sdio;
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index 12e477f1aeb9..edd6131a0587 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -257,7 +257,6 @@
clock-names = "core";
clocks = <&ap_clk 4>;
dma-coherent;
- marvell,xenon-phy-slow-mode;
status = "disabled";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
2021-02-03 13:31 ` [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings kostap
@ 2021-02-03 13:58 ` Baruch Siach
2021-02-03 14:37 ` [EXT] " Kostya Porotchkin
0 siblings, 1 reply; 27+ messages in thread
From: Baruch Siach @ 2021-02-03 13:58 UTC (permalink / raw)
To: kostap
Cc: linux-kernel, devicetree, andrew, jaz, gregory.clement, linux,
nadavh, robh+dt, stefanc, mw, bpeled, sebastian.hesselbarth,
linux-arm-kernel
Hi Konstantin,
On Wed, Feb 03 2021, kostap@marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Update the settings for AP806 SDHCI interface according to
> latest Xenon drivers changes.
> - no need to select the PHY slow mode anymore
Why? Has anything changed since the introduction of
marvell,xenon-phy-slow-mode?
baruch
> - recommended to add HS400 support at 1.8V signalling on AP806-B0
> - fix the bus witdth for A8040 DB from 4 to 8 bits.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> ---
> arch/arm64/boot/dts/marvell/armada-8040-db.dts | 11 ++++++++++-
> arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 5 -----
> arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 1 -
> 3 files changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
> index 09fb5256f1db..6362e654a823 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
> @@ -347,7 +347,16 @@
>
> &ap_sdhci0 {
> status = "okay";
> - bus-width = <4>;
> + bus-width = <8>;
> + /* The below property should be added to boards with AP806-B0
> + * for enabling HS400 speed mode. Otherwise the device highest
> + * speed mode will be HS200.
> + * Should not be added to boards with earlier release of AP806
> + * since it will cause SDHCI driver to fail upon initialization.
> + * Reference - HWE-7296210 (errata for releases A0/A1/A2)
> + *
> + * mmc-hs400-1_8v;
> + */
> non-removable;
> };
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> index 73733b4126e2..69653de998e2 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> @@ -109,11 +109,6 @@
>
> &ap_sdhci0 {
> bus-width = <8>;
> - /*
> - * Not stable in HS modes - phy needs "more calibration", so add
> - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
> - */
> - marvell,xenon-phy-slow-mode;
> no-1-8-v;
> no-sd;
> no-sdio;
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> index 12e477f1aeb9..edd6131a0587 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> @@ -257,7 +257,6 @@
> clock-names = "core";
> clocks = <&ap_clk 4>;
> dma-coherent;
> - marvell,xenon-phy-slow-mode;
> status = "disabled";
> };
--
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
2021-02-03 13:58 ` Baruch Siach
@ 2021-02-03 14:37 ` Kostya Porotchkin
2021-02-03 14:38 ` Russell King - ARM Linux admin
0 siblings, 1 reply; 27+ messages in thread
From: Kostya Porotchkin @ 2021-02-03 14:37 UTC (permalink / raw)
To: Baruch Siach
Cc: linux-kernel, devicetree, andrew, jaz, gregory.clement, linux,
Nadav Haklai, robh+dt, Stefan Chulski, mw, Ben Peled,
sebastian.hesselbarth, linux-arm-kernel
Hi, Baruch,
> -----Original Message-----
> From: Baruch Siach <baruch@tkos.co.il>
> Sent: Wednesday, February 3, 2021 15:59
> To: Kostya Porotchkin <kostap@marvell.com>
> Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> andrew@lunn.ch; jaz@semihalf.com; gregory.clement@bootlin.com;
> linux@armlinux.org.uk; Nadav Haklai <nadavh@marvell.com>;
> robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>;
> mw@semihalf.com; Ben Peled <bpeled@marvell.com>;
> sebastian.hesselbarth@gmail.com; linux-arm-kernel@lists.infradead.org
> Subject: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI
> settings
>
> External Email
>
> ----------------------------------------------------------------------
> Hi Konstantin,
>
> On Wed, Feb 03 2021, kostap@marvell.com wrote:
> > From: Konstantin Porotchkin <kostap@marvell.com>
> >
> > Update the settings for AP806 SDHCI interface according to latest
> > Xenon drivers changes.
> > - no need to select the PHY slow mode anymore
>
> Why? Has anything changed since the introduction of marvell,xenon-phy-slow-
> mode?
[KP] AP806 B0, AP807 and later do not need the "slow mode" set by the default.
The HWE-7296210 errata is not applicable to these components and they are able
to run AP SDHCI in HS400 8-bit mode.
Kosta
>
> baruch
>
> > - * Not stable in HS modes - phy needs "more calibration", so add
> > - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
> > - */
> > - marvell,xenon-phy-slow-mode;
> > no-1-8-v;
> > no-sd;
> > no-sdio;
> > diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> > b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> > index 12e477f1aeb9..edd6131a0587 100644
> > --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> > +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> > @@ -257,7 +257,6 @@
> > clock-names = "core";
> > clocks = <&ap_clk 4>;
> > dma-coherent;
> > - marvell,xenon-phy-slow-mode;
> > status = "disabled";
> > };
>
>
> --
> ~. .~ Tk Open Systems
> =}------------------------------------------------ooO--U--Ooo------------{=
> - baruch@tkos.co.il - tel: +972.52.368.4656,
> https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__www.tkos.co.il&d=DwIBAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=-
> N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=F567knLB6kbyr-
> BZRqLFLJgXHENu41578OHxsKQQ-
> sw&s=eXEBLtBC3CwWIF9XFbHrgSgASz4aMgHi5W1uuXTgdQ4&e= -
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
2021-02-03 14:37 ` [EXT] " Kostya Porotchkin
@ 2021-02-03 14:38 ` Russell King - ARM Linux admin
2021-02-03 14:50 ` Kostya Porotchkin
0 siblings, 1 reply; 27+ messages in thread
From: Russell King - ARM Linux admin @ 2021-02-03 14:38 UTC (permalink / raw)
To: Kostya Porotchkin
Cc: Baruch Siach, linux-kernel, devicetree, andrew, jaz,
gregory.clement, Nadav Haklai, robh+dt, Stefan Chulski, mw,
Ben Peled, sebastian.hesselbarth, linux-arm-kernel
On Wed, Feb 03, 2021 at 02:37:22PM +0000, Kostya Porotchkin wrote:
> Hi, Baruch,
>
> > -----Original Message-----
> > From: Baruch Siach <baruch@tkos.co.il>
> > Sent: Wednesday, February 3, 2021 15:59
> > To: Kostya Porotchkin <kostap@marvell.com>
> > Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> > andrew@lunn.ch; jaz@semihalf.com; gregory.clement@bootlin.com;
> > linux@armlinux.org.uk; Nadav Haklai <nadavh@marvell.com>;
> > robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>;
> > mw@semihalf.com; Ben Peled <bpeled@marvell.com>;
> > sebastian.hesselbarth@gmail.com; linux-arm-kernel@lists.infradead.org
> > Subject: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI
> > settings
> >
> > External Email
> >
> > ----------------------------------------------------------------------
> > Hi Konstantin,
> >
> > On Wed, Feb 03 2021, kostap@marvell.com wrote:
> > > From: Konstantin Porotchkin <kostap@marvell.com>
> > >
> > > Update the settings for AP806 SDHCI interface according to latest
> > > Xenon drivers changes.
> > > - no need to select the PHY slow mode anymore
> >
> > Why? Has anything changed since the introduction of marvell,xenon-phy-slow-
> > mode?
> [KP] AP806 B0, AP807 and later do not need the "slow mode" set by the default.
> The HWE-7296210 errata is not applicable to these components and they are able
> to run AP SDHCI in HS400 8-bit mode.
So what about all those people, such as me, who have A0 silicon on their
Macchiatobin boards?
You can't just go around removing DT properties like this.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
2021-02-03 14:38 ` Russell King - ARM Linux admin
@ 2021-02-03 14:50 ` Kostya Porotchkin
2021-02-03 15:03 ` Kostya Porotchkin
2021-02-03 16:11 ` Russell King - ARM Linux admin
0 siblings, 2 replies; 27+ messages in thread
From: Kostya Porotchkin @ 2021-02-03 14:50 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: Baruch Siach, linux-kernel, devicetree, andrew, jaz,
gregory.clement, Nadav Haklai, robh+dt, Stefan Chulski, mw,
Ben Peled, sebastian.hesselbarth, linux-arm-kernel
> -----Original Message-----
> From: Russell King - ARM Linux admin <linux@armlinux.org.uk>
> Sent: Wednesday, February 3, 2021 16:39
> To: Kostya Porotchkin <kostap@marvell.com>
> Cc: Baruch Siach <baruch@tkos.co.il>; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; andrew@lunn.ch; jaz@semihalf.com;
> gregory.clement@bootlin.com; Nadav Haklai <nadavh@marvell.com>;
> robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>;
> mw@semihalf.com; Ben Peled <bpeled@marvell.com>;
> sebastian.hesselbarth@gmail.com; linux-arm-kernel@lists.infradead.org
> Subject: Re: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI
> settings
>
> On Wed, Feb 03, 2021 at 02:37:22PM +0000, Kostya Porotchkin wrote:
> > Hi, Baruch,
> >
> > > -----Original Message-----
> > > From: Baruch Siach <baruch@tkos.co.il>
> > > Sent: Wednesday, February 3, 2021 15:59
> > > To: Kostya Porotchkin <kostap@marvell.com>
> > > Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> > > andrew@lunn.ch; jaz@semihalf.com; gregory.clement@bootlin.com;
> > > linux@armlinux.org.uk; Nadav Haklai <nadavh@marvell.com>;
> > > robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>;
> > > mw@semihalf.com; Ben Peled <bpeled@marvell.com>;
> > > sebastian.hesselbarth@gmail.com;
> > > linux-arm-kernel@lists.infradead.org
> > > Subject: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI
> > > settings
> > >
> > > External Email
> > >
> > > --------------------------------------------------------------------
> > > --
> > > Hi Konstantin,
> > >
> > > On Wed, Feb 03 2021, kostap@marvell.com wrote:
> > > > From: Konstantin Porotchkin <kostap@marvell.com>
> > > >
> > > > Update the settings for AP806 SDHCI interface according to latest
> > > > Xenon drivers changes.
> > > > - no need to select the PHY slow mode anymore
> > >
> > > Why? Has anything changed since the introduction of
> > > marvell,xenon-phy-slow- mode?
> > [KP] AP806 B0, AP807 and later do not need the "slow mode" set by the
> default.
> > The HWE-7296210 errata is not applicable to these components and they
> > are able to run AP SDHCI in HS400 8-bit mode.
>
> So what about all those people, such as me, who have A0 silicon on their
> Macchiatobin boards?
>
> You can't just go around removing DT properties like this.
>
[KP] So for older systems this "slow mode" parameter could be set on the board level.
When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR52, even if they support HS400 on AP side.
MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v" flag set, so it should remain in low speed anyway.
> --
> RMK's Patch system: https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__www.armlinux.org.uk_developer_patches_&d=DwIBAg&c=nKjWec2b6R0
> mOyPaz7xtfQ&r=-
> N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=yMC9YPQXZUm
> QPwlD7KCTVoVTPXCTQwTXD2yVsAo6sxA&s=OuBO2QArzHvV4k_vsNZdmSoDX
> rL4Q_voTqxrlYU6KKE&e=
> FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
2021-02-03 14:50 ` Kostya Porotchkin
@ 2021-02-03 15:03 ` Kostya Porotchkin
2021-02-03 16:11 ` Russell King - ARM Linux admin
1 sibling, 0 replies; 27+ messages in thread
From: Kostya Porotchkin @ 2021-02-03 15:03 UTC (permalink / raw)
To: Kostya Porotchkin, Russell King - ARM Linux admin
Cc: devicetree, Baruch Siach, andrew, jaz, gregory.clement,
linux-kernel, Nadav Haklai, robh+dt, Stefan Chulski, mw,
Ben Peled, linux-arm-kernel, sebastian.hesselbarth
> -----Original Message-----
> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org> On
> Behalf Of Kostya Porotchkin
> Sent: Wednesday, February 3, 2021 16:51
> To: Russell King - ARM Linux admin <linux@armlinux.org.uk>
> Cc: devicetree@vger.kernel.org; Baruch Siach <baruch@tkos.co.il>;
> andrew@lunn.ch; jaz@semihalf.com; gregory.clement@bootlin.com; linux-
> kernel@vger.kernel.org; Nadav Haklai <nadavh@marvell.com>;
> robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>;
> mw@semihalf.com; Ben Peled <bpeled@marvell.com>; linux-arm-
> kernel@lists.infradead.org; sebastian.hesselbarth@gmail.com
> Subject: RE: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI
> settings
[KP]
> > > > Hi Konstantin,
> > > >
> > > > On Wed, Feb 03 2021, kostap@marvell.com wrote:
> > > > > From: Konstantin Porotchkin <kostap@marvell.com>
> > > > >
> > > > > Update the settings for AP806 SDHCI interface according to
> > > > > latest Xenon drivers changes.
> > > > > - no need to select the PHY slow mode anymore
> > > >
> > > > Why? Has anything changed since the introduction of
> > > > marvell,xenon-phy-slow- mode?
> > > [KP] AP806 B0, AP807 and later do not need the "slow mode" set by
> > > the
> > default.
> > > The HWE-7296210 errata is not applicable to these components and
> > > they are able to run AP SDHCI in HS400 8-bit mode.
> >
> > So what about all those people, such as me, who have A0 silicon on
> > their Macchiatobin boards?
> >
> > You can't just go around removing DT properties like this.
> >
> [KP] So for older systems this "slow mode" parameter could be set on the
> board level.
> When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR52, even if
> they support HS400 on AP side.
> MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v" flag
> set, so it should remain in low speed anyway.
[KP] I also forgot to mention this code piece in Xenon driver:
/* Disable HS200 on Armada AP806 */
if (priv->hw_version == XENON_AP806)
host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
>
> > --
> > RMK's Patch system: https://urldefense.proofpoint.com/v2/url?u=https-
> >
> 3A__www.armlinux.org.uk_developer_patches_&d=DwIBAg&c=nKjWec2b6R0
> > mOyPaz7xtfQ&r=-
> >
> N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=yMC9YPQXZUm
> >
> QPwlD7KCTVoVTPXCTQwTXD2yVsAo6sxA&s=OuBO2QArzHvV4k_vsNZdmSoDX
> > rL4Q_voTqxrlYU6KKE&e=
> > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__lists.infradead.org_mailman_listinfo_linux-2Darm-
> 2Dkernel&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=-
> N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=8f-
> 1fnISJVHCS4gZTeFgRPXGPiwBevUsFbmYDBmkRWM&s=RBlEEUXG0sOmZHsQ
> Omurf018V8kSE_IMZR7bDLVJ0FA&e=
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
2021-02-03 14:50 ` Kostya Porotchkin
2021-02-03 15:03 ` Kostya Porotchkin
@ 2021-02-03 16:11 ` Russell King - ARM Linux admin
2021-02-03 16:57 ` Kostya Porotchkin
1 sibling, 1 reply; 27+ messages in thread
From: Russell King - ARM Linux admin @ 2021-02-03 16:11 UTC (permalink / raw)
To: Kostya Porotchkin
Cc: Baruch Siach, linux-kernel, devicetree, andrew, jaz,
gregory.clement, Nadav Haklai, robh+dt, Stefan Chulski, mw,
Ben Peled, sebastian.hesselbarth, linux-arm-kernel
On Wed, Feb 03, 2021 at 02:50:45PM +0000, Kostya Porotchkin wrote:
> [KP] So for older systems this "slow mode" parameter could be set on the board level.
> When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR52, even if they support HS400 on AP side.
> MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v" flag set, so it should remain in low speed anyway.
Your reasoning does not make sense.
The ap80x.dtsi file does not specify "marvell,xenon-phy-slow-mode".
It is not specified at this level. It is already specified at board
level.
Given that Macchiatobin will still use slow mode, why remove the
marvell,xenon-phy-slow-mode property from this file?
Also, if you're upgrading ap80x.dtsi to use a bus-width of 8, why
keep the bus-width specifier of 8 in the board files?
This patch just doesn't make sense, and your responses to our points
seem to add to the confusion.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
2021-02-03 16:11 ` Russell King - ARM Linux admin
@ 2021-02-03 16:57 ` Kostya Porotchkin
2021-02-05 9:33 ` Marcin Wojtas
0 siblings, 1 reply; 27+ messages in thread
From: Kostya Porotchkin @ 2021-02-03 16:57 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: Baruch Siach, linux-kernel, devicetree, andrew, jaz,
gregory.clement, Nadav Haklai, robh+dt, Stefan Chulski, mw,
Ben Peled, sebastian.hesselbarth, linux-arm-kernel
Hello, Russell,
I agree that this patch needs rework.
I will definitely do it and issue a new version.
> On Wed, Feb 03, 2021 at 02:50:45PM +0000, Kostya Porotchkin wrote:
> > [KP] So for older systems this "slow mode" parameter could be set on the
> board level.
> > When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR52, even
> if they support HS400 on AP side.
> > MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v"
> flag set, so it should remain in low speed anyway.
>
> Your reasoning does not make sense.
>
> The ap80x.dtsi file does not specify "marvell,xenon-phy-slow-mode".
> It is not specified at this level. It is already specified at board level.
[KP] it does. In current armada-ap80x.dtsi File this specification is on row 260:
ap_sdhci0: sdhci@6e0000 {
compatible = "marvell,armada-ap806-sdhci";
reg = <0x6e0000 0x300>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&ap_clk 4>;
dma-coherent;
marvell,xenon-phy-slow-mode;
status = "disabled";
};
So I would like to remove this row.
> Given that Macchiatobin will still use slow mode, why remove the
> marvell,xenon-phy-slow-mode property from this file?
[KP] Agree, I will keep this property in Macchiatobin DTS file.
>
> Also, if you're upgrading ap80x.dtsi to use a bus-width of 8, why keep the bus-
> width specifier of 8 in the board files?
[KP] The bus width is updated in A8040 DB DTS. This board utilizes 8-bit interface.
The armada-ap80x.dtsi file does not specifies the bus width since it is board-specific.
>
> This patch just doesn't make sense, and your responses to our points seem to
> add to the confusion.
[KP] I am sorry about it. Hope my last response clarifies it.
Kosta
>
> --
> RMK's Patch system: https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__www.armlinux.org.uk_developer_patches_&d=DwIBAg&c=nKjWec2b6R0
> mOyPaz7xtfQ&r=-
> N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=V27OOcgNqKN2
> WrlW2YFvHm_D_dXoP44wPd5zyOKvEBk&s=o3OrmStt1ZuXVNlYklTV_b1wY35
> NvPPrdLqwGgtxRZU&e=
> FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
2021-02-03 16:57 ` Kostya Porotchkin
@ 2021-02-05 9:33 ` Marcin Wojtas
0 siblings, 0 replies; 27+ messages in thread
From: Marcin Wojtas @ 2021-02-05 9:33 UTC (permalink / raw)
To: Kostya Porotchkin
Cc: Russell King - ARM Linux admin, Baruch Siach, linux-kernel,
devicetree, andrew, jaz, gregory.clement, Nadav Haklai, robh+dt,
Stefan Chulski, Ben Peled, sebastian.hesselbarth,
linux-arm-kernel
Hi Kosta,
Let me chime in.
śr., 3 lut 2021 o 17:57 Kostya Porotchkin <kostap@marvell.com> napisał(a):
>
> Hello, Russell,
> I agree that this patch needs rework.
> I will definitely do it and issue a new version.
>
> > On Wed, Feb 03, 2021 at 02:50:45PM +0000, Kostya Porotchkin wrote:
> > > [KP] So for older systems this "slow mode" parameter could be set on the
> > board level.
> > > When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR52, even
> > if they support HS400 on AP side.
> > > MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v"
> > flag set, so it should remain in low speed anyway.
> >
> > Your reasoning does not make sense.
> >
> > The ap80x.dtsi file does not specify "marvell,xenon-phy-slow-mode".
> > It is not specified at this level. It is already specified at board level.
> [KP] it does. In current armada-ap80x.dtsi File this specification is on row 260:
> ap_sdhci0: sdhci@6e0000 {
> compatible = "marvell,armada-ap806-sdhci";
> reg = <0x6e0000 0x300>;
> interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> clock-names = "core";
> clocks = <&ap_clk 4>;
> dma-coherent;
> marvell,xenon-phy-slow-mode;
> status = "disabled";
> };
> So I would like to remove this row.
>
> > Given that Macchiatobin will still use slow mode, why remove the
> > marvell,xenon-phy-slow-mode property from this file?
> [KP] Agree, I will keep this property in Macchiatobin DTS file.
>
Please do it another way around.
1. We need to leave the device tree bindings intact as much as
possible - specifically for Armada 7k8k changes in this area have
been causing enough problems in the past, breaking compatibility
between kernel revisions. Moving the property to board level can be
good here, but forces all other board dts files to adjust.
Unfortunately Linux is a source of truth for the arm64 device tree
bindings, but please note other OS's use those files as well - let's
minimize the impact for existing HW and drivers.
2. What I propose is to remove `marvell,xenon-phy-slow-mode` from
armada-ap80x.dtsi and add below in armada-ap806.dtsi:
&ap_sdhci0 {
marvell,xenon-phy-slow-mode;
};
This way AP807 becomes free from the unwanted slow mode setting. Also
any user of Armada 7k8k the B0 revision can add below to the board
file:
&ap_sdhci0 {
+ /delete-property/marvell,xenon-phy-slow-mode;
};
3. Contrary to the SDK version, sdhci-xenon.c is not capable of
checking the SoC revision. HS200 is disabled for all versions of AP806
there - I believe this place requires revisiting, to start relying
explicitly on the `marvell,xenon-phy-slow-mode` setting, rather than
the compatible string. I can handle this one.
4. Please move armada-8040-db.dts changes to a separate patch, please.
Thanks,
Marcin
> >
> > Also, if you're upgrading ap80x.dtsi to use a bus-width of 8, why keep the bus-
> > width specifier of 8 in the board files?
> [KP] The bus width is updated in A8040 DB DTS. This board utilizes 8-bit interface.
> The armada-ap80x.dtsi file does not specifies the bus width since it is board-specific.
>
> >
> > This patch just doesn't make sense, and your responses to our points seem to
> > add to the confusion.
> [KP] I am sorry about it. Hope my last response clarifies it.
>
> Kosta
> >
> > --
> > RMK's Patch system: https://urldefense.proofpoint.com/v2/url?u=https-
> > 3A__www.armlinux.org.uk_developer_patches_&d=DwIBAg&c=nKjWec2b6R0
> > mOyPaz7xtfQ&r=-
> > N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=V27OOcgNqKN2
> > WrlW2YFvHm_D_dXoP44wPd5zyOKvEBk&s=o3OrmStt1ZuXVNlYklTV_b1wY35
> > NvPPrdLqwGgtxRZU&e=
> > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
2021-02-03 13:31 ` [PATCH 01/11] fix: arm64: dts: replace wrong regulator on ap emmc kostap
2021-02-03 13:31 ` [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings kostap
@ 2021-02-03 13:31 ` kostap
2021-02-03 14:00 ` Baruch Siach
2021-02-03 14:28 ` Russell King - ARM Linux admin
2021-02-03 13:31 ` [PATCH 04/11] fix: dts: a8k: Add CP eMMC regulator and update device parameters kostap
` (7 subsequent siblings)
10 siblings, 2 replies; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Konstantin Porotchkin <kostap@marvell.com>
Add SDIO mode pin control configration for CP0 on A8K DB.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++++
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 293403a1a333..179218774ba9 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -47,6 +47,12 @@
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
+ sdhci_pins: sdhi-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61", "mpp62";
+ marvell,function = "sdio";
+ };
+
nand_pins: nand-pins {
marvell,pins =
"mpp15", "mpp16", "mpp17", "mpp18",
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index ee67c70bf02e..64100ae204da 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -70,6 +70,12 @@
&cp0_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
+
+ sdhci_pins: sdhi-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61", "mpp62";
+ marvell,function = "sdio";
+ };
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce
2021-02-03 13:31 ` [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce kostap
@ 2021-02-03 14:00 ` Baruch Siach
2021-02-03 14:39 ` [EXT] " Kostya Porotchkin
2021-02-03 14:28 ` Russell King - ARM Linux admin
1 sibling, 1 reply; 27+ messages in thread
From: Baruch Siach @ 2021-02-03 14:00 UTC (permalink / raw)
To: kostap
Cc: linux-kernel, devicetree, andrew, jaz, gregory.clement, linux,
nadavh, robh+dt, stefanc, mw, bpeled, sebastian.hesselbarth,
linux-arm-kernel
Hi Konstantin,
On Wed, Feb 03 2021, kostap@marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Add SDIO mode pin control configration for CP0 on A8K DB.
This patch does not touch the A8K DB device-tree file.
baruch
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> ---
> arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++++
> arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> index 293403a1a333..179218774ba9 100644
> --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> @@ -47,6 +47,12 @@
> cp0_pinctrl: pinctrl {
> compatible = "marvell,armada-7k-pinctrl";
>
> + sdhci_pins: sdhi-pins {
> + marvell,pins = "mpp56", "mpp57", "mpp58",
> + "mpp59", "mpp60", "mpp61", "mpp62";
> + marvell,function = "sdio";
> + };
> +
> nand_pins: nand-pins {
> marvell,pins =
> "mpp15", "mpp16", "mpp17", "mpp18",
> diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> index ee67c70bf02e..64100ae204da 100644
> --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> @@ -70,6 +70,12 @@
> &cp0_syscon0 {
> cp0_pinctrl: pinctrl {
> compatible = "marvell,armada-8k-cpm-pinctrl";
> +
> + sdhci_pins: sdhi-pins {
> + marvell,pins = "mpp56", "mpp57", "mpp58",
> + "mpp59", "mpp60", "mpp61", "mpp62";
> + marvell,function = "sdio";
> + };
> };
> };
--
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce
2021-02-03 14:00 ` Baruch Siach
@ 2021-02-03 14:39 ` Kostya Porotchkin
0 siblings, 0 replies; 27+ messages in thread
From: Kostya Porotchkin @ 2021-02-03 14:39 UTC (permalink / raw)
To: Baruch Siach
Cc: linux-kernel, devicetree, andrew, jaz, gregory.clement, linux,
Nadav Haklai, robh+dt, Stefan Chulski, mw, Ben Peled,
sebastian.hesselbarth, linux-arm-kernel
> -----Original Message-----
> From: Baruch Siach <baruch@tkos.co.il>
> Sent: Wednesday, February 3, 2021 16:01
> To: Kostya Porotchkin <kostap@marvell.com>
> Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> andrew@lunn.ch; jaz@semihalf.com; gregory.clement@bootlin.com;
> linux@armlinux.org.uk; Nadav Haklai <nadavh@marvell.com>;
> robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>;
> mw@semihalf.com; Ben Peled <bpeled@marvell.com>;
> sebastian.hesselbarth@gmail.com; linux-arm-kernel@lists.infradead.org
> Subject: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for
> SDIO interafce
>
> External Email
>
> ----------------------------------------------------------------------
> Hi Konstantin,
>
> On Wed, Feb 03 2021, kostap@marvell.com wrote:
> > From: Konstantin Porotchkin <kostap@marvell.com>
> >
> > Add SDIO mode pin control configration for CP0 on A8K DB.
>
> This patch does not touch the A8K DB device-tree file.
>
[KP] Right, it changes the SoC DTSI. I missed it when ported the patch.
Will fix in the next version
Kosta
> baruch
>
> >
> > Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> > ---
> > arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++++
> > arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++++++
> > 2 files changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > index 293403a1a333..179218774ba9 100644
> > --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > @@ -47,6 +47,12 @@
> > cp0_pinctrl: pinctrl {
> > compatible = "marvell,armada-7k-pinctrl";
> >
> > + sdhci_pins: sdhi-pins {
> > + marvell,pins = "mpp56", "mpp57", "mpp58",
> > + "mpp59", "mpp60", "mpp61", "mpp62";
> > + marvell,function = "sdio";
> > + };
> > +
> > nand_pins: nand-pins {
> > marvell,pins =
> > "mpp15", "mpp16", "mpp17", "mpp18", diff --git
> > a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > index ee67c70bf02e..64100ae204da 100644
> > --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > @@ -70,6 +70,12 @@
> > &cp0_syscon0 {
> > cp0_pinctrl: pinctrl {
> > compatible = "marvell,armada-8k-cpm-pinctrl";
> > +
> > + sdhci_pins: sdhi-pins {
> > + marvell,pins = "mpp56", "mpp57", "mpp58",
> > + "mpp59", "mpp60", "mpp61", "mpp62";
> > + marvell,function = "sdio";
> > + };
> > };
> > };
>
>
> --
> ~. .~ Tk Open Systems
> =}------------------------------------------------ooO--U--Ooo------------{=
> - baruch@tkos.co.il - tel: +972.52.368.4656,
> https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__www.tkos.co.il&d=DwIBAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=-
> N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=8Kz0ddezxxG41
> 9tiQOva_I9GUi6QZw9Pa6tRxYugqQw&s=Ky8dBlut-daLt2-
> 0j3BIwiBEBAVzKi8e9oJetRIzuPA&e= -
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce
2021-02-03 13:31 ` [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce kostap
2021-02-03 14:00 ` Baruch Siach
@ 2021-02-03 14:28 ` Russell King - ARM Linux admin
2021-02-03 14:41 ` [EXT] " Kostya Porotchkin
1 sibling, 1 reply; 27+ messages in thread
From: Russell King - ARM Linux admin @ 2021-02-03 14:28 UTC (permalink / raw)
To: kostap
Cc: linux-kernel, devicetree, linux-arm-kernel, robh+dt,
sebastian.hesselbarth, gregory.clement, andrew, mw, jaz, nadavh,
stefanc, bpeled
On Wed, Feb 03, 2021 at 03:31:30PM +0200, kostap@marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Add SDIO mode pin control configration for CP0 on A8K DB.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> ---
> arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++++
> arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> index 293403a1a333..179218774ba9 100644
> --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> @@ -47,6 +47,12 @@
> cp0_pinctrl: pinctrl {
> compatible = "marvell,armada-7k-pinctrl";
>
> + sdhci_pins: sdhi-pins {
sdhi-pins ?
> + marvell,pins = "mpp56", "mpp57", "mpp58",
> + "mpp59", "mpp60", "mpp61", "mpp62";
> + marvell,function = "sdio";
> + };
> +
> nand_pins: nand-pins {
> marvell,pins =
> "mpp15", "mpp16", "mpp17", "mpp18",
> diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> index ee67c70bf02e..64100ae204da 100644
> --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> @@ -70,6 +70,12 @@
> &cp0_syscon0 {
> cp0_pinctrl: pinctrl {
> compatible = "marvell,armada-8k-cpm-pinctrl";
> +
> + sdhci_pins: sdhi-pins {
sdhi-pins ?
> + marvell,pins = "mpp56", "mpp57", "mpp58",
> + "mpp59", "mpp60", "mpp61", "mpp62";
> + marvell,function = "sdio";
> + };
> };
> };
>
> --
> 2.17.1
>
>
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce
2021-02-03 14:28 ` Russell King - ARM Linux admin
@ 2021-02-03 14:41 ` Kostya Porotchkin
2021-02-03 15:41 ` Andrew Lunn
0 siblings, 1 reply; 27+ messages in thread
From: Kostya Porotchkin @ 2021-02-03 14:41 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: linux-kernel, devicetree, linux-arm-kernel, robh+dt,
sebastian.hesselbarth, gregory.clement, andrew, mw, jaz,
Nadav Haklai, Stefan Chulski, Ben Peled
Hu, Russel,
> -----Original Message-----
> From: Russell King - ARM Linux admin <linux@armlinux.org.uk>
> Sent: Wednesday, February 3, 2021 16:28
> To: Kostya Porotchkin <kostap@marvell.com>
> Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; robh+dt@kernel.org;
> sebastian.hesselbarth@gmail.com; gregory.clement@bootlin.com;
> andrew@lunn.ch; mw@semihalf.com; jaz@semihalf.com; Nadav Haklai
> <nadavh@marvell.com>; Stefan Chulski <stefanc@marvell.com>; Ben Peled
> <bpeled@marvell.com>
> Subject: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for
> SDIO interafce
>
> External Email
>
> ----------------------------------------------------------------------
> On Wed, Feb 03, 2021 at 03:31:30PM +0200, kostap@marvell.com wrote:
> > From: Konstantin Porotchkin <kostap@marvell.com>
> >
> > Add SDIO mode pin control configration for CP0 on A8K DB.
> >
> > Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> > ---
> > arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++++
> > arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++++++
> > 2 files changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > index 293403a1a333..179218774ba9 100644
> > --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > @@ -47,6 +47,12 @@
> > cp0_pinctrl: pinctrl {
> > compatible = "marvell,armada-7k-pinctrl";
> >
> > + sdhci_pins: sdhi-pins {
>
> sdhi-pins ?
>
[KP] You mean to replace the underline with dash?
Will do it in the next version, no problem.
> > + marvell,pins = "mpp56", "mpp57", "mpp58",
> > + "mpp59", "mpp60", "mpp61", "mpp62";
> > + marvell,function = "sdio";
> > + };
> > +
> > nand_pins: nand-pins {
> > marvell,pins =
> > "mpp15", "mpp16", "mpp17", "mpp18", diff --git
> > a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > index ee67c70bf02e..64100ae204da 100644
> > --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > @@ -70,6 +70,12 @@
> > &cp0_syscon0 {
> > cp0_pinctrl: pinctrl {
> > compatible = "marvell,armada-8k-cpm-pinctrl";
> > +
> > + sdhci_pins: sdhi-pins {
>
> sdhi-pins ?
>
> > + marvell,pins = "mpp56", "mpp57", "mpp58",
> > + "mpp59", "mpp60", "mpp61", "mpp62";
> > + marvell,function = "sdio";
> > + };
> > };
> > };
> >
> > --
> > 2.17.1
> >
> >
>
> --
> RMK's Patch system: https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__www.armlinux.org.uk_developer_patches_&d=DwIBAg&c=nKjWec2b6R0
> mOyPaz7xtfQ&r=-
> N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=wUA0mnqioCngi
> HLZcn2iOBuiWLQtawWb1yfozx_80C4&s=_yolpLSRiJi4CnA-
> iEzpbF5r77VBdLcM6pouXxTdupk&e=
> FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce
2021-02-03 14:41 ` [EXT] " Kostya Porotchkin
@ 2021-02-03 15:41 ` Andrew Lunn
2021-02-03 15:49 ` Kostya Porotchkin
0 siblings, 1 reply; 27+ messages in thread
From: Andrew Lunn @ 2021-02-03 15:41 UTC (permalink / raw)
To: Kostya Porotchkin
Cc: Russell King - ARM Linux admin, linux-kernel, devicetree,
linux-arm-kernel, robh+dt, sebastian.hesselbarth,
gregory.clement, mw, jaz, Nadav Haklai, Stefan Chulski,
Ben Peled
> > > + sdhci_pins: sdhi-pins {
> >
> > sdhi-pins ?
> >
> [KP] You mean to replace the underline with dash?
I think he would like a c added in the correct place.
Andrew
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce
2021-02-03 15:41 ` Andrew Lunn
@ 2021-02-03 15:49 ` Kostya Porotchkin
0 siblings, 0 replies; 27+ messages in thread
From: Kostya Porotchkin @ 2021-02-03 15:49 UTC (permalink / raw)
To: Andrew Lunn
Cc: Russell King - ARM Linux admin, linux-kernel, devicetree,
linux-arm-kernel, robh+dt, sebastian.hesselbarth,
gregory.clement, mw, jaz, Nadav Haklai, Stefan Chulski,
Ben Peled
> > > > + sdhci_pins: sdhi-pins {
> > >
> > > sdhi-pins ?
> > >
> > [KP] You mean to replace the underline with dash?
>
> I think he would like a c added in the correct place.
>
[KP] Ahh, now I see it. Thank you, Andrew!
Kosta
> Andrew
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 04/11] fix: dts: a8k: Add CP eMMC regulator and update device parameters
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
` (2 preceding siblings ...)
2021-02-03 13:31 ` [PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce kostap
@ 2021-02-03 13:31 ` kostap
2021-02-03 13:31 ` [PATCH 05/11] arm64: dts: marvell: armada-3720-db: add comphy references kostap
` (6 subsequent siblings)
10 siblings, 0 replies; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Konstantin Porotchkin <kostap@marvell.com>
Add GPIO regulator for controlling CP0 eMMC voltage (3.3V/1.8V)
Update CP0 SDHCI parameters in A7K/A8K boards DTS files.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 17 ++++++++++++++++-
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 18 +++++++++++++++++-
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index a7eb4e7697a2..f8179cadc610 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -28,6 +28,19 @@
ethernet2 = &cp0_eth2;
};
+ cp0_vccq_sd0_reg: cp0_vccq_sd0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0-vccq-sd0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ enable-active-high;
+ };
+
cp0_exp_usb3_0_current_regulator: gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "cp0-usb3-0-current-regulator";
@@ -253,8 +266,10 @@
&cp0_sdhci0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
bus-width = <4>;
- no-1-8-v;
+ vqmmc-supply = <&cp0_vccq_sd0_reg>;
cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 6362e654a823..d96aa9e9e61c 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -31,6 +31,19 @@
i2c2 = &cp1_i2c0;
};
+ cp0_vccq_sd0_reg: cp0_vccq_sd0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0-vccq-sd0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ enable-active-high;
+ };
+
cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "cp0-usb3h0-vbus";
@@ -362,6 +375,9 @@
&cp0_sdhci0 {
status = "okay";
- bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
+ bus-width = <4>;
+ vqmmc-supply = <&cp0_vccq_sd0_reg>;
non-removable;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 05/11] arm64: dts: marvell: armada-3720-db: add comphy references
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
` (3 preceding siblings ...)
2021-02-03 13:31 ` [PATCH 04/11] fix: dts: a8k: Add CP eMMC regulator and update device parameters kostap
@ 2021-02-03 13:31 ` kostap
2021-02-03 13:31 ` [PATCH 06/11] arm64: dts: marvell: armada-3270-espressobin: " kostap
` (5 subsequent siblings)
10 siblings, 0 replies; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Adding phy description to pcie, sata and usb will allow appropriate drivers
to configure marvell comphy-a3700 accordingly.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 3e5789f37206..15e923f945d4 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -132,11 +132,15 @@
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&comphy1 0>;
};
/* CON3 */
&sata {
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&comphy2 0>;
};
&sdhci0 {
@@ -217,4 +221,7 @@
&usb3 {
status = "okay";
usb-phy = <&usb3_phy>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&comphy0 0>;
+ phy-names = "usb";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 06/11] arm64: dts: marvell: armada-3270-espressobin: add comphy references
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
` (4 preceding siblings ...)
2021-02-03 13:31 ` [PATCH 05/11] arm64: dts: marvell: armada-3720-db: add comphy references kostap
@ 2021-02-03 13:31 ` kostap
2021-02-03 13:31 ` [PATCH 07/11] fix: ARM64: dts: cp110: Switch to 8-bit ECC NAND setting kostap
` (4 subsequent siblings)
10 siblings, 0 replies; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Add "phys" entries pointing to COMPHYs to PCIe and USB3 nodes
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
index daffe136c523..bbd955909813 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
@@ -59,6 +59,8 @@
/* J9 */
&pcie0 {
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&comphy1 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
@@ -139,6 +141,9 @@
/* J7 */
&usb3 {
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&comphy0 0>;
+ phy-names = "usb";
};
/* J8 */
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 07/11] fix: ARM64: dts: cp110: Switch to 8-bit ECC NAND setting
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
` (5 preceding siblings ...)
2021-02-03 13:31 ` [PATCH 06/11] arm64: dts: marvell: armada-3270-espressobin: " kostap
@ 2021-02-03 13:31 ` kostap
2021-02-03 13:31 ` [PATCH 08/11] arm64: dts: marvell: armada-3720-db: add eeprom description kostap
` (3 subsequent siblings)
10 siblings, 0 replies; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Konstantin Porotchkin <kostap@marvell.com>
All A7K/A8K boards are using NAND chip that supports
8 bit ECC strength. Using lower ECC strength is not recommended
by the flash manufacturer and may cause data corruption.
This patch changes the nand-ecc-strength value from 4 to 8.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 2 +-
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index f8179cadc610..39f1d393664f 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -169,7 +169,7 @@
label = "pxa3xx_nand-0";
nand-rb = <0>;
nand-on-flash-bbt;
- nand-ecc-strength = <4>;
+ nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
partitions {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index d96aa9e9e61c..04241dba189e 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -281,7 +281,7 @@
reg = <0>;
nand-rb = <0>;
nand-on-flash-bbt;
- nand-ecc-strength = <4>;
+ nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
partitions {
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 08/11] arm64: dts: marvell: armada-3720-db: add eeprom description
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
` (6 preceding siblings ...)
2021-02-03 13:31 ` [PATCH 07/11] fix: ARM64: dts: cp110: Switch to 8-bit ECC NAND setting kostap
@ 2021-02-03 13:31 ` kostap
2021-02-03 13:31 ` [PATCH 09/11] dts: a3700: enable dma coherence for PCIE interface kostap
` (2 subsequent siblings)
10 siblings, 0 replies; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Grzegorz Jaszczyk <jaz@semihalf.com>
On Armada 3720 board there is serial emprom M24C64 at address 0x57,
reflect it in device-tree.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 15e923f945d4..f2435537c1d3 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -113,6 +113,12 @@
compatible = "dallas,ds1337";
reg = <0x68>;
};
+
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <32>;
+ };
};
&mdio {
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 09/11] dts: a3700: enable dma coherence for PCIE interface
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
` (7 preceding siblings ...)
2021-02-03 13:31 ` [PATCH 08/11] arm64: dts: marvell: armada-3720-db: add eeprom description kostap
@ 2021-02-03 13:31 ` kostap
2021-02-05 9:45 ` Marcin Wojtas
2021-02-03 13:31 ` [PATCH 10/11] dts: marvell: add 2 eeprom properties to A8K DB device tree kostap
2021-02-03 13:31 ` [PATCH 11/11] dts: marvell: add 2 eeprom properties to A7K " kostap
10 siblings, 1 reply; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Stefan Chulski <stefanc@marvell.com>
Enavble PCIe dma coherence for A3700 platform
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index d5b6c0a1c54a..5c0df06bc707 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -486,6 +486,7 @@
#interrupt-cells = <1>;
msi-parent = <&pcie0>;
msi-controller;
+ dma-coherent;
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
interrupt-map-mask = <0 0 0 7>;
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 09/11] dts: a3700: enable dma coherence for PCIE interface
2021-02-03 13:31 ` [PATCH 09/11] dts: a3700: enable dma coherence for PCIE interface kostap
@ 2021-02-05 9:45 ` Marcin Wojtas
0 siblings, 0 replies; 27+ messages in thread
From: Marcin Wojtas @ 2021-02-05 9:45 UTC (permalink / raw)
To: Kostya Porotchkin
Cc: Linux Kernel Mailing List, devicetree, linux-arm-kernel,
Russell King - ARM Linux, Rob Herring, Sebastian Hesselbarth,
Grégory Clement, Andrew Lunn, Grzegorz Jaszczyk, nadavh,
Stefan Chulski, Ben Peled (בן פלד)
Hi Kosta,
śr., 3 lut 2021 o 14:32 <kostap@marvell.com> napisał(a):
>
> From: Stefan Chulski <stefanc@marvell.com>
>
> Enavble PCIe dma coherence for A3700 platform
>
While at it, can we also add:
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -71,6 +71,7 @@ soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
+ dma-coherent;
ranges;
internal-regs@d0000000 {
so that to enable it for all bus-attached interfaces? This safe and
will boost IO performance.
Thanks,
Marcin
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> ---
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> index d5b6c0a1c54a..5c0df06bc707 100644
> --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> @@ -486,6 +486,7 @@
> #interrupt-cells = <1>;
> msi-parent = <&pcie0>;
> msi-controller;
> + dma-coherent;
> ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
> 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
> interrupt-map-mask = <0 0 0 7>;
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 10/11] dts: marvell: add 2 eeprom properties to A8K DB device tree
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
` (8 preceding siblings ...)
2021-02-03 13:31 ` [PATCH 09/11] dts: a3700: enable dma coherence for PCIE interface kostap
@ 2021-02-03 13:31 ` kostap
2021-02-03 13:31 ` [PATCH 11/11] dts: marvell: add 2 eeprom properties to A7K " kostap
10 siblings, 0 replies; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Ben Peled <bpeled@marvell.com>
Add on-board i2c EEPROMs U41 and U51
Signed-off-by: Ben Peled <bpeled@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 04241dba189e..13964193fb77 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -150,6 +150,19 @@
reg = <0x25>;
};
+ /* U51 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U41 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
};
/* CON4 on CP0 expansion */
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 11/11] dts: marvell: add 2 eeprom properties to A7K DB device tree
2021-02-03 13:31 [PATCH 00/11] Device tree fixes for Armada family kostap
` (9 preceding siblings ...)
2021-02-03 13:31 ` [PATCH 10/11] dts: marvell: add 2 eeprom properties to A8K DB device tree kostap
@ 2021-02-03 13:31 ` kostap
10 siblings, 0 replies; 27+ messages in thread
From: kostap @ 2021-02-03 13:31 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: linux, robh+dt, sebastian.hesselbarth, gregory.clement, andrew,
mw, jaz, nadavh, stefanc, bpeled, Konstantin Porotchkin
From: Ben Peled <bpeled@marvell.com>
Add on-board i2c EEPROMs U37 and U38
Signed-off-by: Ben Peled <bpeled@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 39f1d393664f..c8258defa9e5 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -152,6 +152,20 @@
* IO0_7: IO1_7: SDIO_Vcntrl
*/
};
+
+ /* U38 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U37 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
};
&cp0_nand_controller {
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread