* [PATCH v2 1/4] arm64: dts: ti: k3-am64-main: Add CPSW DT node
2021-03-04 21:10 [PATCH v2 0/4] arm64: dts: ti: am642x: add CPSW3g DT nodes Grygorii Strashko
@ 2021-03-04 21:10 ` Grygorii Strashko
2021-03-04 21:10 ` [PATCH v2 2/4] arm64: dts: ti: k3-am64-main: add main CPTS entry Grygorii Strashko
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Grygorii Strashko @ 2021-03-04 21:10 UTC (permalink / raw)
To: Nishanth Menon, devicetree, linux-arm-kernel,
Vignesh Raghavendra, Lokesh Vutla
Cc: linux-kernel, Rob Herring, Kishon Vijay Abraham I, Tero Kristo,
Grygorii Strashko
From: Vignesh Raghavendra <vigneshr@ti.com>
Add CPSW3g DT node with two external ports, MDIO and CPTS support. For
CPSW3g DMA channels the ASEL is set to 15 (AM642x per DMA channel coherency
feature), so that CPSW DMA channel participates in Coherency and thus avoid
need to cache maintenance for SKBs. This improves bidirectional TCP
performance by up to 100Mbps (on 1G link).
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 74 ++++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 2 +
2 files changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 5f85950daef7..80443dbf272c 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -178,6 +178,12 @@
compatible = "ti,am654-chipid";
reg = <0x00000014 0x4>;
};
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
};
main_uart0: serial@2800000 {
@@ -402,4 +408,72 @@
ti,otap-del-sel-ddr50 = <0x9>;
ti,clkbuf-sel = <0x7>;
};
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x8000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 1>;
+ assigned-clock-parents = <&k3_clks 13 9>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_pktdma 0xC500 15>,
+ <&main_pktdma 0xC501 15>,
+ <&main_pktdma 0xC502 15>,
+ <&main_pktdma 0xC503 15>,
+ <&main_pktdma 0xC504 15>,
+ <&main_pktdma 0xC505 15>,
+ <&main_pktdma 0xC506 15>,
+ <&main_pktdma 0xC507 15>,
+ <&main_pktdma 0x4500 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 de ad be ef];
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 01 de ad be ef];
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 13 1>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
index 0ae8c844c482..de6805b0c72c 100644
--- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -28,6 +28,8 @@
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
};
chosen { };
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 2/4] arm64: dts: ti: k3-am64-main: add main CPTS entry
2021-03-04 21:10 [PATCH v2 0/4] arm64: dts: ti: am642x: add CPSW3g DT nodes Grygorii Strashko
2021-03-04 21:10 ` [PATCH v2 1/4] arm64: dts: ti: k3-am64-main: Add CPSW DT node Grygorii Strashko
@ 2021-03-04 21:10 ` Grygorii Strashko
2021-03-04 21:10 ` [PATCH v2 3/4] arm64: dts: ti: k3-am642-evm: add CPSW3g DT nodes Grygorii Strashko
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Grygorii Strashko @ 2021-03-04 21:10 UTC (permalink / raw)
To: Nishanth Menon, devicetree, linux-arm-kernel,
Vignesh Raghavendra, Lokesh Vutla
Cc: linux-kernel, Rob Herring, Kishon Vijay Abraham I, Tero Kristo,
Grygorii Strashko
Add DT node for the Main domain CPTS.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 80443dbf272c..0cf727e3d1e2 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -476,4 +476,19 @@
ti,cpts-periodic-outputs = <2>;
};
};
+
+ cpts@39000000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x39000000 0x0 0x400>;
+ reg-names = "cpts";
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 84 0>;
+ clock-names = "cpts";
+ assigned-clocks = <&k3_clks 84 0>;
+ assigned-clock-parents = <&k3_clks 84 8>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-periodic-outputs = <6>;
+ ti,cpts-ext-ts-inputs = <8>;
+ };
};
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 3/4] arm64: dts: ti: k3-am642-evm: add CPSW3g DT nodes
2021-03-04 21:10 [PATCH v2 0/4] arm64: dts: ti: am642x: add CPSW3g DT nodes Grygorii Strashko
2021-03-04 21:10 ` [PATCH v2 1/4] arm64: dts: ti: k3-am64-main: Add CPSW DT node Grygorii Strashko
2021-03-04 21:10 ` [PATCH v2 2/4] arm64: dts: ti: k3-am64-main: add main CPTS entry Grygorii Strashko
@ 2021-03-04 21:10 ` Grygorii Strashko
2021-03-04 21:10 ` [PATCH v2 4/4] arm64: dts: ti: k3-am642-sk: Add CPSW " Grygorii Strashko
2021-03-09 14:51 ` [PATCH v2 0/4] arm64: dts: ti: am642x: add CPSW3g " Nishanth Menon
4 siblings, 0 replies; 6+ messages in thread
From: Grygorii Strashko @ 2021-03-04 21:10 UTC (permalink / raw)
To: Nishanth Menon, devicetree, linux-arm-kernel,
Vignesh Raghavendra, Lokesh Vutla
Cc: linux-kernel, Rob Herring, Kishon Vijay Abraham I, Tero Kristo,
Grygorii Strashko
From: Vignesh Raghavendra <vigneshr@ti.com>
On am642-evm the CPSW3g ext. Port1 is directly connected to TI DP83867 PHY
and Port2 is connected to TI DP83869 PHY which is shared with ICSS
subsystem. The TI DP83869 PHY MII interface is configured using pinmux for
CPSW3g, while MDIO bus is connected through GPIO controllable 2:1 TMUX154E
switch (MDIO GPIO MUX) which has to be configured to route MDIO bus from
CPSW3g to TI DP83869 PHY.
Hence add networking support for am642-evm:
- add CPSW3g MDIO and RGMII pinmux entries for both ext. ports;
- add CPSW3g nodes;
- add mdio-mux-multiplexer DT nodes to represent above topology.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 93 +++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 1f1787750fef..962ef807e286 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
/ {
@@ -101,6 +103,31 @@
default-state = "off";
};
};
+
+ mdio_mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ mdio-mux-1 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mdio_mux>;
+ mdio-parent-bus = <&cpsw3g_mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw3g_phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
+ };
};
&main_pmx0 {
@@ -133,6 +160,47 @@
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
+
+ mdio1_pins_default: mdio1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
+ AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
+ AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
+ AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
+ AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
+ AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
+ AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+ AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+ AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+ AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+ >;
+ };
+
+ rgmii2_pins_default: rgmii2-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+ AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+ >;
+ };
};
&main_uart0 {
@@ -244,3 +312,28 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default
+ &rgmii1_pins_default
+ &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy3>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 4/4] arm64: dts: ti: k3-am642-sk: Add CPSW DT nodes
2021-03-04 21:10 [PATCH v2 0/4] arm64: dts: ti: am642x: add CPSW3g DT nodes Grygorii Strashko
` (2 preceding siblings ...)
2021-03-04 21:10 ` [PATCH v2 3/4] arm64: dts: ti: k3-am642-evm: add CPSW3g DT nodes Grygorii Strashko
@ 2021-03-04 21:10 ` Grygorii Strashko
2021-03-09 14:51 ` [PATCH v2 0/4] arm64: dts: ti: am642x: add CPSW3g " Nishanth Menon
4 siblings, 0 replies; 6+ messages in thread
From: Grygorii Strashko @ 2021-03-04 21:10 UTC (permalink / raw)
To: Nishanth Menon, devicetree, linux-arm-kernel,
Vignesh Raghavendra, Lokesh Vutla
Cc: linux-kernel, Rob Herring, Kishon Vijay Abraham I, Tero Kristo,
Grygorii Strashko
From: Vignesh Raghavendra <vigneshr@ti.com>
AM642 SK board has 2 CPSW3g ports connected through TI DP83867 PHYs. Add DT
entries for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 73 ++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index aa6ca4c49153..397ed3b2e121 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
/ {
@@ -90,6 +91,47 @@
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
+
+ mdio1_pins_default: mdio1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
+ AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
+ AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
+ AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
+ AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
+ AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
+ AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+ AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+ AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+ AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+ >;
+ };
+
+ rgmii2_pins_default: rgmii2-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+ AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+ >;
+ };
};
&mcu_uart0 {
@@ -171,3 +213,34 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default
+ &rgmii1_pins_default
+ &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v2 0/4] arm64: dts: ti: am642x: add CPSW3g DT nodes
2021-03-04 21:10 [PATCH v2 0/4] arm64: dts: ti: am642x: add CPSW3g DT nodes Grygorii Strashko
` (3 preceding siblings ...)
2021-03-04 21:10 ` [PATCH v2 4/4] arm64: dts: ti: k3-am642-sk: Add CPSW " Grygorii Strashko
@ 2021-03-09 14:51 ` Nishanth Menon
4 siblings, 0 replies; 6+ messages in thread
From: Nishanth Menon @ 2021-03-09 14:51 UTC (permalink / raw)
To: Grygorii Strashko
Cc: devicetree, linux-arm-kernel, Vignesh Raghavendra, Lokesh Vutla,
linux-kernel, Rob Herring, Kishon Vijay Abraham I, Tero Kristo
On 23:10-20210304, Grygorii Strashko wrote:
> Hi
>
> This series adds corresponding AM642x CPSW3g nodes required to enable networking
> on TI am642-evm/sk platforms and adds required pinmux/PHY nodes in corresponding
> board files.
>
> Kernel Boot Log:
> EVM: https://pastebin.ubuntu.com/p/6Qkbw35Jg3/
> SK: https://pastebin.ubuntu.com/p/Pd3xxP9J9K/
>
> Changes in v2:
> - minor comment fixed
> - add Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
>
> v1: https://lore.kernel.org/patchwork/cover/1389305/
>
> Grygorii Strashko (1):
> arm64: dts: ti: k3-am64-main: add main CPTS entry
>
Thanks, applied to ti-k3-dts-next.
PS: my -next branches are being rebased to 5.12-rc2 to keep a future bisect
clean.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 6+ messages in thread