* [PATCH] x86/apic: Rudimentary typo fixes
@ 2021-03-24 13:41 Bhaskar Chowdhury
2021-03-24 17:49 ` Randy Dunlap
2021-03-25 14:05 ` Ingo Molnar
0 siblings, 2 replies; 3+ messages in thread
From: Bhaskar Chowdhury @ 2021-03-24 13:41 UTC (permalink / raw)
To: tglx, mingo, bp, x86, hpa, dwmw, luto, dave.hansen, linux-kernel
Cc: rdunlap, Bhaskar Chowdhury
s/preferrable/preferable/
s/serivced/serviced/
s/distributon/distribution/
Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
---
arch/x86/kernel/apic/apic.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index bda4f2a36868..e26ee6e67f47 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -619,7 +619,7 @@ static void setup_APIC_timer(void)
if (this_cpu_has(X86_FEATURE_ARAT)) {
lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
- /* Make LAPIC timer preferrable over percpu HPET */
+ /* Make LAPIC timer preferable over percpu HPET */
lapic_clockevent.rating = 150;
}
@@ -1532,7 +1532,7 @@ static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
* Most probably by now the CPU has serviced that pending interrupt and it
* might not have done the ack_APIC_irq() because it thought, interrupt
* came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
- * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
+ * the ISR bit and cpu thinks it has already serviced the interrupt. Hence
* a vector might get locked. It was noticed for timer irq (vector
* 0x31). Issue an extra EOI to clear ISR.
*
@@ -1657,7 +1657,7 @@ static void setup_local_APIC(void)
*/
/*
* Actually disabling the focus CPU check just makes the hang less
- * frequent as it makes the interrupt distributon model be more
+ * frequent as it makes the interrupt distribution model be more
* like LRU than MRU (the short-term load is more even across CPUs).
*/
--
2.30.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] x86/apic: Rudimentary typo fixes
2021-03-24 13:41 [PATCH] x86/apic: Rudimentary typo fixes Bhaskar Chowdhury
@ 2021-03-24 17:49 ` Randy Dunlap
2021-03-25 14:05 ` Ingo Molnar
1 sibling, 0 replies; 3+ messages in thread
From: Randy Dunlap @ 2021-03-24 17:49 UTC (permalink / raw)
To: Bhaskar Chowdhury, tglx, mingo, bp, x86, hpa, dwmw, luto,
dave.hansen, linux-kernel
On 3/24/21 6:41 AM, Bhaskar Chowdhury wrote:
>
> s/preferrable/preferable/
> s/serivced/serviced/
> s/distributon/distribution/
>
> Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
> ---
> arch/x86/kernel/apic/apic.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index bda4f2a36868..e26ee6e67f47 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -619,7 +619,7 @@ static void setup_APIC_timer(void)
>
> if (this_cpu_has(X86_FEATURE_ARAT)) {
> lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
> - /* Make LAPIC timer preferrable over percpu HPET */
> + /* Make LAPIC timer preferable over percpu HPET */
> lapic_clockevent.rating = 150;
> }
>
> @@ -1532,7 +1532,7 @@ static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
> * Most probably by now the CPU has serviced that pending interrupt and it
> * might not have done the ack_APIC_irq() because it thought, interrupt
> * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
> - * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
> + * the ISR bit and cpu thinks it has already serviced the interrupt. Hence
> * a vector might get locked. It was noticed for timer irq (vector
> * 0x31). Issue an extra EOI to clear ISR.
> *
> @@ -1657,7 +1657,7 @@ static void setup_local_APIC(void)
> */
> /*
> * Actually disabling the focus CPU check just makes the hang less
> - * frequent as it makes the interrupt distributon model be more
> + * frequent as it makes the interrupt distribution model be more
> * like LRU than MRU (the short-term load is more even across CPUs).
> */
>
> --
--
~Randy
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] x86/apic: Rudimentary typo fixes
2021-03-24 13:41 [PATCH] x86/apic: Rudimentary typo fixes Bhaskar Chowdhury
2021-03-24 17:49 ` Randy Dunlap
@ 2021-03-25 14:05 ` Ingo Molnar
1 sibling, 0 replies; 3+ messages in thread
From: Ingo Molnar @ 2021-03-25 14:05 UTC (permalink / raw)
To: Bhaskar Chowdhury
Cc: tglx, mingo, bp, x86, hpa, dwmw, luto, dave.hansen, linux-kernel,
rdunlap
* Bhaskar Chowdhury <unixbhaskar@gmail.com> wrote:
> s/preferrable/preferable/
> s/serivced/serviced/
> s/distributon/distribution/
>
> Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
> ---
> arch/x86/kernel/apic/apic.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index bda4f2a36868..e26ee6e67f47 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -619,7 +619,7 @@ static void setup_APIC_timer(void)
>
> if (this_cpu_has(X86_FEATURE_ARAT)) {
> lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
> - /* Make LAPIC timer preferrable over percpu HPET */
> + /* Make LAPIC timer preferable over percpu HPET */
> lapic_clockevent.rating = 150;
> }
>
> @@ -1532,7 +1532,7 @@ static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
> * Most probably by now the CPU has serviced that pending interrupt and it
> * might not have done the ack_APIC_irq() because it thought, interrupt
> * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
> - * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
> + * the ISR bit and cpu thinks it has already serviced the interrupt. Hence
> * a vector might get locked. It was noticed for timer irq (vector
> * 0x31). Issue an extra EOI to clear ISR.
> *
> @@ -1657,7 +1657,7 @@ static void setup_local_APIC(void)
> */
> /*
> * Actually disabling the focus CPU check just makes the hang less
> - * frequent as it makes the interrupt distributon model be more
> + * frequent as it makes the interrupt distribution model be more
> * like LRU than MRU (the short-term load is more even across CPUs).
> */
This and many more comment typos are already fixed in the latest x86
tree, which you can find at:
git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
Thanks,
Ingo
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-03-25 14:06 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-24 13:41 [PATCH] x86/apic: Rudimentary typo fixes Bhaskar Chowdhury
2021-03-24 17:49 ` Randy Dunlap
2021-03-25 14:05 ` Ingo Molnar
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).