From: kernel test robot <lkp@intel.com>
To: Dan Williams <dan.j.williams@intel.com>, linux-cxl@vger.kernel.org
Cc: kbuild-all@lists.01.org, linux-pci@vger.kernel.org,
linux-acpi@vger.kernel.org, ira.weiny@intel.com,
vishal.l.verma@intel.com, alison.schofield@intel.com,
ben.widawsky@intel.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/8] cxl/core: Refactor CXL register lookup for bridge reuse
Date: Fri, 26 Mar 2021 09:11:34 +0800 [thread overview]
Message-ID: <202103260957.6Ec3O6Cz-lkp@intel.com> (raw)
In-Reply-To: <161662144627.1723715.7776509014834832493.stgit@dwillia2-desk3.amr.corp.intel.com>
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Hi Dan,
I love your patch! Yet something to improve:
[auto build test ERROR on a38fd8748464831584a19438cbb3082b5a2dab15]
url: https://github.com/0day-ci/linux/commits/Dan-Williams/CXL-Port-Enumeration/20210325-053311
base: a38fd8748464831584a19438cbb3082b5a2dab15
config: arc-randconfig-r014-20210325 (attached as .config)
compiler: arceb-elf-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/efa27967ffcd67a6109c23987e76b9ed2e97ae27
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Dan-Williams/CXL-Port-Enumeration/20210325-053311
git checkout efa27967ffcd67a6109c23987e76b9ed2e97ae27
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/cxl/core.c: In function 'cxl_setup_device_regs':
>> drivers/cxl/core.c:27:14: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Werror=implicit-function-declaration]
27 | cap_array = readq(base + CXLDEV_CAP_ARRAY_OFFSET);
| ^~~~~
| readb
cc1: some warnings being treated as errors
vim +27 drivers/cxl/core.c
6
7 /**
8 * DOC: cxl core
9 *
10 * The CXL core provides a sysfs hierarchy for control devices and a rendezvous
11 * point for cross-device interleave coordination through cxl ports.
12 */
13
14 /*
15 * cxl_setup_device_regs() - Detect CXL Device register blocks
16 * @dev: Host device of the @base mapping
17 * @base: mapping of CXL 2.0 8.2.8 CXL Device Register Interface
18 */
19 void cxl_setup_device_regs(struct device *dev, void __iomem *base,
20 struct cxl_device_regs *regs)
21 {
22 int cap, cap_count;
23 u64 cap_array;
24
25 *regs = (struct cxl_device_regs) { 0 };
26
> 27 cap_array = readq(base + CXLDEV_CAP_ARRAY_OFFSET);
28 if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) !=
29 CXLDEV_CAP_ARRAY_CAP_ID)
30 return;
31
32 cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array);
33
34 for (cap = 1; cap <= cap_count; cap++) {
35 void __iomem *register_block;
36 u32 offset;
37 u16 cap_id;
38
39 cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK,
40 readl(base + cap * 0x10));
41 offset = readl(base + cap * 0x10 + 0x4);
42 register_block = base + offset;
43
44 switch (cap_id) {
45 case CXLDEV_CAP_CAP_ID_DEVICE_STATUS:
46 dev_dbg(dev, "found Status capability (0x%x)\n", offset);
47 regs->status = register_block;
48 break;
49 case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX:
50 dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset);
51 regs->mbox = register_block;
52 break;
53 case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX:
54 dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset);
55 break;
56 case CXLDEV_CAP_CAP_ID_MEMDEV:
57 dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset);
58 regs->memdev = register_block;
59 break;
60 default:
61 dev_dbg(dev, "Unknown cap ID: %d (0x%x)\n", cap_id, offset);
62 break;
63 }
64 }
65 }
66 EXPORT_SYMBOL_GPL(cxl_setup_device_regs);
67
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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next prev parent reply other threads:[~2021-03-26 1:13 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-24 21:30 [PATCH 0/8] CXL Port Enumeration Dan Williams
2021-03-24 21:30 ` [PATCH 1/8] cxl/mem: Move some definitions to mem.h Dan Williams
2021-03-24 21:30 ` [PATCH 2/8] cxl/mem: Introduce 'struct cxl_regs' Dan Williams
2021-03-25 8:15 ` Christoph Hellwig
2021-03-29 19:01 ` Williams, Dan J
2021-03-24 21:30 ` [PATCH 3/8] cxl/core: Rename bus.c to core.c Dan Williams
2021-03-24 21:30 ` [PATCH 4/8] cxl/core: Refactor CXL register lookup for bridge reuse Dan Williams
2021-03-26 1:11 ` kernel test robot [this message]
2021-03-24 21:30 ` [PATCH 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root Dan Williams
2021-03-24 21:30 ` [PATCH 6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS Dan Williams
2021-03-24 21:31 ` [PATCH 7/8] cxl/port: Introduce cxl_port objects Dan Williams
2021-03-24 21:31 ` [PATCH 8/8] cxl/acpi: Add module parameters to stand in for ACPI tables Dan Williams
2021-05-07 22:51 [PATCH v3 0/8] CXL Port Enumeration and Plans for v5.14 Dan Williams
2021-05-07 22:51 ` [PATCH 4/8] cxl/core: Refactor CXL register lookup for bridge reuse Dan Williams
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