* [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600
@ 2021-03-30 10:06 Lecopzer Chen
2021-03-30 10:33 ` Marc Zyngier
0 siblings, 1 reply; 6+ messages in thread
From: Lecopzer Chen @ 2021-03-30 10:06 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, tglx, maz
Cc: julien.thierry, lecopzer, yj.chiang, Lecopzer Chen
When pseudo-NMI enabled, register_nmi() set priority of specific IRQ
by byte ops, and this doesn't work in GIC-600.
We have asked ARM Support [1]:
> Please refer to following description in
> "2.1.2 Distributor ACE-Lite slave interface" of GIC-600 TRM for
> the GIC600 ACE-lite slave interface supported sizes:
> "The GIC-600 only accepts single beat accesses of the sizes for
> each register that are shown in the Programmers model,
> see Chapter 4 Programmer's model on page 4-102.
> All other accesses are rejected and given either an
> OKAY or SLVERR response that is based on the GICT_ERR0CTLR.UE bit.".
Thus the register needs to be written by double word operation and
the step will be: read 32bit, set byte and write it back.
[1] https://services.arm.com/support/s/case/5003t00001L4Pba
Signed-off-by: Lecopzer Chen <lecopzer.chen@mediatek.com>
---
drivers/irqchip/irq-gic-v3.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index eb0ee356a629..cfc5a6ad30dc 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -440,10 +440,21 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio)
{
void __iomem *base = gic_dist_base(d);
u32 offset, index;
+ u32 val, prio_offset_mask, prio_offset_shift;
offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
- writeb_relaxed(prio, base + offset + index);
+ /*
+ * GIC-600 memory mapping register doesn't support byte opteration,
+ * thus read 32-bits from register, set bytes and wtire back to it.
+ */
+ prio_offset_shift = (index & 0x3) * 8;
+ prio_offset_mask = GENMASK(prio_offset_shift + 7, prio_offset_shift);
+ index &= ~0x3;
+ val = readl_relaxed(base + offset + index);
+ val &= ~prio_offset_mask;
+ val |= prio << prio_offset_shift;
+ writel_relaxed(val, base + offset + index);
}
static u32 gic_get_ppi_index(struct irq_data *d)
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600
2021-03-30 10:06 [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600 Lecopzer Chen
@ 2021-03-30 10:33 ` Marc Zyngier
2021-03-30 11:05 ` Lorenzo Pieralisi
0 siblings, 1 reply; 6+ messages in thread
From: Marc Zyngier @ 2021-03-30 10:33 UTC (permalink / raw)
To: Lecopzer Chen
Cc: linux-kernel, linux-arm-kernel, tglx, lecopzer, yj.chiang,
Lorenzo Pieralisi, Julien Thierry
[+Lorenzo, +Julien on an actual email address]
On Tue, 30 Mar 2021 11:06:19 +0100,
Lecopzer Chen <lecopzer.chen@mediatek.com> wrote:
>
> When pseudo-NMI enabled, register_nmi() set priority of specific IRQ
> by byte ops, and this doesn't work in GIC-600.
>
> We have asked ARM Support [1]:
> > Please refer to following description in
> > "2.1.2 Distributor ACE-Lite slave interface" of GIC-600 TRM for
> > the GIC600 ACE-lite slave interface supported sizes:
> > "The GIC-600 only accepts single beat accesses of the sizes for
> > each register that are shown in the Programmers model,
> > see Chapter 4 Programmer's model on page 4-102.
> > All other accesses are rejected and given either an
> > OKAY or SLVERR response that is based on the GICT_ERR0CTLR.UE bit.".
>
> Thus the register needs to be written by double word operation and
> the step will be: read 32bit, set byte and write it back.
>
> [1] https://services.arm.com/support/s/case/5003t00001L4Pba
You do realise that this link:
- is unusable for most people as it is behind a registration interface
- discloses confidential information to other people
I strongly suggest you stop posting such links.
>
> Signed-off-by: Lecopzer Chen <lecopzer.chen@mediatek.com>
> ---
> drivers/irqchip/irq-gic-v3.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index eb0ee356a629..cfc5a6ad30dc 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -440,10 +440,21 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio)
> {
> void __iomem *base = gic_dist_base(d);
> u32 offset, index;
> + u32 val, prio_offset_mask, prio_offset_shift;
>
> offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
>
> - writeb_relaxed(prio, base + offset + index);
> + /*
> + * GIC-600 memory mapping register doesn't support byte opteration,
> + * thus read 32-bits from register, set bytes and wtire back to it.
> + */
> + prio_offset_shift = (index & 0x3) * 8;
> + prio_offset_mask = GENMASK(prio_offset_shift + 7, prio_offset_shift);
> + index &= ~0x3;
> + val = readl_relaxed(base + offset + index);
> + val &= ~prio_offset_mask;
> + val |= prio << prio_offset_shift;
> + writel_relaxed(val, base + offset + index);
> }
>
> static u32 gic_get_ppi_index(struct irq_data *d)
From the architecture spec:
<quote>
11.1.3 GIC memory-mapped register access
In any system, access to the following registers must be supported:
[...]
* Byte accesses to:
- GICD_IPRIORITYR<n>.
- GICD_ITARGETSR<n>.
- GICD_SPENDSGIR<n>.
- GICD_CPENDSGIR<n>.
- GICR_IPRIORITYR<n>.
</quote>
So if GIC600 doesn't follow this architectural requirement, this is a
HW erratum, and I want an actual description of the HW issue together
with an erratum number.
Lorenzo, can you please investigate on your side?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600
2021-03-30 10:33 ` Marc Zyngier
@ 2021-03-30 11:05 ` Lorenzo Pieralisi
2021-03-30 13:06 ` Lorenzo Pieralisi
0 siblings, 1 reply; 6+ messages in thread
From: Lorenzo Pieralisi @ 2021-03-30 11:05 UTC (permalink / raw)
To: Marc Zyngier
Cc: Lecopzer Chen, linux-kernel, linux-arm-kernel, tglx, lecopzer,
yj.chiang, Julien Thierry
On Tue, Mar 30, 2021 at 11:33:13AM +0100, Marc Zyngier wrote:
> [+Lorenzo, +Julien on an actual email address]
>
> On Tue, 30 Mar 2021 11:06:19 +0100,
> Lecopzer Chen <lecopzer.chen@mediatek.com> wrote:
> >
> > When pseudo-NMI enabled, register_nmi() set priority of specific IRQ
> > by byte ops, and this doesn't work in GIC-600.
> >
> > We have asked ARM Support [1]:
> > > Please refer to following description in
> > > "2.1.2 Distributor ACE-Lite slave interface" of GIC-600 TRM for
> > > the GIC600 ACE-lite slave interface supported sizes:
> > > "The GIC-600 only accepts single beat accesses of the sizes for
> > > each register that are shown in the Programmers model,
> > > see Chapter 4 Programmer's model on page 4-102.
> > > All other accesses are rejected and given either an
> > > OKAY or SLVERR response that is based on the GICT_ERR0CTLR.UE bit.".
> >
> > Thus the register needs to be written by double word operation and
> > the step will be: read 32bit, set byte and write it back.
> >
> > [1] https://services.arm.com/support/s/case/5003t00001L4Pba
>
> You do realise that this link:
>
> - is unusable for most people as it is behind a registration interface
> - discloses confidential information to other people
>
> I strongly suggest you stop posting such links.
>
> >
> > Signed-off-by: Lecopzer Chen <lecopzer.chen@mediatek.com>
> > ---
> > drivers/irqchip/irq-gic-v3.c | 13 ++++++++++++-
> > 1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> > index eb0ee356a629..cfc5a6ad30dc 100644
> > --- a/drivers/irqchip/irq-gic-v3.c
> > +++ b/drivers/irqchip/irq-gic-v3.c
> > @@ -440,10 +440,21 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio)
> > {
> > void __iomem *base = gic_dist_base(d);
> > u32 offset, index;
> > + u32 val, prio_offset_mask, prio_offset_shift;
> >
> > offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
> >
> > - writeb_relaxed(prio, base + offset + index);
> > + /*
> > + * GIC-600 memory mapping register doesn't support byte opteration,
> > + * thus read 32-bits from register, set bytes and wtire back to it.
> > + */
> > + prio_offset_shift = (index & 0x3) * 8;
> > + prio_offset_mask = GENMASK(prio_offset_shift + 7, prio_offset_shift);
> > + index &= ~0x3;
> > + val = readl_relaxed(base + offset + index);
> > + val &= ~prio_offset_mask;
> > + val |= prio << prio_offset_shift;
> > + writel_relaxed(val, base + offset + index);
> > }
> >
> > static u32 gic_get_ppi_index(struct irq_data *d)
>
> From the architecture spec:
>
> <quote>
> 11.1.3 GIC memory-mapped register access
>
> In any system, access to the following registers must be supported:
>
> [...]
> * Byte accesses to:
> - GICD_IPRIORITYR<n>.
> - GICD_ITARGETSR<n>.
> - GICD_SPENDSGIR<n>.
> - GICD_CPENDSGIR<n>.
> - GICR_IPRIORITYR<n>.
> </quote>
>
> So if GIC600 doesn't follow this architectural requirement, this is a
> HW erratum, and I want an actual description of the HW issue together
> with an erratum number.
>
> Lorenzo, can you please investigate on your side?
Sure - I will look into it and report back.
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600
2021-03-30 11:05 ` Lorenzo Pieralisi
@ 2021-03-30 13:06 ` Lorenzo Pieralisi
2021-03-30 14:11 ` Marc Zyngier
0 siblings, 1 reply; 6+ messages in thread
From: Lorenzo Pieralisi @ 2021-03-30 13:06 UTC (permalink / raw)
To: Marc Zyngier
Cc: Lecopzer Chen, linux-kernel, linux-arm-kernel, tglx, lecopzer,
yj.chiang, Julien Thierry
On Tue, Mar 30, 2021 at 12:05:46PM +0100, Lorenzo Pieralisi wrote:
> On Tue, Mar 30, 2021 at 11:33:13AM +0100, Marc Zyngier wrote:
> > [+Lorenzo, +Julien on an actual email address]
> >
> > On Tue, 30 Mar 2021 11:06:19 +0100,
> > Lecopzer Chen <lecopzer.chen@mediatek.com> wrote:
> > >
> > > When pseudo-NMI enabled, register_nmi() set priority of specific IRQ
> > > by byte ops, and this doesn't work in GIC-600.
> > >
> > > We have asked ARM Support [1]:
> > > > Please refer to following description in
> > > > "2.1.2 Distributor ACE-Lite slave interface" of GIC-600 TRM for
> > > > the GIC600 ACE-lite slave interface supported sizes:
> > > > "The GIC-600 only accepts single beat accesses of the sizes for
> > > > each register that are shown in the Programmers model,
> > > > see Chapter 4 Programmer's model on page 4-102.
> > > > All other accesses are rejected and given either an
> > > > OKAY or SLVERR response that is based on the GICT_ERR0CTLR.UE bit.".
> > >
> > > Thus the register needs to be written by double word operation and
> > > the step will be: read 32bit, set byte and write it back.
> > >
> > > [1] https://services.arm.com/support/s/case/5003t00001L4Pba
> >
> > You do realise that this link:
> >
> > - is unusable for most people as it is behind a registration interface
> > - discloses confidential information to other people
> >
> > I strongly suggest you stop posting such links.
> >
> > >
> > > Signed-off-by: Lecopzer Chen <lecopzer.chen@mediatek.com>
> > > ---
> > > drivers/irqchip/irq-gic-v3.c | 13 ++++++++++++-
> > > 1 file changed, 12 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> > > index eb0ee356a629..cfc5a6ad30dc 100644
> > > --- a/drivers/irqchip/irq-gic-v3.c
> > > +++ b/drivers/irqchip/irq-gic-v3.c
> > > @@ -440,10 +440,21 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio)
> > > {
> > > void __iomem *base = gic_dist_base(d);
> > > u32 offset, index;
> > > + u32 val, prio_offset_mask, prio_offset_shift;
> > >
> > > offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
> > >
> > > - writeb_relaxed(prio, base + offset + index);
> > > + /*
> > > + * GIC-600 memory mapping register doesn't support byte opteration,
> > > + * thus read 32-bits from register, set bytes and wtire back to it.
> > > + */
> > > + prio_offset_shift = (index & 0x3) * 8;
> > > + prio_offset_mask = GENMASK(prio_offset_shift + 7, prio_offset_shift);
> > > + index &= ~0x3;
> > > + val = readl_relaxed(base + offset + index);
> > > + val &= ~prio_offset_mask;
> > > + val |= prio << prio_offset_shift;
> > > + writel_relaxed(val, base + offset + index);
> > > }
> > >
> > > static u32 gic_get_ppi_index(struct irq_data *d)
> >
> > From the architecture spec:
> >
> > <quote>
> > 11.1.3 GIC memory-mapped register access
> >
> > In any system, access to the following registers must be supported:
> >
> > [...]
> > * Byte accesses to:
> > - GICD_IPRIORITYR<n>.
> > - GICD_ITARGETSR<n>.
> > - GICD_SPENDSGIR<n>.
> > - GICD_CPENDSGIR<n>.
> > - GICR_IPRIORITYR<n>.
> > </quote>
> >
> > So if GIC600 doesn't follow this architectural requirement, this is a
> > HW erratum, and I want an actual description of the HW issue together
> > with an erratum number.
> >
> > Lorenzo, can you please investigate on your side?
>
> Sure - I will look into it and report back.
Checked - I don't think this patch is needed so it should be dropped and
a follow-up discussion can continue in the relevant/appropriate forum -
if there is anything left to discuss.
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600
2021-03-30 13:06 ` Lorenzo Pieralisi
@ 2021-03-30 14:11 ` Marc Zyngier
2021-03-30 14:24 ` Lecopzer Chen
0 siblings, 1 reply; 6+ messages in thread
From: Marc Zyngier @ 2021-03-30 14:11 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Lecopzer Chen, linux-kernel, linux-arm-kernel, tglx, lecopzer,
yj.chiang, Julien Thierry
On Tue, 30 Mar 2021 14:06:37 +0100,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
>
> On Tue, Mar 30, 2021 at 12:05:46PM +0100, Lorenzo Pieralisi wrote:
> > On Tue, Mar 30, 2021 at 11:33:13AM +0100, Marc Zyngier wrote:
> > > [+Lorenzo, +Julien on an actual email address]
> > >
> > > On Tue, 30 Mar 2021 11:06:19 +0100,
> > > Lecopzer Chen <lecopzer.chen@mediatek.com> wrote:
> > > >
> > > > When pseudo-NMI enabled, register_nmi() set priority of specific IRQ
> > > > by byte ops, and this doesn't work in GIC-600.
> > > >
> > > > We have asked ARM Support [1]:
> > > > > Please refer to following description in
> > > > > "2.1.2 Distributor ACE-Lite slave interface" of GIC-600 TRM for
> > > > > the GIC600 ACE-lite slave interface supported sizes:
> > > > > "The GIC-600 only accepts single beat accesses of the sizes for
> > > > > each register that are shown in the Programmers model,
> > > > > see Chapter 4 Programmer's model on page 4-102.
> > > > > All other accesses are rejected and given either an
> > > > > OKAY or SLVERR response that is based on the GICT_ERR0CTLR.UE bit.".
> > > >
> > > > Thus the register needs to be written by double word operation and
> > > > the step will be: read 32bit, set byte and write it back.
> > > >
> > > > [1] https://services.arm.com/support/s/case/5003t00001L4Pba
> > >
> > > You do realise that this link:
> > >
> > > - is unusable for most people as it is behind a registration interface
> > > - discloses confidential information to other people
> > >
> > > I strongly suggest you stop posting such links.
> > >
> > > >
> > > > Signed-off-by: Lecopzer Chen <lecopzer.chen@mediatek.com>
> > > > ---
> > > > drivers/irqchip/irq-gic-v3.c | 13 ++++++++++++-
> > > > 1 file changed, 12 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> > > > index eb0ee356a629..cfc5a6ad30dc 100644
> > > > --- a/drivers/irqchip/irq-gic-v3.c
> > > > +++ b/drivers/irqchip/irq-gic-v3.c
> > > > @@ -440,10 +440,21 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio)
> > > > {
> > > > void __iomem *base = gic_dist_base(d);
> > > > u32 offset, index;
> > > > + u32 val, prio_offset_mask, prio_offset_shift;
> > > >
> > > > offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
> > > >
> > > > - writeb_relaxed(prio, base + offset + index);
> > > > + /*
> > > > + * GIC-600 memory mapping register doesn't support byte opteration,
> > > > + * thus read 32-bits from register, set bytes and wtire back to it.
> > > > + */
> > > > + prio_offset_shift = (index & 0x3) * 8;
> > > > + prio_offset_mask = GENMASK(prio_offset_shift + 7, prio_offset_shift);
> > > > + index &= ~0x3;
> > > > + val = readl_relaxed(base + offset + index);
> > > > + val &= ~prio_offset_mask;
> > > > + val |= prio << prio_offset_shift;
> > > > + writel_relaxed(val, base + offset + index);
> > > > }
> > > >
> > > > static u32 gic_get_ppi_index(struct irq_data *d)
> > >
> > > From the architecture spec:
> > >
> > > <quote>
> > > 11.1.3 GIC memory-mapped register access
> > >
> > > In any system, access to the following registers must be supported:
> > >
> > > [...]
> > > * Byte accesses to:
> > > - GICD_IPRIORITYR<n>.
> > > - GICD_ITARGETSR<n>.
> > > - GICD_SPENDSGIR<n>.
> > > - GICD_CPENDSGIR<n>.
> > > - GICR_IPRIORITYR<n>.
> > > </quote>
> > >
> > > So if GIC600 doesn't follow this architectural requirement, this is a
> > > HW erratum, and I want an actual description of the HW issue together
> > > with an erratum number.
> > >
> > > Lorenzo, can you please investigate on your side?
> >
> > Sure - I will look into it and report back.
>
> Checked - I don't think this patch is needed so it should be dropped and
> a follow-up discussion can continue in the relevant/appropriate forum -
> if there is anything left to discuss.
Thanks for having had a look. This really smells like an integration
issue rather than an actual GIC bug.
Lecopzer, please check with your HW people and potentially ARM, as I
think you are looking at the wrong problem.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600
2021-03-30 14:11 ` Marc Zyngier
@ 2021-03-30 14:24 ` Lecopzer Chen
0 siblings, 0 replies; 6+ messages in thread
From: Lecopzer Chen @ 2021-03-30 14:24 UTC (permalink / raw)
To: maz
Cc: julien.thierry.kdev, lecopzer.chen, lecopzer, linux-arm-kernel,
linux-kernel, lorenzo.pieralisi, tglx, yj.chiang
[...]
> > > >
> > > > From the architecture spec:
> > > >
> > > > <quote>
> > > > 11.1.3 GIC memory-mapped register access
> > > >
> > > > In any system, access to the following registers must be supported:
> > > >
> > > > [...]
> > > > * Byte accesses to:
> > > > - GICD_IPRIORITYR<n>.
> > > > - GICD_ITARGETSR<n>.
> > > > - GICD_SPENDSGIR<n>.
> > > > - GICD_CPENDSGIR<n>.
> > > > - GICR_IPRIORITYR<n>.
> > > > </quote>
> > > >
> > > > So if GIC600 doesn't follow this architectural requirement, this is a
> > > > HW erratum, and I want an actual description of the HW issue together
> > > > with an erratum number.
> > > >
> > > > Lorenzo, can you please investigate on your side?
> > >
> > > Sure - I will look into it and report back.
> >
> > Checked - I don't think this patch is needed so it should be dropped and
> > a follow-up discussion can continue in the relevant/appropriate forum -
> > if there is anything left to discuss.
>
> Thanks for having had a look. This really smells like an integration
> issue rather than an actual GIC bug.
>
> Lecopzer, please check with your HW people and potentially ARM, as I
> think you are looking at the wrong problem.
Thanks a lot for the suggestion and checking,
I think I'll back to disscuss with ARM and our HW team to figure out
the previous answer from ARM Support in detail.
Thanks again!
Lecopzer
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-03-30 14:25 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2021-03-30 10:06 [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600 Lecopzer Chen
2021-03-30 10:33 ` Marc Zyngier
2021-03-30 11:05 ` Lorenzo Pieralisi
2021-03-30 13:06 ` Lorenzo Pieralisi
2021-03-30 14:11 ` Marc Zyngier
2021-03-30 14:24 ` Lecopzer Chen
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