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From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
To: macro@orcam.me.uk
Cc: ilya.lipnitskiy@gmail.com, linux-kernel@vger.kernel.org,
	linux-mips@vger.kernel.org, liwei391@huawei.com, nbd@nbd.name,
	tsbogend@alpha.franken.de, yangtiezhu@loongson.cn
Subject: [PATCH v3] MIPS: add support for buggy MT7621S core detection
Date: Wed,  7 Apr 2021 13:07:38 -0700	[thread overview]
Message-ID: <20210407200738.149207-1-ilya.lipnitskiy@gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.21.2104071549560.65251@angie.orcam.me.uk>

Most MT7621 SoCs have 2 cores, which is detected and supported properly
by CPS.

Unfortunately, MT7621 SoC has a less common S variant with only one core.
On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
starting SMP. CPULAUNCH registers can be used in that case to detect the
absence of the second core and override the GCR_CONFIG PCORES field.

Rework a long-standing OpenWrt patch to override the value of
mips_cps_numcores on single-core MT7621 systems.

Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
MT7621 device (Netgear R6220).

Original 4.14 OpenWrt patch:
Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
Current 5.10 OpenWrt patch:
Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904

Suggested-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
---
 arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h
index fd43d876892e..35fb8ee6dd33 100644
--- a/arch/mips/include/asm/mips-cps.h
+++ b/arch/mips/include/asm/mips-cps.h
@@ -10,6 +10,8 @@
 #include <linux/io.h>
 #include <linux/types.h>
 
+#include <asm/mips-boards/launch.h>
+
 extern unsigned long __cps_access_bad_size(void)
 	__compiletime_error("Bad size for CPS accessor");
 
@@ -165,11 +167,30 @@ static inline uint64_t mips_cps_cluster_config(unsigned int cluster)
  */
 static inline unsigned int mips_cps_numcores(unsigned int cluster)
 {
+	unsigned int ncores;
+
 	if (!mips_cm_present())
 		return 0;
 
 	/* Add one before masking to handle 0xff indicating no cores */
-	return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
+	ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
+
+	if (IS_ENABLED(CONFIG_SOC_MT7621)) {
+		struct cpulaunch *launch;
+
+		/*
+		 * Ralink MT7621S SoC is single core, but the GCR_CONFIG method
+		 * always reports 2 cores. Check the second core's LAUNCH_FREADY
+		 * flag to detect if the second core is missing. This method
+		 * only works before the core has been started.
+		 */
+		launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
+		launch += 2; /* MT7621 has 2 VPEs per core */
+		if (!(launch->flags & LAUNCH_FREADY))
+			ncores = 1;
+	}
+
+	return ncores;
 }
 
 /**
-- 
2.31.1


  reply	other threads:[~2021-04-07 20:08 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-03  6:19 [PATCH] " Ilya Lipnitskiy
2021-04-06  1:22 ` Maciej W. Rozycki
2021-04-06  1:54   ` Ilya Lipnitskiy
2021-04-07 13:49     ` Maciej W. Rozycki
2021-04-07 18:49       ` Ilya Lipnitskiy
2021-06-25 10:54         ` Strontium
2021-04-06  4:23   ` [PATCH v2] " Ilya Lipnitskiy
2021-04-07 13:52     ` Maciej W. Rozycki
2021-04-07 20:07       ` Ilya Lipnitskiy [this message]
2021-04-12 15:03         ` [PATCH v3] " Thomas Bogendoerfer
2021-09-16  2:56 Greg Ungerer
2021-09-16  6:33 ` Sergio Paracuellos
2021-09-16  6:54   ` Greg Ungerer
2021-09-16  8:54 ` Strontium
2021-09-30 12:41   ` Greg Ungerer
2021-09-30 13:35     ` Sergio Paracuellos
2021-09-30 16:41       ` Ilya Lipnitskiy
2021-09-30 22:36         ` Greg Ungerer
     [not found]         ` <d1eb4cb4-6e9e-3f3c-8ca7-a84d03bb9f53@gmail.com>
2021-10-01  5:04           ` Sergio Paracuellos

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