Re: [PATCH] MIPS: add support for buggy MT7621S core detection

["Maciej W. Rozycki" <macro@orcam.me.uk>]

On Fri, 2 Apr 2021, Ilya Lipnitskiy wrote:

> diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h
> index d72dc6e1cf3c..d32f0c4e61f7 100644
> --- a/arch/mips/include/asm/bugs.h
> +++ b/arch/mips/include/asm/bugs.h
> @@ -50,4 +51,21 @@ static inline int r4k_daddiu_bug(void)
>  	return daddiu_bug != 0;
>  }
>  
> +static inline void cm_gcr_pcores_bug(unsigned int *ncores)
> +{
> +	struct cpulaunch *launch;
> +
> +	if (!IS_ENABLED(CONFIG_SOC_MT7621) || !ncores)
> +		return;
> +
> +	/*
> +	 * Ralink MT7621S SoC is single core, but GCR_CONFIG always reports 2 cores.

 Overlong line.

> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
> index bcd6a944b839..e1e9c11e8a7c 100644
> --- a/arch/mips/kernel/smp-cps.c
> +++ b/arch/mips/kernel/smp-cps.c
> @@ -60,6 +61,7 @@ static void __init cps_smp_setup(void)
>  		pr_cont("{");
>  
>  		ncores = mips_cps_numcores(cl);
> +		cm_gcr_pcores_bug(&ncores);
>  		for (c = 0; c < ncores; c++) {
>  			core_vpes = core_vpe_count(cl, c);
>  
> @@ -170,6 +172,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
>  
>  	/* Allocate core boot configuration structs */
>  	ncores = mips_cps_numcores(0);
> +	cm_gcr_pcores_bug(&ncores);

 Why called at each `mips_cps_numcores' call site rather than within the 
callee?  Also weird inefficient interface: why isn't `ncores' passed by 
value for a new value to be returned?

  Maciej