Re: [PATCH rdma-next 00/10] Enable relaxed ordering for ULPs

From: Jason Gunthorpe <jgg@nvidia.com>
To: David Laight <David.Laight@ACULAB.COM>
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Subject: Re: [PATCH rdma-next 00/10] Enable relaxed ordering for ULPs
Date: Wed, 14 Apr 2021 11:49:07 -0300	[thread overview]
Message-ID: <20210414144907.GD1370958@nvidia.com> (raw)
In-Reply-To: <c2318ee1464a4d1c8439699cb0652d12@AcuMS.aculab.com>

On Wed, Apr 14, 2021 at 02:41:52PM +0000, David Laight wrote:

> So whatever driver initialises the target needs to configure whatever
> target-specific register enables the RO transfers themselves.

RDMA in general, and mlx5 in particular, is a layered design:

mlx5_core <- owns the PCI function, should turn on RO at the PCI
             function level
 mlx5_en  <- Commands the chip to use RO for queues used in ethernet
ib_core
  ib_uverbs
    mlx5_ib <- Commands the chip to use RO for some queues used in
               userspace
  ib_srp* <- A ULP driver built on RDMA - this patch commands the chip
             to use RO on SRP queues
  nvme-rdma <- Ditto
  ib_iser <- Ditto
  rds <- Ditto

So this series is about expanding the set of queues running on mlx5
that have RO turned when the PCI function is already running with RO
enabled.

We want as many queues as possible RO enabled because it brings big
performance wins

Jason