From: Beata Michalska <beata.michalska@arm.com>
To: Dietmar Eggemann <dietmar.eggemann@arm.com>
Cc: Valentin Schneider <valentin.schneider@arm.com>,
linux-kernel@vger.kernel.org, peterz@infradead.org,
mingo@redhat.com, juri.lelli@redhat.com,
vincent.guittot@linaro.org, corbet@lwn.net,
rdunlap@infradead.org, linux-doc@vger.kernel.org
Subject: Re: [PATCH v5 2/3] sched/topology: Rework CPU capacity asymmetry detection
Date: Thu, 27 May 2021 18:07:30 +0100 [thread overview]
Message-ID: <20210527170729.GA20994@e120325.cambridge.arm.com> (raw)
In-Reply-To: <14593ba7-eed9-f035-724c-5cadbb859adc@arm.com>
On Thu, May 27, 2021 at 05:08:42PM +0200, Dietmar Eggemann wrote:
> On 26/05/2021 23:40, Beata Michalska wrote:
> > On Wed, May 26, 2021 at 08:17:41PM +0200, Dietmar Eggemann wrote:
> >> On 26/05/2021 14:51, Beata Michalska wrote:
> >>> On Wed, May 26, 2021 at 01:15:46PM +0100, Beata Michalska wrote:
> >>>> On Wed, May 26, 2021 at 11:52:25AM +0200, Dietmar Eggemann wrote:
> >>>>> On 25/05/2021 12:29, Beata Michalska wrote:
> >>>>>> On Tue, May 25, 2021 at 10:53:07AM +0100, Valentin Schneider wrote:
> >>>>>>> On 24/05/21 23:55, Beata Michalska wrote:
> >>>>>>>> On Mon, May 24, 2021 at 07:01:04PM +0100, Valentin Schneider wrote:
> >>>>>>>>> On 24/05/21 11:16, Beata Michalska wrote:
>
> [...]
>
> >> cpu-map {
> >> cluster0 {
> >> core0 {
> >> thread0 {
> >> cpu = <&A53_0>;
> >> };
> >> thread1 {
> >> cpu = <&A53_1>;
> >> };
> >> };
> >> core1 {
> >> thread0 {
> >> cpu = <&A53_2>;
> >> };
> >> thread1 {
> >> cpu = <&A53_3>;
> >> };
> >> };
> >> core2 {
> >> thread0 {
> >> cpu = <&A53_4>;
> >> };
> >> thread1 {
> >> cpu = <&A53_5>;
> >> };
> >> };
> >> };
> >>
> >> cluster1 {
> >> core0 {
> >> thread0 {
> >> cpu = <&A53_6>;
> >> };
> >> thread1 {
> >> cpu = <&A53_7>;
> >> };
> >> };
> >> };
> >> };
> >>
> >> A53_0: cpu@0 {
> >> capacity-dmips-mhz = <446>;
> >> A53_1: cpu@1 {
> >> capacity-dmips-mhz = <1024>;
> >> A53_2: cpu@2 {
> >> capacity-dmips-mhz = <871>;
> >> A53_3: cpu@3 {
> >> capacity-dmips-mhz = <1024>;
> >> A53_4: cpu@4 {
> >> capacity-dmips-mhz = <446>;
> >> A53_5: cpu@5 {
> >> capacity-dmips-mhz = <871>;
> >> A53_6: cpu@6 {
> >> capacity-dmips-mhz = <1024>;
> >> A53_7: cpu@7 {
> >> capacity-dmips-mhz = <1024>;
> >>
> >> Here I guess SD_ASYM_CPUCAPACITY will be attached to SMT[0-5]. So this
> >> 'capacity-dmips-mhz' config error won't be detected.
> >>
> >> In case all CPUs (i.e. hw threads would have the correct
> >> capacity-dmips-mhz = <1024> or not being set (default 1024))
> >> asym_cap_list would corrcetly only have 1 entry.
> > We could possibly add a warning (like in EAS) if the asymmetry is detected
> > for SMT which would give some indication that there is smth ... wrong ?
>
> Maybe, in case you find an easy way to detect this.
>
> But the issue already exists today. Not with the topology mentioned
> above but in case we slightly change it to:
>
> cpus = { ([446 1024] [871 1024] [446 1024] ) ([1024 1024]) }
> ^^^^
> so that we have a 1024 CPU in the lowest sd for each CPU, we would get
> SD_ASYM_CPUCAPACITY on SMT.
The asymmetry capacity flags are being set on a sched domain level, so
we could use the SD_SHARE_CPUCAPACITY|SD_SHARE_PKG_RESOURCES (cpu_smt_flags)
flags to determine if having asymmetry is valid or not ? If this is enough
this could be handled by the classify function?
---
BR
B.
next prev parent reply other threads:[~2021-05-27 17:07 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-24 10:16 [PATCH v5 0/3] Rework CPU capacity asymmetry detection Beata Michalska
2021-05-24 10:16 ` [PATCH v5 1/3] sched/core: Introduce SD_ASYM_CPUCAPACITY_FULL sched_domain flag Beata Michalska
2021-05-24 10:16 ` [PATCH v5 2/3] sched/topology: Rework CPU capacity asymmetry detection Beata Michalska
2021-05-24 18:01 ` Valentin Schneider
2021-05-24 22:55 ` Beata Michalska
2021-05-24 23:19 ` Beata Michalska
2021-05-25 9:53 ` Valentin Schneider
2021-05-25 10:29 ` Beata Michalska
2021-05-26 9:52 ` Dietmar Eggemann
2021-05-26 12:15 ` Beata Michalska
2021-05-26 12:51 ` Beata Michalska
2021-05-26 18:17 ` Dietmar Eggemann
2021-05-26 21:40 ` Beata Michalska
2021-05-27 15:08 ` Dietmar Eggemann
2021-05-27 17:07 ` Beata Michalska [this message]
2021-06-02 17:17 ` Dietmar Eggemann
2021-06-02 19:48 ` Beata Michalska
2021-06-03 9:09 ` Dietmar Eggemann
2021-06-03 9:24 ` Beata Michalska
2021-05-26 18:17 ` Dietmar Eggemann
2021-05-26 21:43 ` Beata Michalska
2021-05-27 7:03 ` Peter Zijlstra
2021-05-27 12:22 ` Dietmar Eggemann
2021-05-27 12:32 ` Beata Michalska
2021-05-25 8:25 ` Dietmar Eggemann
2021-05-25 9:30 ` Beata Michalska
2021-05-25 11:59 ` Dietmar Eggemann
2021-05-25 14:04 ` Beata Michalska
2021-05-24 10:16 ` [PATCH v5 3/3] sched/doc: Update the CPU capacity asymmetry bits Beata Michalska
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