* [PATCH 1/3] dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller
2021-06-04 18:09 [PATCH 0/3] SoC identification support for RZ/G2L Lad Prabhakar
@ 2021-06-04 18:09 ` Lad Prabhakar
2021-06-09 7:19 ` Geert Uytterhoeven
2021-06-04 18:09 ` [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's Lad Prabhakar
2021-06-04 18:09 ` [PATCH 3/3] arm64: dts: renesas: r9a07g044: Add SYSC node to RZ/G2L SoC DTSI Lad Prabhakar
2 siblings, 1 reply; 9+ messages in thread
From: Lad Prabhakar @ 2021-06-04 18:09 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc,
devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add DT binding documentation for SYSC controller found on
RZ/G2{L,LC,UL} SoC's.
SYSC block contains the LSI_DEVID register which is used to retrieve
SoC product information.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/power/renesas,rzg2l-sysc.yaml | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
new file mode 100644
index 000000000000..616a5139644f
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas RZ/G2L System Controller (SYSC)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The RZ/G2L System Controller (SYSC) performs system control of the LSI and
+ supports following functions,
+ - External terminal state capture function
+ - 34-bit address space access function
+ - Low power consumption control
+ - WDT stop control
+
+properties:
+ compatible:
+ enum:
+ - renesas,r9a07g044-sysc # RZ/G2{L,LC}
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 4
+ maxItems: 4
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ // System Controller node
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g044-sysc";
+ reg = <0x11020000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller
2021-06-04 18:09 ` [PATCH 1/3] dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller Lad Prabhakar
@ 2021-06-09 7:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2021-06-09 7:19 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
Hi Prabhakr,
On Fri, Jun 4, 2021 at 8:09 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add DT binding documentation for SYSC controller found on
> RZ/G2{L,LC,UL} SoC's.
>
> SYSC block contains the LSI_DEVID register which is used to retrieve
> SoC product information.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/power/renesas,rzg2l-sysc.yaml | 50 +++++++++++++++++++
> 1 file changed, 50 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
>
> diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
> new file mode 100644
> index 000000000000..616a5139644f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Renesas RZ/G2L System Controller (SYSC)
> +
> +maintainers:
> + - Geert Uytterhoeven <geert+renesas@glider.be>
> +
> +description:
> + The RZ/G2L System Controller (SYSC) performs system control of the LSI and
> + supports following functions,
> + - External terminal state capture function
> + - 34-bit address space access function
> + - Low power consumption control
> + - WDT stop control
> +
> +properties:
> + compatible:
> + enum:
> + - renesas,r9a07g044-sysc # RZ/G2{L,LC}
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + minItems: 4
> + maxItems: 4
For multiple interrupts, you may want to add descriptions, and
interrupt-names.
The reset looks good to me, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's
2021-06-04 18:09 [PATCH 0/3] SoC identification support for RZ/G2L Lad Prabhakar
2021-06-04 18:09 ` [PATCH 1/3] dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller Lad Prabhakar
@ 2021-06-04 18:09 ` Lad Prabhakar
2021-06-09 7:27 ` Geert Uytterhoeven
2021-06-04 18:09 ` [PATCH 3/3] arm64: dts: renesas: r9a07g044: Add SYSC node to RZ/G2L SoC DTSI Lad Prabhakar
2 siblings, 1 reply; 9+ messages in thread
From: Lad Prabhakar @ 2021-06-04 18:09 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc,
devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add support for reading the LSI DEVID register which is present in
SYSC block of RZ/G2{L,LC} SoC's.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/soc/renesas/renesas-soc.c | 34 ++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 0f8eff4a641a..e6b21da281ef 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -56,6 +56,11 @@ static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
.reg = 0xfff00044, /* PRR (Product Register) */
};
+static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
+ .name = "RZ/G2L",
+ .reg = 0x11020a04,
+};
+
static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
.name = "SH-Mobile",
.reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
@@ -64,7 +69,7 @@ static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
struct renesas_soc {
const struct renesas_family *family;
- u8 id;
+ u32 id;
};
static const struct renesas_soc soc_rz_a1h __initconst __maybe_unused = {
@@ -131,6 +136,11 @@ static const struct renesas_soc soc_rz_g2h __initconst __maybe_unused = {
.id = 0x4f,
};
+static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = {
+ .family = &fam_rzg2l,
+ .id = 0x841c447,
+};
+
static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
.family = &fam_rcar_gen1,
};
@@ -299,6 +309,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A779A0
{ .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u },
#endif
+#if defined(CONFIG_ARCH_R9A07G044)
+ { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l },
+#endif
#ifdef CONFIG_ARCH_SH73A0
{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
#endif
@@ -348,6 +361,25 @@ static int __init renesas_soc_init(void)
goto done;
}
+ np = of_find_compatible_node(NULL, NULL, "renesas,r9a07g044-sysc");
+ if (np) {
+ of_node_put(np);
+ chipid = ioremap(family->reg, 4);
+
+ if (chipid) {
+ product = readl(chipid);
+ iounmap(chipid);
+
+ if (soc->id && (product & 0xfffffff) != soc->id) {
+ pr_warn("SoC mismatch (product = 0x%x)\n",
+ product);
+ return -ENODEV;
+ }
+ }
+
+ goto done;
+ }
+
/* Try PRR first, then hardcoded fallback */
np = of_find_compatible_node(NULL, NULL, "renesas,prr");
if (np) {
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's
2021-06-04 18:09 ` [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's Lad Prabhakar
@ 2021-06-09 7:27 ` Geert Uytterhoeven
2021-06-09 15:49 ` Lad, Prabhakar
0 siblings, 1 reply; 9+ messages in thread
From: Geert Uytterhoeven @ 2021-06-09 7:27 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
Hi Prabhakar,
On Fri, Jun 4, 2021 at 8:09 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add support for reading the LSI DEVID register which is present in
> SYSC block of RZ/G2{L,LC} SoC's.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/soc/renesas/renesas-soc.c
> +++ b/drivers/soc/renesas/renesas-soc.c
> @@ -56,6 +56,11 @@ static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
> .reg = 0xfff00044, /* PRR (Product Register) */
> };
>
> +static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
> + .name = "RZ/G2L",
> + .reg = 0x11020a04,
Please don't add hardcoded register addresses for new SoCs (i.e. drop
".reg"). The "renesas,r9a07g044-sysc" is always present.
And if it were missing, the hardcoded fallback would lead into the
classic CCCR/PRR scheme, which is not correct for RZ/G2L...
> @@ -348,6 +361,25 @@ static int __init renesas_soc_init(void)
> goto done;
> }
>
> + np = of_find_compatible_node(NULL, NULL, "renesas,r9a07g044-sysc");
> + if (np) {
> + of_node_put(np);
> + chipid = ioremap(family->reg, 4);
Just use of_iomap(np, 0)...
> +
> + if (chipid) {
> + product = readl(chipid);
... and add the DEVID offset within the SYSC block here.
> + iounmap(chipid);
> +
> + if (soc->id && (product & 0xfffffff) != soc->id) {
> + pr_warn("SoC mismatch (product = 0x%x)\n",
> + product);
> + return -ENODEV;
> + }
> + }
> +
> + goto done;
> + }
> +
> /* Try PRR first, then hardcoded fallback */
> np = of_find_compatible_node(NULL, NULL, "renesas,prr");
> if (np) {
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's
2021-06-09 7:27 ` Geert Uytterhoeven
@ 2021-06-09 15:49 ` Lad, Prabhakar
2021-06-09 15:57 ` Geert Uytterhoeven
0 siblings, 1 reply; 9+ messages in thread
From: Lad, Prabhakar @ 2021-06-09 15:49 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Biju Das
Hi Geert,
Thank you for the review.
On Wed, Jun 9, 2021 at 8:27 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, Jun 4, 2021 at 8:09 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Add support for reading the LSI DEVID register which is present in
> > SYSC block of RZ/G2{L,LC} SoC's.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/soc/renesas/renesas-soc.c
> > +++ b/drivers/soc/renesas/renesas-soc.c
> > @@ -56,6 +56,11 @@ static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
> > .reg = 0xfff00044, /* PRR (Product Register) */
> > };
> >
> > +static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
> > + .name = "RZ/G2L",
> > + .reg = 0x11020a04,
>
> Please don't add hardcoded register addresses for new SoCs (i.e. drop
> ".reg"). The "renesas,r9a07g044-sysc" is always present.
> And if it were missing, the hardcoded fallback would lead into the
> classic CCCR/PRR scheme, which is not correct for RZ/G2L...
>
I wanted to avoid iomap for the entire sysc block for just a single register.
> > @@ -348,6 +361,25 @@ static int __init renesas_soc_init(void)
> > goto done;
> > }
> >
> > + np = of_find_compatible_node(NULL, NULL, "renesas,r9a07g044-sysc");
> > + if (np) {
> > + of_node_put(np);
> > + chipid = ioremap(family->reg, 4);
>
> Just use of_iomap(np, 0)...
>
will do.
> > +
> > + if (chipid) {
> > + product = readl(chipid);
>
> ... and add the DEVID offset within the SYSC block here.
>
will do.
Cheers,
Prabhakar
> > + iounmap(chipid);
> > +
> > + if (soc->id && (product & 0xfffffff) != soc->id) {
> > + pr_warn("SoC mismatch (product = 0x%x)\n",
> > + product);
> > + return -ENODEV;
> > + }
> > + }
> > +
> > + goto done;
> > + }
> > +
> > /* Try PRR first, then hardcoded fallback */
> > np = of_find_compatible_node(NULL, NULL, "renesas,prr");
> > if (np) {
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's
2021-06-09 15:49 ` Lad, Prabhakar
@ 2021-06-09 15:57 ` Geert Uytterhoeven
0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2021-06-09 15:57 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Biju Das
Hi Prabhakar,
On Wed, Jun 9, 2021 at 5:50 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Wed, Jun 9, 2021 at 8:27 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, Jun 4, 2021 at 8:09 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > Add support for reading the LSI DEVID register which is present in
> > > SYSC block of RZ/G2{L,LC} SoC's.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/soc/renesas/renesas-soc.c
> > > +++ b/drivers/soc/renesas/renesas-soc.c
> > > @@ -56,6 +56,11 @@ static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
> > > .reg = 0xfff00044, /* PRR (Product Register) */
> > > };
> > >
> > > +static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
> > > + .name = "RZ/G2L",
> > > + .reg = 0x11020a04,
> >
> > Please don't add hardcoded register addresses for new SoCs (i.e. drop
> > ".reg"). The "renesas,r9a07g044-sysc" is always present.
> > And if it were missing, the hardcoded fallback would lead into the
> > classic CCCR/PRR scheme, which is not correct for RZ/G2L...
> >
> I wanted to avoid iomap for the entire sysc block for just a single register.
The mapping will be rounded up to PAGE_SIZE anyway
(I know, SYSC is 64 KiB, hence larger than the typical page size).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: renesas: r9a07g044: Add SYSC node to RZ/G2L SoC DTSI
2021-06-04 18:09 [PATCH 0/3] SoC identification support for RZ/G2L Lad Prabhakar
2021-06-04 18:09 ` [PATCH 1/3] dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller Lad Prabhakar
2021-06-04 18:09 ` [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's Lad Prabhakar
@ 2021-06-04 18:09 ` Lad Prabhakar
2021-06-09 7:28 ` Geert Uytterhoeven
2 siblings, 1 reply; 9+ messages in thread
From: Lad Prabhakar @ 2021-06-04 18:09 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc,
devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add SYSC node to RZ/G2L (R9A07G044) SoC DTSI
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index b2dbf6543d98..6515177bce29 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -98,6 +98,16 @@
#power-domain-cells = <0>;
};
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g044-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] arm64: dts: renesas: r9a07g044: Add SYSC node to RZ/G2L SoC DTSI
2021-06-04 18:09 ` [PATCH 3/3] arm64: dts: renesas: r9a07g044: Add SYSC node to RZ/G2L SoC DTSI Lad Prabhakar
@ 2021-06-09 7:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 9+ messages in thread
From: Geert Uytterhoeven @ 2021-06-09 7:28 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
On Fri, Jun 4, 2021 at 8:09 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add SYSC node to RZ/G2L (R9A07G044) SoC DTSI
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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