From: Steven Lee <steven_lee@aspeedtech.com>
To: Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
Rob Herring <robh+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Andrew Jeffery <andrew@aj.id.au>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
"moderated list:ARM/ASPEED MACHINE SUPPORT"
<linux-arm-kernel@lists.infradead.org>,
"moderated list:ARM/ASPEED MACHINE SUPPORT"
<linux-aspeed@lists.ozlabs.org>,
open list <linux-kernel@vger.kernel.org>
Cc: <steven_lee@aspeedtech.com>, <Hongweiz@ami.com>,
<ryan_chen@aspeedtech.com>, <billy_tsai@aspeedtech.com>
Subject: [PATCH v4 5/7] gpio: gpio-aspeed-sgpio: Add set_config function
Date: Mon, 7 Jun 2021 15:15:10 +0800 [thread overview]
Message-ID: <20210607071514.11727-6-steven_lee@aspeedtech.com> (raw)
In-Reply-To: <20210607071514.11727-1-steven_lee@aspeedtech.com>
AST SoC supports *retain pin state* function when wdt reset.
The patch adds set_config function for handling sgpio reset tolerance
register.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
---
drivers/gpio/gpio-aspeed-sgpio.c | 54 +++++++++++++++++++++++++++++---
1 file changed, 50 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 8b893356f0ca..08696f12ee1c 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -51,9 +51,10 @@ struct aspeed_sgpio {
};
struct aspeed_sgpio_bank {
- uint16_t val_regs;
- uint16_t rdata_reg;
- uint16_t irq_regs;
+ u16 val_regs;
+ u16 rdata_reg;
+ u16 irq_regs;
+ u16 tolerance_regs;
const char names[4][3];
};
@@ -69,24 +70,28 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
.val_regs = 0x0000,
.rdata_reg = 0x0070,
.irq_regs = 0x0004,
+ .tolerance_regs = 0x0018,
.names = { "A", "B", "C", "D" },
},
{
.val_regs = 0x001C,
.rdata_reg = 0x0074,
.irq_regs = 0x0020,
+ .tolerance_regs = 0x0034,
.names = { "E", "F", "G", "H" },
},
{
.val_regs = 0x0038,
.rdata_reg = 0x0078,
.irq_regs = 0x003C,
+ .tolerance_regs = 0x0050,
.names = { "I", "J", "K", "L" },
},
{
.val_regs = 0x0090,
.rdata_reg = 0x007C,
.irq_regs = 0x0094,
+ .tolerance_regs = 0x00A8,
.names = { "M", "N", "O", "P" },
},
};
@@ -99,6 +104,7 @@ enum aspeed_sgpio_reg {
reg_irq_type1,
reg_irq_type2,
reg_irq_status,
+ reg_tolerance,
};
#define GPIO_VAL_VALUE 0x00
@@ -127,6 +133,8 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
case reg_irq_status:
return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
+ case reg_tolerance:
+ return gpio->base + bank->tolerance_regs;
default:
/* acturally if code runs to here, it's an error case */
BUG();
@@ -483,6 +491,44 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
return 0;
}
+static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
+ unsigned int offset, bool enable)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
+ unsigned long flags;
+ void __iomem *reg;
+ u32 val;
+
+ reg = bank_reg(gpio, to_bank(offset, gpio), reg_tolerance);
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ val = readl(reg);
+
+ if (enable)
+ val |= GPIO_BIT(offset, gpio);
+ else
+ val &= ~GPIO_BIT(offset, gpio);
+
+ writel(val, reg);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return 0;
+}
+
+static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
+ unsigned long config)
+{
+ unsigned long param = pinconf_to_config_param(config);
+ u32 arg = pinconf_to_config_argument(config);
+
+ if (param == PIN_CONFIG_PERSIST_STATE)
+ return aspeed_sgpio_reset_tolerance(chip, offset, arg);
+
+ return -ENOTSUPP;
+}
+
static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = {
.max_ngpios = 128,
.pin_mask = GENMASK(10, 6),
@@ -590,7 +636,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
gpio->chip.free = NULL;
gpio->chip.get = aspeed_sgpio_get;
gpio->chip.set = aspeed_sgpio_set;
- gpio->chip.set_config = NULL;
+ gpio->chip.set_config = aspeed_sgpio_set_config;
gpio->chip.label = dev_name(&pdev->dev);
gpio->chip.base = -1;
--
2.17.1
next prev parent reply other threads:[~2021-06-07 7:15 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 7:15 [PATCH v4 0/7] ASPEED sgpio driver enhancement Steven Lee
2021-06-07 7:15 ` [PATCH v4 1/7] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml Steven Lee
2021-06-07 7:15 ` [PATCH v4 2/7] dt-bindings: aspeed-sgpio: Add ast2600 sgpio compatibles Steven Lee
2021-06-07 23:22 ` Andrew Jeffery
2021-06-07 7:15 ` [PATCH v4 3/7] ARM: dts: aspeed-g6: Add SGPIO node Steven Lee
2021-06-07 23:28 ` Andrew Jeffery
2021-06-08 2:25 ` Steven Lee
2021-06-07 7:15 ` [PATCH v4 4/7] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support Steven Lee
2021-06-07 23:43 ` Andrew Jeffery
2021-06-08 2:50 ` Steven Lee
2021-06-08 3:22 ` Andrew Jeffery
2021-06-07 7:15 ` Steven Lee [this message]
2021-06-07 23:48 ` [PATCH v4 5/7] gpio: gpio-aspeed-sgpio: Add set_config function Andrew Jeffery
2021-06-07 7:15 ` [PATCH v4 6/7] gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct Steven Lee
2021-06-07 7:15 ` [PATCH v4 7/7] gpio: gpio-aspeed-sgpio: Use generic device property APIs Steven Lee
2021-06-07 23:52 ` Andrew Jeffery
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