* [PATCH v8 1/6] dt-bindings: spi: spi-rockchip: add description for rv1126
2021-06-15 3:32 [PATCH v8 0/6] Support ROCKCHIP SPI new feature Jon Lin
@ 2021-06-15 3:32 ` Jon Lin
2021-06-15 23:33 ` Rob Herring
2021-06-15 3:32 ` [PATCH v8 2/6] spi: rockchip: add compatible string " Jon Lin
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Jon Lin @ 2021-06-15 3:32 UTC (permalink / raw)
To: broonie
Cc: jon.lin, heiko, robh+dt, linux-spi, linux-arm-kernel,
linux-rockchip, linux-kernel, devicetree
The description below will be used for rv1126.dtsi or compatible one in
the future
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
Changes in v8:
- There is a problem with the version 7 mail format. resend it
Changes in v7:
- Fall back "rockchip,rv1126-spi" to "rockchip,rk3066-spi"
Changes in v6:
- Consider to compatibility, the "rockchip,rk3568-spi" is removed in
Series-changes v5, so the commit massage should also remove the
corresponding information
Changes in v5:
- Change to leave one compatible id rv1126, and rk3568 is compatible
with rv1126
Changes in v4:
- Adjust the order patches
- Simply commit massage like redundancy "application" content
Changes in v3:
- Fix compile error which is find by Sascha in [v2,2/8]
Documentation/devicetree/bindings/spi/spi-rockchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml
index 1e6cf29e6388..7f987e79337c 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml
@@ -33,6 +33,7 @@ properties:
- rockchip,rk3328-spi
- rockchip,rk3368-spi
- rockchip,rk3399-spi
+ - rockchip,rv1126-spi
- const: rockchip,rk3066-spi
reg:
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v8 1/6] dt-bindings: spi: spi-rockchip: add description for rv1126
2021-06-15 3:32 ` [PATCH v8 1/6] dt-bindings: spi: spi-rockchip: add description for rv1126 Jon Lin
@ 2021-06-15 23:33 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2021-06-15 23:33 UTC (permalink / raw)
To: Jon Lin
Cc: broonie, linux-arm-kernel, heiko, devicetree, linux-spi,
linux-rockchip, robh+dt, linux-kernel
On Tue, 15 Jun 2021 11:32:08 +0800, Jon Lin wrote:
> The description below will be used for rv1126.dtsi or compatible one in
> the future
>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
>
> Changes in v8:
> - There is a problem with the version 7 mail format. resend it
>
> Changes in v7:
> - Fall back "rockchip,rv1126-spi" to "rockchip,rk3066-spi"
>
> Changes in v6:
> - Consider to compatibility, the "rockchip,rk3568-spi" is removed in
> Series-changes v5, so the commit massage should also remove the
> corresponding information
>
> Changes in v5:
> - Change to leave one compatible id rv1126, and rk3568 is compatible
> with rv1126
>
> Changes in v4:
> - Adjust the order patches
> - Simply commit massage like redundancy "application" content
>
> Changes in v3:
> - Fix compile error which is find by Sascha in [v2,2/8]
>
> Documentation/devicetree/bindings/spi/spi-rockchip.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v8 2/6] spi: rockchip: add compatible string for rv1126
2021-06-15 3:32 [PATCH v8 0/6] Support ROCKCHIP SPI new feature Jon Lin
2021-06-15 3:32 ` [PATCH v8 1/6] dt-bindings: spi: spi-rockchip: add description for rv1126 Jon Lin
@ 2021-06-15 3:32 ` Jon Lin
2021-06-15 3:32 ` [PATCH v8 3/6] spi: rockchip: Set rx_fifo interrupt waterline base on transfer item Jon Lin
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Jon Lin @ 2021-06-15 3:32 UTC (permalink / raw)
To: broonie
Cc: jon.lin, heiko, robh+dt, linux-spi, linux-arm-kernel,
linux-rockchip, linux-kernel, devicetree
Add compatible string for rv1126 for potential applications.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/spi/spi-rockchip.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 52d6259d96ed..bbeed3ae4ee1 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -922,6 +922,7 @@ static const struct of_device_id rockchip_spi_dt_match[] = {
{ .compatible = "rockchip,rk3368-spi", },
{ .compatible = "rockchip,rk3399-spi", },
{ .compatible = "rockchip,rv1108-spi", },
+ { .compatible = "rockchip,rv1126-spi", },
{ },
};
MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v8 3/6] spi: rockchip: Set rx_fifo interrupt waterline base on transfer item
2021-06-15 3:32 [PATCH v8 0/6] Support ROCKCHIP SPI new feature Jon Lin
2021-06-15 3:32 ` [PATCH v8 1/6] dt-bindings: spi: spi-rockchip: add description for rv1126 Jon Lin
2021-06-15 3:32 ` [PATCH v8 2/6] spi: rockchip: add compatible string " Jon Lin
@ 2021-06-15 3:32 ` Jon Lin
2021-06-15 3:32 ` [PATCH v8 4/6] spi: rockchip: Wait for STB status in slave mode tx_xfer Jon Lin
2021-06-15 3:32 ` [PATCH v8 5/6] spi: rockchip: Support cs-gpio Jon Lin
4 siblings, 0 replies; 8+ messages in thread
From: Jon Lin @ 2021-06-15 3:32 UTC (permalink / raw)
To: broonie
Cc: jon.lin, heiko, robh+dt, linux-spi, linux-arm-kernel,
linux-rockchip, linux-kernel, devicetree
The error here is to calculate the width as 8 bits. In fact, 16 bits
should be considered.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/spi/spi-rockchip.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index bbeed3ae4ee1..0887b19ef3ad 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -540,8 +540,8 @@ static int rockchip_spi_config(struct rockchip_spi *rs,
* interrupt exactly when the fifo is full doesn't seem to work,
* so we need the strict inequality here
*/
- if (xfer->len < rs->fifo_len)
- writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
+ if ((xfer->len / rs->n_bytes) < rs->fifo_len)
+ writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
else
writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v8 4/6] spi: rockchip: Wait for STB status in slave mode tx_xfer
2021-06-15 3:32 [PATCH v8 0/6] Support ROCKCHIP SPI new feature Jon Lin
` (2 preceding siblings ...)
2021-06-15 3:32 ` [PATCH v8 3/6] spi: rockchip: Set rx_fifo interrupt waterline base on transfer item Jon Lin
@ 2021-06-15 3:32 ` Jon Lin
2021-06-15 3:32 ` [PATCH v8 5/6] spi: rockchip: Support cs-gpio Jon Lin
4 siblings, 0 replies; 8+ messages in thread
From: Jon Lin @ 2021-06-15 3:32 UTC (permalink / raw)
To: broonie
Cc: jon.lin, heiko, robh+dt, linux-spi, linux-arm-kernel,
linux-rockchip, linux-kernel, devicetree
After ROCKCHIP_SPI_VER2_TYPE2, SR->STB is a more accurate judgment
bit for spi slave transmition.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/spi/spi-rockchip.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 0887b19ef3ad..950d3bce443b 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -116,13 +116,14 @@
#define BAUDR_SCKDV_MIN 2
#define BAUDR_SCKDV_MAX 65534
-/* Bit fields in SR, 5bit */
-#define SR_MASK 0x1f
+/* Bit fields in SR, 6bit */
+#define SR_MASK 0x3f
#define SR_BUSY (1 << 0)
#define SR_TF_FULL (1 << 1)
#define SR_TF_EMPTY (1 << 2)
#define SR_RF_EMPTY (1 << 3)
#define SR_RF_FULL (1 << 4)
+#define SR_SLAVE_TX_BUSY (1 << 5)
/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
#define INT_MASK 0x1f
@@ -197,13 +198,19 @@ static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
}
-static inline void wait_for_idle(struct rockchip_spi *rs)
+static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
{
unsigned long timeout = jiffies + msecs_to_jiffies(5);
do {
- if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
- return;
+ if (slave_mode) {
+ if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
+ !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
+ return;
+ } else {
+ if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
+ return;
+ }
} while (!time_after(jiffies, timeout));
dev_warn(rs->dev, "spi controller is in busy state!\n");
@@ -383,7 +390,7 @@ static void rockchip_spi_dma_txcb(void *data)
return;
/* Wait until the FIFO data completely. */
- wait_for_idle(rs);
+ wait_for_tx_idle(rs, ctlr->slave);
spi_enable_chip(rs, false);
spi_finalize_current_transfer(ctlr);
@@ -545,7 +552,7 @@ static int rockchip_spi_config(struct rockchip_spi *rs,
else
writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
- writel_relaxed(rs->fifo_len / 2, rs->regs + ROCKCHIP_SPI_DMATDLR);
+ writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
rs->regs + ROCKCHIP_SPI_DMARDLR);
writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v8 5/6] spi: rockchip: Support cs-gpio
2021-06-15 3:32 [PATCH v8 0/6] Support ROCKCHIP SPI new feature Jon Lin
` (3 preceding siblings ...)
2021-06-15 3:32 ` [PATCH v8 4/6] spi: rockchip: Wait for STB status in slave mode tx_xfer Jon Lin
@ 2021-06-15 3:32 ` Jon Lin
2021-06-15 3:32 ` [PATCH v8 6/6] spi: rockchip: Support SPI_CS_HIGH Jon Lin
4 siblings, 1 reply; 8+ messages in thread
From: Jon Lin @ 2021-06-15 3:32 UTC (permalink / raw)
To: broonie
Cc: jon.lin, heiko, robh+dt, linux-spi, linux-arm-kernel,
linux-rockchip, linux-kernel, devicetree
1.Add standard cs-gpio support
2.Refer to spi-controller.yaml for details
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/spi/spi-rockchip.c | 61 ++++++++++++++++++++++++++++++++++----
1 file changed, 56 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 950d3bce443b..48b666d42d8a 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -6,6 +6,7 @@
#include <linux/clk.h>
#include <linux/dmaengine.h>
+#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -157,7 +158,8 @@
*/
#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
-#define ROCKCHIP_SPI_MAX_CS_NUM 2
+/* 2 for native cs, 2 for cs-gpio */
+#define ROCKCHIP_SPI_MAX_CS_NUM 4
#define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
#define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
@@ -191,6 +193,7 @@ struct rockchip_spi {
bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
bool slave_abort;
+ bool gpio_requested;
};
static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
@@ -245,11 +248,15 @@ static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
/* Keep things powered as long as CS is asserted */
pm_runtime_get_sync(rs->dev);
- ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
- BIT(spi->chip_select));
+ if (gpio_is_valid(spi->cs_gpio))
+ ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
+ else
+ ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
} else {
- ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
- BIT(spi->chip_select));
+ if (gpio_is_valid(spi->cs_gpio))
+ ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
+ else
+ ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
/* Drop reference from when we first asserted CS */
pm_runtime_put(rs->dev);
@@ -632,6 +639,47 @@ static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
return xfer->len / bytes_per_word >= rs->fifo_len;
}
+static int rockchip_spi_setup(struct spi_device *spi)
+{
+
+ int ret = -EINVAL;
+ struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
+
+ if (spi->cs_gpio == -ENOENT)
+ return 0;
+
+ if (!rs->gpio_requested && gpio_is_valid(spi->cs_gpio)) {
+ ret = gpio_request_one(spi->cs_gpio,
+ (spi->mode & SPI_CS_HIGH) ?
+ GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
+ dev_name(&spi->dev));
+ if (ret)
+ dev_err(&spi->dev, "can't request chipselect gpio %d\n",
+ spi->cs_gpio);
+ else
+ rs->gpio_requested = true;
+ } else {
+ if (gpio_is_valid(spi->cs_gpio)) {
+ int mode = ((spi->mode & SPI_CS_HIGH) ? 0 : 1);
+
+ ret = gpio_direction_output(spi->cs_gpio, mode);
+ if (ret)
+ dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n",
+ spi->cs_gpio, ret);
+ }
+ }
+
+ return ret;
+}
+
+static void rockchip_spi_cleanup(struct spi_device *spi)
+{
+ struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
+
+ if (rs->gpio_requested)
+ gpio_free(spi->cs_gpio);
+}
+
static int rockchip_spi_probe(struct platform_device *pdev)
{
int ret;
@@ -706,6 +754,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
rs->dev = &pdev->dev;
rs->freq = clk_get_rate(rs->spiclk);
+ rs->gpio_requested = false;
if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
&rsd_nsecs)) {
@@ -759,6 +808,8 @@ static int rockchip_spi_probe(struct platform_device *pdev)
ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
ctlr->set_cs = rockchip_spi_set_cs;
+ ctlr->setup = rockchip_spi_setup;
+ ctlr->cleanup = rockchip_spi_cleanup;
ctlr->transfer_one = rockchip_spi_transfer_one;
ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
ctlr->handle_err = rockchip_spi_handle_err;
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v8 6/6] spi: rockchip: Support SPI_CS_HIGH
2021-06-15 3:32 ` [PATCH v8 5/6] spi: rockchip: Support cs-gpio Jon Lin
@ 2021-06-15 3:32 ` Jon Lin
0 siblings, 0 replies; 8+ messages in thread
From: Jon Lin @ 2021-06-15 3:32 UTC (permalink / raw)
To: broonie
Cc: jon.lin, heiko, robh+dt, linux-spi, linux-arm-kernel,
linux-rockchip, linux-kernel, devicetree
1.Add standard spi-cs-high support
2.Refer to spi-controller.yaml for details
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/spi/spi-rockchip.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 48b666d42d8a..d64cca34eef7 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -108,6 +108,8 @@
#define CR0_OPM_MASTER 0x0
#define CR0_OPM_SLAVE 0x1
+#define CR0_SOI_OFFSET 23
+
#define CR0_MTM_OFFSET 0x21
/* Bit fields in SER, 2bit */
@@ -238,7 +240,7 @@ static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
{
struct spi_controller *ctlr = spi->controller;
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
- bool cs_asserted = !enable;
+ bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
/* Return immediately for no-op */
if (cs_asserted == rs->cs_asserted[spi->chip_select])
@@ -509,6 +511,8 @@ static int rockchip_spi_config(struct rockchip_spi *rs,
cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
if (spi->mode & SPI_LSB_FIRST)
cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
+ if (spi->mode & SPI_CS_HIGH)
+ cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
if (xfer->rx_buf && xfer->tx_buf)
cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
@@ -787,7 +791,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
ctlr->auto_runtime_pm = true;
ctlr->bus_num = pdev->id;
- ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
+ ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST | SPI_CS_HIGH;
if (slave_mode) {
ctlr->mode_bits |= SPI_NO_CS;
ctlr->slave_abort = rockchip_spi_slave_abort;
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread