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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: gregkh@linuxfoundation.org
Cc: hemantk@codeaurora.org, bbhatt@codeaurora.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	loic.poulain@linaro.org, Baochen Qiang <bqiang@codeaurora.org>,
	stable@vger.kernel.org,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH 3/8] bus: mhi: Wait for M2 state during system resume
Date: Mon, 21 Jun 2021 21:46:11 +0530	[thread overview]
Message-ID: <20210621161616.77524-4-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20210621161616.77524-1-manivannan.sadhasivam@linaro.org>

From: Baochen Qiang <bqiang@codeaurora.org>

During system resume, MHI host triggers M3->M0 transition and then waits
for target device to enter M0 state. Once done, the device queues a state
change event into ctrl event ring and notifies MHI host by raising an
interrupt, where a tasklet is scheduled to process this event. In most
cases, the tasklet is served timely and wait operation succeeds.

However, there are cases where CPU is busy and cannot serve this tasklet
for some time. Once delay goes long enough, the device moves itself to M1
state and also interrupts MHI host after inserting a new state change
event to ctrl ring. Later when CPU finally has time to process the ring,
there will be two events:

1. For M3->M0 event, which is the first event to be processed queued first.
   The tasklet handler serves the event, updates device state to M0 and
   wakes up the task.

2. For M0->M1 event, which is processed later, the tasklet handler
   triggers M1->M2 transition and updates device state to M2 directly,
   then wakes up the MHI host (if it is still sleeping on this wait queue).

Note that although MHI host has been woken up while processing the first
event, it may still has no chance to run before the second event is
processed. In other words, MHI host has to keep waiting till timeout
causing the M0 state to be missed.

kernel log here:
...
Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3
Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0
Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1
Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2
...

Fix this issue by simply adding M2 as a valid state for resume.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1

Cc: stable@vger.kernel.org
Fixes: 0c6b20a1d720 ("bus: mhi: core: Add support for MHI suspend and resume")
Signed-off-by: Baochen Qiang <bqiang@codeaurora.org>
Reviewed-by: Hemant Kumar <hemantk@codeaurora.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210524040312.14409-1-bqiang@codeaurora.org
[mani: slightly massaged the commit message]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/bus/mhi/core/pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
index 704a5e225097..bbf6cd04861e 100644
--- a/drivers/bus/mhi/core/pm.c
+++ b/drivers/bus/mhi/core/pm.c
@@ -926,6 +926,7 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
 
 	ret = wait_event_timeout(mhi_cntrl->state_event,
 				 mhi_cntrl->dev_state == MHI_STATE_M0 ||
+				 mhi_cntrl->dev_state == MHI_STATE_M2 ||
 				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
 				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
 
-- 
2.25.1


  parent reply	other threads:[~2021-06-21 16:16 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-21 16:16 [PATCH 0/8] MHI patches for v5.14 Manivannan Sadhasivam
2021-06-21 16:16 ` [PATCH 1/8] bus: mhi: core: Validate channel ID when processing command completions Manivannan Sadhasivam
2021-06-24 13:50   ` Greg KH
2021-06-24 14:32     ` Manivannan Sadhasivam
2021-06-24 14:39       ` Greg KH
2021-06-24 14:47         ` Manivannan Sadhasivam
2021-06-24 15:27           ` Greg KH
2021-06-24 15:56             ` Manivannan Sadhasivam
2021-06-21 16:16 ` [PATCH 2/8] bus: mhi: core: Fix power down latency Manivannan Sadhasivam
2021-06-21 16:16 ` Manivannan Sadhasivam [this message]
2021-06-21 16:16 ` [PATCH 4/8] bus: mhi: Add inbound buffers allocation flag Manivannan Sadhasivam
2021-06-24 13:51   ` Greg KH
2021-06-24 15:39     ` Loic Poulain
2021-06-24 16:48       ` Greg KH
2021-06-24 19:01         ` Loic Poulain
2021-06-21 16:16 ` [PATCH 5/8] bus: mhi: pci-generic: Add missing 'pci_disable_pcie_error_reporting()' calls Manivannan Sadhasivam
2021-06-21 16:16 ` [PATCH 6/8] bus: mhi: core: Add support for processing priority of event ring Manivannan Sadhasivam
2021-06-24 13:53   ` Greg KH
2021-06-24 14:24     ` Manivannan Sadhasivam
2021-06-24 14:40       ` Greg KH
2021-06-24 14:50         ` Manivannan Sadhasivam
2021-06-21 16:16 ` [PATCH 7/8] bus: mhi: pci_generic: Apply no-op for wake using sideband wake boolean Manivannan Sadhasivam
2021-06-24 13:54   ` Greg KH
2021-06-21 16:16 ` [PATCH 8/8] bus: mhi: pci_generic: Add Cinterion MV31-W PCIe to MHI Manivannan Sadhasivam
2021-06-24 13:54   ` Greg KH
2021-06-24 13:54 ` [PATCH 0/8] MHI patches for v5.14 Greg KH
2021-06-24 14:20   ` Manivannan Sadhasivam

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