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From: Apurva Nandan <a-nandan@ti.com>
To: Mark Brown <broonie@kernel.org>, <linux-spi@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Cc: Apurva Nandan <a-nandan@ti.com>, Pratyush Yadav <p.yadav@ti.com>,
	Vignesh Raghavendra <vigneshr@ti.com>
Subject: [PATCH 0/2] spi: cadence-quadspi: Fix DTR op checks and timeout in SPI NAND write operations
Date: Tue, 13 Jul 2021 12:57:40 +0000	[thread overview]
Message-ID: <20210713125743.1540-1-a-nandan@ti.com> (raw)

Hi,
This series proposes fixes for cadence-quadspi controller for the
following issues with SPI NAND flashes:

- Due to auto-HW polling without address phase, the cadence-quadspi
  controller timeouts when performing any write operation on SPI NAND
  flash.

- When checking for DTR spi_mem_op, cadence-quadspi doesn't ignore a
  zero length phase in the SPI instruction, resulting in false negatives.

This series has been tested on TI J721e EVM with the Winbond W35N01JW
flash.

Apurva Nandan (2):
  spi: cadence-quadspi: Disable Auto-HW polling
  spi: cadence-quadspi: Fix check condition for DTR ops

 drivers/spi/spi-cadence-quadspi.c | 39 ++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 16 deletions(-)

-- 
2.17.1


             reply	other threads:[~2021-07-13 12:57 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-13 12:57 Apurva Nandan [this message]
2021-07-13 12:57 ` [PATCH 1/2] spi: cadence-quadspi: Disable Auto-HW polling Apurva Nandan
2021-07-13 18:25   ` Mark Brown
2021-07-14 13:22     ` Nandan, Apurva
2021-07-14 16:28       ` Mark Brown
2021-07-14 17:51         ` Apurva Nandan
2021-07-15 16:27           ` Apurva Nandan
2021-07-15 16:41             ` Mark Brown
2021-07-15 18:36               ` Pratyush Yadav
2021-07-16 18:04                 ` Mark Brown
2021-07-13 12:57 ` [PATCH 2/2] spi: cadence-quadspi: Fix check condition for DTR ops Apurva Nandan
2021-07-13 18:39   ` Mark Brown
2021-07-14 12:54     ` [EXTERNAL] " Nandan, Apurva
2021-07-16 18:31 ` (subset) [PATCH 0/2] spi: cadence-quadspi: Fix DTR op checks and timeout in SPI NAND write operations Mark Brown

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