From: Mark Brown <broonie@kernel.org>
To: Apurva Nandan <a-nandan@ti.com>
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
Pratyush Yadav <p.yadav@ti.com>,
Vignesh Raghavendra <vigneshr@ti.com>
Subject: Re: [PATCH 1/2] spi: cadence-quadspi: Disable Auto-HW polling
Date: Tue, 13 Jul 2021 19:25:50 +0100 [thread overview]
Message-ID: <20210713182550.GG4098@sirena.org.uk> (raw)
In-Reply-To: <20210713125743.1540-2-a-nandan@ti.com>
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On Tue, Jul 13, 2021 at 12:57:41PM +0000, Apurva Nandan wrote:
> cadence-quadspi controller doesn't allow an address phase when
> auto-polling the busy bit on the status register. Unlike SPI NOR
> flashes, SPI NAND flashes do require the address of status register
> when polling the busy bit using the read register operation. As
> Auto-HW polling is enabled by default, cadence-quadspi returns a
> timeout for every write operation after an indefinite amount of
> polling on SPI NAND flashes.
> Disable Auto-HW polling completely as the spi-nor core, spinand core,
> etc. take care of polling the busy bit on their own.
Would it not be better to only disable this on NAND rather than
disabling it completely?
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next prev parent reply other threads:[~2021-07-13 18:26 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-13 12:57 [PATCH 0/2] spi: cadence-quadspi: Fix DTR op checks and timeout in SPI NAND write operations Apurva Nandan
2021-07-13 12:57 ` [PATCH 1/2] spi: cadence-quadspi: Disable Auto-HW polling Apurva Nandan
2021-07-13 18:25 ` Mark Brown [this message]
2021-07-14 13:22 ` Nandan, Apurva
2021-07-14 16:28 ` Mark Brown
2021-07-14 17:51 ` Apurva Nandan
2021-07-15 16:27 ` Apurva Nandan
2021-07-15 16:41 ` Mark Brown
2021-07-15 18:36 ` Pratyush Yadav
2021-07-16 18:04 ` Mark Brown
2021-07-13 12:57 ` [PATCH 2/2] spi: cadence-quadspi: Fix check condition for DTR ops Apurva Nandan
2021-07-13 18:39 ` Mark Brown
2021-07-14 12:54 ` [EXTERNAL] " Nandan, Apurva
2021-07-16 18:31 ` (subset) [PATCH 0/2] spi: cadence-quadspi: Fix DTR op checks and timeout in SPI NAND write operations Mark Brown
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