* [v6,1/3] dt-bindings: mediatek: mt8195: update mtk-wdt document [not found] <20210723093127.24568-1-Christine.Zhu@mediatek.com> @ 2021-07-23 9:31 ` Christine Zhu 2021-07-23 9:31 ` [v6,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller header file Christine Zhu 1 sibling, 0 replies; 4+ messages in thread From: Christine Zhu @ 2021-07-23 9:31 UTC (permalink / raw) To: wim, linux, robh+dt, matthias.bgg Cc: srv_heupstream, linux-mediatek, linux-arm-kernel, linux-kernel, linux-watchdog, devicetree, seiya.wang, Rex-BC.Chen, Christine Zhu Update mtk-wdt document for MT8195 platform. Signed-off-by: Christine Zhu <Christine.Zhu@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index e36ba60de829..ca9b67ab7c44 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -13,6 +13,7 @@ Required properties: "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 "mediatek,mt8192-wdt": for MT8192 + "mediatek,mt8195-wdt": for MT8195 - reg : Specifies base physical address and size of the registers. -- 2.18.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [v6,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller header file [not found] <20210723093127.24568-1-Christine.Zhu@mediatek.com> 2021-07-23 9:31 ` [v6,1/3] dt-bindings: mediatek: mt8195: update mtk-wdt document Christine Zhu @ 2021-07-23 9:31 ` Christine Zhu 1 sibling, 0 replies; 4+ messages in thread From: Christine Zhu @ 2021-07-23 9:31 UTC (permalink / raw) To: wim, linux, robh+dt, matthias.bgg Cc: srv_heupstream, linux-mediatek, linux-arm-kernel, linux-kernel, linux-watchdog, devicetree, seiya.wang, Rex-BC.Chen, Christine Zhu Add toprgu reset-controller header file for MT8195 platform Signed-off-by: Christine Zhu <Christine.Zhu@mediatek.com> --- .../reset-controller/mt8195-resets.h | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h new file mode 100644 index 000000000000..8176a3e5063f --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8195-resets.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either licens + * + * Copyright (c) 2021 MediaTek Inc. + * Author: Christine Zhu <christine.zhu@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 + +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8195_TOPRGU_APU_SW_RST 2 +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +#define MT8195_TOPRGU_MMSYS_SW_RST 7 +#define MT8195_TOPRGU_MFG_SW_RST 8 +#define MT8195_TOPRGU_VENC_SW_RST 9 +#define MT8195_TOPRGU_VDEC_SW_RST 10 +#define MT8195_TOPRGU_IMG_SW_RST 11 +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8195_TOPRGU_AUDIO_SW_RST 14 +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +#define MT8195_TOPRGU_EDPTX_SW_RST 16 +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8195_TOPRGU_DPTX_SW_RST 22 +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8195_TOPRGU_SW_RST_NUM 16 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ -- 2.18.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
[parent not found: <20210723094138.24793-1-Christine.Zhu@mediatek.com>]
* [v6,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller header file [not found] <20210723094138.24793-1-Christine.Zhu@mediatek.com> @ 2021-07-23 9:41 ` Christine Zhu 2021-07-23 9:54 ` Enric Balletbo Serra 0 siblings, 1 reply; 4+ messages in thread From: Christine Zhu @ 2021-07-23 9:41 UTC (permalink / raw) To: wim, linux, robh+dt, matthias.bgg Cc: srv_heupstream, linux-mediatek, linux-arm-kernel, linux-kernel, linux-watchdog, devicetree, seiya.wang, Rex-BC.Chen, Christine Zhu Add toprgu reset-controller header file for MT8195 platform Signed-off-by: Christine Zhu <Christine.Zhu@mediatek.com> --- .../reset-controller/mt8195-resets.h | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h new file mode 100644 index 000000000000..8176a3e5063f --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8195-resets.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either licens + * + * Copyright (c) 2021 MediaTek Inc. + * Author: Christine Zhu <christine.zhu@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 + +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8195_TOPRGU_APU_SW_RST 2 +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +#define MT8195_TOPRGU_MMSYS_SW_RST 7 +#define MT8195_TOPRGU_MFG_SW_RST 8 +#define MT8195_TOPRGU_VENC_SW_RST 9 +#define MT8195_TOPRGU_VDEC_SW_RST 10 +#define MT8195_TOPRGU_IMG_SW_RST 11 +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8195_TOPRGU_AUDIO_SW_RST 14 +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +#define MT8195_TOPRGU_EDPTX_SW_RST 16 +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8195_TOPRGU_DPTX_SW_RST 22 +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8195_TOPRGU_SW_RST_NUM 16 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ -- 2.18.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [v6,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller header file 2021-07-23 9:41 ` Christine Zhu @ 2021-07-23 9:54 ` Enric Balletbo Serra 0 siblings, 0 replies; 4+ messages in thread From: Enric Balletbo Serra @ 2021-07-23 9:54 UTC (permalink / raw) To: Christine Zhu Cc: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Matthias Brugger, srv_heupstream, moderated list:ARM/Mediatek SoC support, Linux ARM, linux-kernel, linux-watchdog, devicetree, Seiya Wang, Rex-BC Chen Hi Christine, Thank you for your patch. Missatge de Christine Zhu <Christine.Zhu@mediatek.com> del dia dv., 23 de jul. 2021 a les 11:45: > > Add toprgu reset-controller header file for MT8195 platform > > Signed-off-by: Christine Zhu <Christine.Zhu@mediatek.com> > --- > .../reset-controller/mt8195-resets.h | 32 +++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h > > diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h The DT binding includes for reset controllers are located in `include/dt-bindings/reset/` Move the Mediatek reset constants there instead of the `reset-controller`directory. We're doing this also for current files that are there, see [1] [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210714121116.v2.1.I514d9aafff3a062f751b37d3fea7402f67595b86@changeid/ > new file mode 100644 > index 000000000000..8176a3e5063f > --- /dev/null > +++ b/include/dt-bindings/reset-controller/mt8195-resets.h > @@ -0,0 +1,32 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ > +/* > + * This file is provided under a dual BSD/GPLv2 license. When using or > + * redistributing this file, you may do so under either licens This is implicit in the SPDX-License-Identifier, so you can remove these two lines. Thanks, Enric > + * > + * Copyright (c) 2021 MediaTek Inc. > + * Author: Christine Zhu <christine.zhu@mediatek.com> > + */ > + > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 > +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 > + > +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 > +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 > +#define MT8195_TOPRGU_APU_SW_RST 2 > +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 > +#define MT8195_TOPRGU_MMSYS_SW_RST 7 > +#define MT8195_TOPRGU_MFG_SW_RST 8 > +#define MT8195_TOPRGU_VENC_SW_RST 9 > +#define MT8195_TOPRGU_VDEC_SW_RST 10 > +#define MT8195_TOPRGU_IMG_SW_RST 11 > +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 > +#define MT8195_TOPRGU_AUDIO_SW_RST 14 > +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 > +#define MT8195_TOPRGU_EDPTX_SW_RST 16 > +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 > +#define MT8195_TOPRGU_DPTX_SW_RST 22 > +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 > + > +#define MT8195_TOPRGU_SW_RST_NUM 16 > + > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ > -- > 2.18.0 > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-07-23 9:54 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- [not found] <20210723093127.24568-1-Christine.Zhu@mediatek.com> 2021-07-23 9:31 ` [v6,1/3] dt-bindings: mediatek: mt8195: update mtk-wdt document Christine Zhu 2021-07-23 9:31 ` [v6,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller header file Christine Zhu [not found] <20210723094138.24793-1-Christine.Zhu@mediatek.com> 2021-07-23 9:41 ` Christine Zhu 2021-07-23 9:54 ` Enric Balletbo Serra
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