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From: Peter Geis <pgwipeout@gmail.com>
To: Rob Herring <robh+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de>
Cc: Peter Geis <pgwipeout@gmail.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 5/8] arm64: dts: rockchip: add rk3568 tsadc nodes
Date: Wed, 28 Jul 2021 14:00:31 -0400	[thread overview]
Message-ID: <20210728180034.717953-6-pgwipeout@gmail.com> (raw)
In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com>

Add the thermal and tsadc nodes to the rk3568 device tree.
There are two sensors, one for the cpu, one for the gpu.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 .../boot/dts/rockchip/rk3568-pinctrl.dtsi     |  7 ++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 70 +++++++++++++++++++
 2 files changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
index a588ca95ace2..3b1efaf2646e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
@@ -2420,6 +2420,13 @@ spi3m1_cs1: spi3m1-cs1 {
 	};
 
 	tsadc {
+		/omit-if-no-ref/
+		tsadc_pin: tsadc-pin {
+			rockchip,pins =
+				/* tsadc_pin */
+				<0 RK_PA1 0 &pcfg_pull_none>;
+		};
+
 		/omit-if-no-ref/
 		tsadcm0_shut: tsadcm0-shut {
 			rockchip,pins =
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index fbd9f1c366ff..c74072941da1 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -50,6 +50,7 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x0>;
 			clocks = <&scmi_clk 0>;
+			#cooling-cells = <2>;
 			enable-method = "psci";
 			operating-points-v2 = <&cpu0_opp_table>;
 		};
@@ -58,6 +59,7 @@ cpu1: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x100>;
+			#cooling-cells = <2>;
 			enable-method = "psci";
 			operating-points-v2 = <&cpu0_opp_table>;
 		};
@@ -66,6 +68,7 @@ cpu2: cpu@200 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x200>;
+			#cooling-cells = <2>;
 			enable-method = "psci";
 			operating-points-v2 = <&cpu0_opp_table>;
 		};
@@ -74,6 +77,7 @@ cpu3: cpu@300 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x300>;
+			#cooling-cells = <2>;
 			enable-method = "psci";
 			operating-points-v2 = <&cpu0_opp_table>;
 		};
@@ -773,6 +777,72 @@ uart9: serial@fe6d0000 {
 		status = "disabled";
 	};
 
+	thermal_zones: thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <100>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsadc 0>;
+
+			trips {
+				cpu_alert0: cpu_alert0 {
+					temperature = <70000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_alert1: cpu_alert1 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit: cpu_crit {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu_thermal: gpu-thermal {
+			polling-delay-passive = <20>; /* milliseconds */
+			polling-delay = <1000>; /* milliseconds */
+
+			thermal-sensors = <&tsadc 1>;
+		};
+	};
+
+	tsadc: tsadc@fe710000 {
+		compatible = "rockchip,rk3568-tsadc";
+		reg = <0x0 0xfe710000 0x0 0x100>;
+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+		assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
+		assigned-clock-rates = <17000000>, <700000>;
+		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
+		clock-names = "tsadc", "apb_pclk";
+		resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
+			 <&cru SRST_TSADCPHY>;
+		reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
+		rockchip,grf = <&grf>;
+		rockchip,hw-tshut-temp = <95000>;
+		pinctrl-names = "init", "default", "sleep";
+		pinctrl-0 = <&tsadc_pin>;
+		pinctrl-1 = <&tsadc_shutorg>;
+		pinctrl-2 = <&tsadc_pin>;
+		#thermal-sensor-cells = <1>;
+		status = "disabled";
+	};
+
 	saradc: saradc@fe720000 {
 		compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
 		reg = <0x0 0xfe720000 0x0 0x100>;
-- 
2.25.1


  parent reply	other threads:[~2021-07-28 18:01 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-28 18:00 [PATCH v2 0/8] fixes and enablement for rk356x Peter Geis
2021-07-28 18:00 ` [PATCH v2 1/8] arm64: dts: rockchip: fix rk3568 mbi-alias Peter Geis
2021-07-28 18:00 ` [PATCH v2 2/8] clk: rockchip: fix clk-pll rk356x early pll init Peter Geis
2021-07-28 18:00 ` [PATCH v2 3/8] arm64: dts: rockchip: add rk356x gpio debounce clocks Peter Geis
2021-07-28 18:00 ` [PATCH v2 4/8] arm64: dts: rockchip: add rk356x gmac1 node Peter Geis
2021-07-28 18:00 ` Peter Geis [this message]
2021-07-28 21:17   ` [PATCH v2 5/8] arm64: dts: rockchip: add rk3568 tsadc nodes Heiko Stübner
2021-07-28 18:00 ` [PATCH v2 6/8] arm64: dts: rockchip: adjust rk3568 pll clocks Peter Geis
2021-07-28 18:00 ` [PATCH v2 7/8] arm64: dts: rockchip: enable gmac node on quartz64-a Peter Geis
2021-07-28 18:00 ` [PATCH v2 8/8] arm64: dts: rockchip: add thermal support to Quartz64 Model A Peter Geis
2021-07-29 13:19 ` (subset) [PATCH v2 0/8] fixes and enablement for rk356x Heiko Stuebner
2021-08-18 21:25 ` Heiko Stuebner
2021-08-18 21:42 ` Heiko Stuebner

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