From: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
To: Ulf Hansson <ulf.hansson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Atish Patra <atish.patra@wdc.com>,
Yash Shah <yash.shah@sifive.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Piotr Sroka <piotrs@cadence.com>,
linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH 1/6] dt-bindings: riscv: correct e51 and u54-mc CPU bindings
Date: Thu, 19 Aug 2021 17:44:31 +0200 [thread overview]
Message-ID: <20210819154436.117798-1-krzysztof.kozlowski@canonical.com> (raw)
All existing boards with sifive,e51 and sifive,u54-mc use it on top of
sifive,rocket0 compatible:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed:
['sifive,e51', 'sifive,rocket0', 'riscv'] is too long
Additional items are not allowed ('riscv' was unexpected)
Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected)
'riscv' was expected
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e534f6a7cfa1..aa5fb64d57eb 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -31,9 +31,7 @@ properties:
- sifive,bullet0
- sifive,e5
- sifive,e7
- - sifive,e51
- sifive,e71
- - sifive,u54-mc
- sifive,u74-mc
- sifive,u54
- sifive,u74
@@ -41,6 +39,12 @@ properties:
- sifive,u7
- canaan,k210
- const: riscv
+ - items:
+ - enum:
+ - sifive,e51
+ - sifive,u54-mc
+ - const: sifive,rocket0
+ - const: riscv
- const: riscv # Simulator only
description:
Identifies that the hart uses the RISC-V instruction set
--
2.30.2
next reply other threads:[~2021-08-19 15:45 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-19 15:44 Krzysztof Kozlowski [this message]
2021-08-19 15:44 ` [PATCH 2/6] dt-bindings: mmc: cdns: match MPFS MMC/SDHCI controller Krzysztof Kozlowski
2021-08-24 14:33 ` Rob Herring
2021-08-24 19:02 ` Krzysztof Kozlowski
2021-08-30 15:09 ` Rob Herring
2021-09-06 8:38 ` Conor.Dooley
2021-09-08 7:37 ` Krzysztof Kozlowski
2021-08-19 15:44 ` [PATCH 3/6] riscv: microchip: mpfs: drop duplicated nodes Krzysztof Kozlowski
2021-08-19 16:21 ` Krzysztof Kozlowski
2021-08-24 15:32 ` Geert Uytterhoeven
2021-08-19 15:44 ` [PATCH 4/6] riscv: microchip: mpfs: fix board compatible Krzysztof Kozlowski
2021-08-24 15:29 ` Geert Uytterhoeven
2021-08-24 19:05 ` Krzysztof Kozlowski
2021-08-19 15:44 ` [PATCH 5/6] riscv: microchip: mpfs: drop duplicated MMC/SDHC node Krzysztof Kozlowski
2021-08-24 15:37 ` Geert Uytterhoeven
2021-08-24 19:07 ` Krzysztof Kozlowski
2021-08-19 15:44 ` [PATCH 6/6] riscv: microchip: mpfs: drop unused pinctrl-names Krzysztof Kozlowski
2021-08-24 15:34 ` Geert Uytterhoeven
2021-08-24 14:34 ` [PATCH 1/6] dt-bindings: riscv: correct e51 and u54-mc CPU bindings Rob Herring
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