From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Rob Herring <robh+dt@kernel.org>
Cc: Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [RFC PATCH v4 09/10] clocksource: clint: Add support for ACLINT MTIMER device
Date: Thu, 7 Oct 2021 18:06:31 +0530 [thread overview]
Message-ID: <20211007123632.697666-10-anup.patel@wdc.com> (raw)
In-Reply-To: <20211007123632.697666-1-anup.patel@wdc.com>
The RISC-V ACLINT specification is a modular specification and the
ACLINT MTIMER device is backward compatible with the M-mode timer
functionality of the CLINT device. This patch extends the CLINT
timer driver to support both CLINT device and ACLINT MTIMER device.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
drivers/clocksource/timer-clint.c | 59 ++++++++++++++++++++++++-------
1 file changed, 47 insertions(+), 12 deletions(-)
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index 3b68ed53fe4a..9d38dfce374e 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -2,8 +2,16 @@
/*
* Copyright (C) 2020 Western Digital Corporation or its affiliates.
*
- * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
- * CLINT MMIO timer device.
+ * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT
+ * MMIO device which is a composite device capable of injecting M-mode
+ * software interrupts and M-mode timer interrupts.
+ *
+ * The RISC-V ACLINT specification is modular in nature and defines
+ * separate devices for M-mode software interrupt (MSWI), M-mode timer
+ * (MTIMER) and S-mode software interrupt (SSWI).
+ *
+ * This is a common timer driver for the CLINT device and the ACLINT
+ * MTIMER device.
*/
#define pr_fmt(fmt) "clint: " fmt
@@ -17,12 +25,16 @@
#include <linux/sched_clock.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/interrupt.h>
+#include <linux/irqchip/irq-riscv-aclint-swi.h>
#include <linux/of_irq.h>
#include <linux/smp.h>
#include <linux/timex.h>
-#ifndef CONFIG_RISCV_M_MODE
+#ifdef CONFIG_RISCV_M_MODE
#include <asm/clint.h>
+
+u64 __iomem *clint_time_val;
+EXPORT_SYMBOL(clint_time_val);
#endif
#define CLINT_IPI_OFF 0
@@ -35,11 +47,6 @@ static u64 __iomem *clint_timer_val;
static unsigned long clint_timer_freq;
static unsigned int clint_timer_irq;
-#ifdef CONFIG_RISCV_M_MODE
-u64 __iomem *clint_time_val;
-EXPORT_SYMBOL(clint_time_val);
-#endif
-
#ifdef CONFIG_64BIT
#define clint_get_cycles() readq_relaxed(clint_timer_val)
#else
@@ -129,8 +136,10 @@ static int __init clint_timer_init_dt(struct device_node *np)
{
int rc;
u32 i, nr_irqs;
- void __iomem *base;
+ void __iomem *base = NULL;
+ void __iomem *base1 = NULL;
struct of_phandle_args oirq;
+ bool is_aclint = of_device_is_compatible(np, "riscv,aclint-mtimer");
/*
* Ensure that CLINT device interrupts are either RV_IRQ_TIMER or
@@ -170,8 +179,19 @@ static int __init clint_timer_init_dt(struct device_node *np)
return -ENODEV;
}
- clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
- clint_timer_val = base + CLINT_TIMER_VAL_OFF;
+ if (is_aclint) {
+ clint_timer_val = base;
+ base1 = of_iomap(np, 1);
+ if (!base1) {
+ rc = -ENODEV;
+ pr_err("%pOFP: could not map registers\n", np);
+ goto fail_iounmap;
+ }
+ clint_timer_cmp = base1;
+ } else {
+ clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
+ clint_timer_val = base + CLINT_TIMER_VAL_OFF;
+ }
clint_timer_freq = riscv_timebase;
#ifdef CONFIG_RISCV_M_MODE
@@ -208,14 +228,29 @@ static int __init clint_timer_init_dt(struct device_node *np)
goto fail_free_irq;
}
+ if (!is_aclint) {
+ rc = aclint_swi_init(np, base + CLINT_IPI_OFF);
+ if (rc) {
+ pr_err("%pOFP: aclint swi init failed [%d]\n",
+ np, rc);
+ goto fail_remove_cpuhp;
+ }
+ }
+
return 0;
+fail_remove_cpuhp:
+ cpuhp_remove_state(CPUHP_AP_CLINT_TIMER_STARTING);
fail_free_irq:
free_irq(clint_timer_irq, &clint_clock_event);
fail_iounmap:
- iounmap(base);
+ if (base1)
+ iounmap(base1);
+ if (base)
+ iounmap(base);
return rc;
}
TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
+TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt);
--
2.25.1
next prev parent reply other threads:[~2021-10-07 12:38 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-07 12:36 [RFC PATCH v4 00/10] Linux RISC-V ACLINT Support Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 02/10] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 03/10] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 04/10] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 05/10] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Anup Patel
2021-10-08 2:46 ` Rob Herring
2021-10-08 5:46 ` Anup Patel
2023-06-16 14:39 ` Vivian Wang
2021-10-07 12:36 ` [RFC PATCH v4 06/10] irqchip: Add ACLINT software interrupt driver Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 07/10] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel
2021-10-08 2:46 ` Rob Herring
2021-10-08 5:48 ` Anup Patel
2021-10-08 20:02 ` Rob Herring
2021-10-07 12:36 ` Anup Patel [this message]
2021-10-07 12:36 ` [RFC PATCH v4 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211007123632.697666-10-anup.patel@wdc.com \
--to=anup.patel@wdc.com \
--cc=Alistair.Francis@wdc.com \
--cc=anup@brainfault.org \
--cc=atish.patra@wdc.com \
--cc=bmeng.cn@gmail.com \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=palmerdabbelt@google.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).