From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Rob Herring <robh+dt@kernel.org>
Cc: Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [RFC PATCH v4 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings
Date: Thu, 7 Oct 2021 18:06:30 +0530 [thread overview]
Message-ID: <20211007123632.697666-9-anup.patel@wdc.com> (raw)
In-Reply-To: <20211007123632.697666-1-anup.patel@wdc.com>
We add DT bindings documentation for the ACLINT MTIMER device
found on RISC-V SOCs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
.../bindings/timer/riscv,aclint-mtimer.yaml | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
new file mode 100644
index 000000000000..ebb7e81a5a12
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V ACLINT M-level Timer
+
+maintainers:
+ - Anup Patel <anup.patel@wdc.com>
+
+description:
+ RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined
+ in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The
+ ACLINT MTIMER device is documented in the RISC-V ACLINT specification found
+ at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
+
+ The ACLINT MTIMER device directly connects to the M-level timer interrupt
+ lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local
+ interrupt controller is the parent interrupt controller for the ACLINT
+ MTIMER device.
+
+ The clock frequency of ACLINT is specified via "timebase-frequency" DT
+ property of "/cpus" DT node. The "timebase-frequency" DT property is
+ described in Documentation/devicetree/bindings/riscv/cpus.yaml
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - sifive,fu540-c000-aclint-mtimer
+ - const: riscv,aclint-mtimer
+
+ description:
+ Should be "<vendor>,<chip>-aclint-mtimer" and "riscv,aclint-mtimer".
+
+ reg:
+ description: |
+ Specifies base physical address(s) of the MTIME register and MTIMECMPx
+ registers. The 1st region is the MTIME register base and size. The 2nd
+ region is the MTIMECMPx registers base and size.
+ minItems: 2
+ maxItems: 2
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4095
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+
+examples:
+ - |
+ timer@2004000 {
+ compatible = "sifive,fu540-c000-aclint-mtimer", "riscv,aclint-mtimer";
+ reg = <0x200bff8 0x8>,
+ <0x2004000 0x7ff8>;
+ interrupts-extended = <&cpu1intc 7>,
+ <&cpu2intc 7>,
+ <&cpu3intc 7>,
+ <&cpu4intc 7>;
+ };
+...
--
2.25.1
next prev parent reply other threads:[~2021-10-07 12:38 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-07 12:36 [RFC PATCH v4 00/10] Linux RISC-V ACLINT Support Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 02/10] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 03/10] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 04/10] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 05/10] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Anup Patel
2021-10-08 2:46 ` Rob Herring
2021-10-08 5:46 ` Anup Patel
2023-06-16 14:39 ` Vivian Wang
2021-10-07 12:36 ` [RFC PATCH v4 06/10] irqchip: Add ACLINT software interrupt driver Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 07/10] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel
2021-10-07 12:36 ` Anup Patel [this message]
2021-10-08 2:46 ` [RFC PATCH v4 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings Rob Herring
2021-10-08 5:48 ` Anup Patel
2021-10-08 20:02 ` Rob Herring
2021-10-07 12:36 ` [RFC PATCH v4 09/10] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel
2021-10-07 12:36 ` [RFC PATCH v4 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel
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