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From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Peter Shier <pshier@google.com>,
	Raghavendra Rao Ananta <rananta@google.com>,
	Ricardo Koller <ricarkol@google.com>,
	Oliver Upton <oupton@google.com>, Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	kernel-team@android.com
Subject: [PATCH v3 11/17] clocksource/arm_arch_timer: Drop unnecessary ISB on CVAL programming
Date: Sun, 10 Oct 2021 12:43:00 +0100	[thread overview]
Message-ID: <20211010114306.2910453-12-maz@kernel.org> (raw)
In-Reply-To: <20211010114306.2910453-1-maz@kernel.org>

Switching from TVAL to CVAL has a small drawback: we need an ISB
before reading the counter. We cannot get rid of it, but we can
instead remove the one that comes just after writing to CVAL.

This reduces the number of ISBs from 3 to 2 when programming
the timer.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm/include/asm/arch_timer.h   | 4 ++--
 arch/arm64/include/asm/arch_timer.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 9f4b895b78f7..bb129b6d2366 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -31,6 +31,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
 		switch (reg) {
 		case ARCH_TIMER_REG_CTRL:
 			asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" ((u32)val));
+			isb();
 			break;
 		case ARCH_TIMER_REG_CVAL:
 			asm volatile("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
@@ -42,6 +43,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
 		switch (reg) {
 		case ARCH_TIMER_REG_CTRL:
 			asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" ((u32)val));
+			isb();
 			break;
 		case ARCH_TIMER_REG_CVAL:
 			asm volatile("mcrr p15, 3, %Q0, %R0, c14" : : "r" (val));
@@ -52,8 +54,6 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
 	} else {
 		BUILD_BUG();
 	}
-
-	isb();
 }
 
 static __always_inline
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index 4f4aa13dd01e..b8000ef71a2c 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -95,6 +95,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
 		switch (reg) {
 		case ARCH_TIMER_REG_CTRL:
 			write_sysreg(val, cntp_ctl_el0);
+			isb();
 			break;
 		case ARCH_TIMER_REG_CVAL:
 			write_sysreg(val, cntp_cval_el0);
@@ -106,6 +107,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
 		switch (reg) {
 		case ARCH_TIMER_REG_CTRL:
 			write_sysreg(val, cntv_ctl_el0);
+			isb();
 			break;
 		case ARCH_TIMER_REG_CVAL:
 			write_sysreg(val, cntv_cval_el0);
@@ -116,8 +118,6 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
 	} else {
 		BUILD_BUG();
 	}
-
-	isb();
 }
 
 static __always_inline
-- 
2.30.2


  parent reply	other threads:[~2021-10-10 11:57 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-10 11:42 [PATCH v3 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 01/17] clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 02/17] clocksource/arm_arch_timer: Drop CNT*_TVAL read accessors Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 03/17] clocksource/arm_arch_timer: Extend write side of timer register accessors to u64 Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 04/17] clocksource/arm_arch_timer: Move system register timer programming over to CVAL Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 05/17] clocksource/arm_arch_timer: Move drop _tval from erratum function names Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 06/17] clocksource/arm_arch_timer: Fix MMIO base address vs callback ordering issue Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 07/17] clocksource/arm_arch_timer: Move MMIO timer programming over to CVAL Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 08/17] clocksource/arm_arch_timer: Advertise 56bit timer to the core code Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 09/17] clocksource/arm_arch_timer: Work around broken CVAL implementations Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 10/17] clocksource/arm_arch_timer: Remove any trace of the TVAL programming interface Marc Zyngier
2021-10-10 11:43 ` Marc Zyngier [this message]
2021-10-10 11:43 ` [PATCH v3 12/17] clocksource/arm_arch_timer: Fix masking for high freq counters Marc Zyngier
2021-10-10 11:43 ` [PATCH v3 13/17] clocksource/arch_arm_timer: Move workaround synchronisation around Marc Zyngier
2021-10-10 11:43 ` [PATCH v3 14/17] arm64: Add a capability for FEAT_ECV Marc Zyngier
2021-10-11 10:56   ` Will Deacon
2021-10-11 10:57     ` Will Deacon
2021-10-10 11:43 ` [PATCH v3 15/17] arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0 Marc Zyngier
2021-10-11 10:33   ` Will Deacon
2021-10-10 11:43 ` [PATCH v3 16/17] arm64: Add handling of CNTVCTSS traps Marc Zyngier
2021-10-11 10:54   ` Will Deacon
2021-10-10 11:43 ` [PATCH v3 17/17] arm64: Add HWCAP for self-synchronising virtual counter Marc Zyngier
2021-10-11 11:00   ` Will Deacon
2021-10-11 11:02 ` [PATCH v3 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support Will Deacon
2021-10-11 13:39   ` Marc Zyngier
2021-10-16 21:59     ` Daniel Lezcano
2021-10-17  9:57       ` Marc Zyngier
2021-10-18  7:51         ` Daniel Lezcano
2021-10-19  8:00           ` Marc Zyngier
2021-10-19  8:04             ` Daniel Lezcano
2021-10-19 11:09           ` Will Deacon
2021-10-19 11:10             ` Daniel Lezcano

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