From: Will Deacon <will@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Mark Rutland <mark.rutland@arm.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Shier <pshier@google.com>,
Raghavendra Rao Ananta <rananta@google.com>,
Ricardo Koller <ricarkol@google.com>,
Oliver Upton <oupton@google.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Linus Walleij <linus.walleij@linaro.org>,
kernel-team@android.com
Subject: Re: [PATCH v3 15/17] arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0
Date: Mon, 11 Oct 2021 11:33:09 +0100 [thread overview]
Message-ID: <20211011103308.GE3681@willie-the-truck> (raw)
In-Reply-To: <20211010114306.2910453-16-maz@kernel.org>
On Sun, Oct 10, 2021 at 12:43:04PM +0100, Marc Zyngier wrote:
> CNTPCTSS_EL0 and CNTVCTSS_EL0 are alternatives to the usual
> CNTPCT_EL0 and CNTVCT_EL0 that do not require a previous ISB
> to be synchronised (SS stands for Self-Synchronising).
>
> Use the ARM64_HAS_ECV capability to control alternative sequences
> that switch to these low(er)-cost primitives. Note that the
> counter access in the VDSO is for now left alone until we decide
> whether we want to allow this.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/include/asm/arch_timer.h | 32 +++++++++++++++++++++--------
> arch/arm64/include/asm/sysreg.h | 3 +++
> 2 files changed, 27 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
> index 519ac1f7f859..33a08fff0f06 100644
> --- a/arch/arm64/include/asm/arch_timer.h
> +++ b/arch/arm64/include/asm/arch_timer.h
> @@ -64,14 +64,26 @@ DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *,
>
> static inline notrace u64 arch_timer_read_cntpct_el0(void)
> {
> - isb();
> - return read_sysreg(cntpct_el0);
> + u64 cnt;
> +
> + asm volatile(ALTERNATIVE("isb\n mrs %x0, cntpct_el0",
> + "nop\n" __mrs_s("%x0", SYS_CNTPCTSS_EL0),
> + ARM64_HAS_ECV)
> + : "=r" (cnt));
> +
> + return cnt;
Why do you need to use %x0 instead of just %0 here? Similarly for the other
functions you're changing in this file.
Will
next prev parent reply other threads:[~2021-10-11 10:33 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-10 11:42 [PATCH v3 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 01/17] clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 02/17] clocksource/arm_arch_timer: Drop CNT*_TVAL read accessors Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 03/17] clocksource/arm_arch_timer: Extend write side of timer register accessors to u64 Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 04/17] clocksource/arm_arch_timer: Move system register timer programming over to CVAL Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 05/17] clocksource/arm_arch_timer: Move drop _tval from erratum function names Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 06/17] clocksource/arm_arch_timer: Fix MMIO base address vs callback ordering issue Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 07/17] clocksource/arm_arch_timer: Move MMIO timer programming over to CVAL Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 08/17] clocksource/arm_arch_timer: Advertise 56bit timer to the core code Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 09/17] clocksource/arm_arch_timer: Work around broken CVAL implementations Marc Zyngier
2021-10-10 11:42 ` [PATCH v3 10/17] clocksource/arm_arch_timer: Remove any trace of the TVAL programming interface Marc Zyngier
2021-10-10 11:43 ` [PATCH v3 11/17] clocksource/arm_arch_timer: Drop unnecessary ISB on CVAL programming Marc Zyngier
2021-10-10 11:43 ` [PATCH v3 12/17] clocksource/arm_arch_timer: Fix masking for high freq counters Marc Zyngier
2021-10-10 11:43 ` [PATCH v3 13/17] clocksource/arch_arm_timer: Move workaround synchronisation around Marc Zyngier
2021-10-10 11:43 ` [PATCH v3 14/17] arm64: Add a capability for FEAT_ECV Marc Zyngier
2021-10-11 10:56 ` Will Deacon
2021-10-11 10:57 ` Will Deacon
2021-10-10 11:43 ` [PATCH v3 15/17] arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0 Marc Zyngier
2021-10-11 10:33 ` Will Deacon [this message]
2021-10-10 11:43 ` [PATCH v3 16/17] arm64: Add handling of CNTVCTSS traps Marc Zyngier
2021-10-11 10:54 ` Will Deacon
2021-10-10 11:43 ` [PATCH v3 17/17] arm64: Add HWCAP for self-synchronising virtual counter Marc Zyngier
2021-10-11 11:00 ` Will Deacon
2021-10-11 11:02 ` [PATCH v3 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6 support Will Deacon
2021-10-11 13:39 ` Marc Zyngier
2021-10-16 21:59 ` Daniel Lezcano
2021-10-17 9:57 ` Marc Zyngier
2021-10-18 7:51 ` Daniel Lezcano
2021-10-19 8:00 ` Marc Zyngier
2021-10-19 8:04 ` Daniel Lezcano
2021-10-19 11:09 ` Will Deacon
2021-10-19 11:10 ` Daniel Lezcano
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