From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, "Chang S. Bae" <chang.seok.bae@intel.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Arjan van de Ven <arjan@linux.intel.com>,
kvm@vger.kernel.org, Paolo Bonzini <pbonzini@redhat.com>
Subject: [patch 08/21] x86/fpu/signal: Convert to fpstate
Date: Wed, 13 Oct 2021 16:55:37 +0200 (CEST) [thread overview]
Message-ID: <20211013145322.607370221@linutronix.de> (raw)
In-Reply-To: 20211013142847.120153383@linutronix.de
Convert signal related code to the new register storage mechanism in
preparation for dynamically sized buffers.
No functional change.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/kernel/fpu/signal.c | 30 ++++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
--- a/arch/x86/kernel/fpu/signal.c
+++ b/arch/x86/kernel/fpu/signal.c
@@ -72,13 +72,13 @@ static inline bool check_xstate_in_sigfr
static inline bool save_fsave_header(struct task_struct *tsk, void __user *buf)
{
if (use_fxsr()) {
- struct xregs_state *xsave = &tsk->thread.fpu.state.xsave;
+ struct xregs_state *xsave = &tsk->thread.fpu.fpstate->regs.xsave;
struct user_i387_ia32_struct env;
struct _fpstate_32 __user *fp = buf;
fpregs_lock();
if (!test_thread_flag(TIF_NEED_FPU_LOAD))
- fxsave(&tsk->thread.fpu.state.fxsave);
+ fxsave(&tsk->thread.fpu.fpstate->regs.fxsave);
fpregs_unlock();
convert_from_fxsr(&env, tsk);
@@ -303,7 +303,7 @@ static bool restore_fpregs_from_user(voi
* been restored from a user buffer directly.
*/
if (test_thread_flag(TIF_NEED_FPU_LOAD) && xfeatures_mask_supervisor())
- os_xrstor(&fpu->state.xsave, xfeatures_mask_supervisor());
+ os_xrstor(&fpu->fpstate->regs.xsave, xfeatures_mask_supervisor());
fpregs_mark_activate();
fpregs_unlock();
@@ -317,6 +317,7 @@ static bool __fpu_restore_sig(void __use
struct task_struct *tsk = current;
struct fpu *fpu = &tsk->thread.fpu;
struct user_i387_ia32_struct env;
+ union fpregs_state *fpregs;
u64 user_xfeatures = 0;
bool fx_only = false;
bool success;
@@ -349,6 +350,7 @@ static bool __fpu_restore_sig(void __use
if (__copy_from_user(&env, buf, sizeof(env)))
return false;
+ fpregs = &fpu->fpstate->regs;
/*
* By setting TIF_NEED_FPU_LOAD it is ensured that our xstate is
* not modified on context switch and that the xstate is considered
@@ -366,7 +368,7 @@ static bool __fpu_restore_sig(void __use
* the right place in memory. It's ia32 mode. Shrug.
*/
if (xfeatures_mask_supervisor())
- os_xsave(&fpu->state.xsave);
+ os_xsave(&fpregs->xsave);
set_thread_flag(TIF_NEED_FPU_LOAD);
}
__fpu_invalidate_fpregs_state(fpu);
@@ -374,29 +376,29 @@ static bool __fpu_restore_sig(void __use
fpregs_unlock();
if (use_xsave() && !fx_only) {
- if (copy_sigframe_from_user_to_xstate(&fpu->state.xsave, buf_fx))
+ if (copy_sigframe_from_user_to_xstate(&fpregs->xsave, buf_fx))
return false;
} else {
- if (__copy_from_user(&fpu->state.fxsave, buf_fx,
- sizeof(fpu->state.fxsave)))
+ if (__copy_from_user(&fpregs->fxsave, buf_fx,
+ sizeof(fpregs->fxsave)))
return false;
if (IS_ENABLED(CONFIG_X86_64)) {
/* Reject invalid MXCSR values. */
- if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask)
+ if (fpregs->fxsave.mxcsr & ~mxcsr_feature_mask)
return false;
} else {
/* Mask invalid bits out for historical reasons (broken hardware). */
- fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask;
+ fpregs->fxsave.mxcsr &= ~mxcsr_feature_mask;
}
/* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */
if (use_xsave())
- fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
+ fpregs->xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
}
/* Fold the legacy FP storage */
- convert_to_fxsr(&fpu->state.fxsave, &env);
+ convert_to_fxsr(&fpregs->fxsave, &env);
fpregs_lock();
if (use_xsave()) {
@@ -411,10 +413,10 @@ static bool __fpu_restore_sig(void __use
*/
u64 mask = user_xfeatures | xfeatures_mask_supervisor();
- fpu->state.xsave.header.xfeatures &= mask;
- success = !os_xrstor_safe(&fpu->state.xsave, xfeatures_mask_all);
+ fpregs->xsave.header.xfeatures &= mask;
+ success = !os_xrstor_safe(&fpregs->xsave, xfeatures_mask_all);
} else {
- success = !fxrstor_safe(&fpu->state.fxsave);
+ success = !fxrstor_safe(&fpregs->fxsave);
}
if (likely(success))
next prev parent reply other threads:[~2021-10-13 14:55 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 14:55 [patch 00/21] x86/fpu: Move register state into a container struct (part 2) Thomas Gleixner
2021-10-13 14:55 ` [patch 01/21] x86/fpu: Provide struct fpstate Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 02/21] x86/fpu: Convert fpstate_init() to " Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 03/21] x86/fpu: Convert restore_fpregs_from_fpstate() " Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 04/21] x86/fpu: Replace KVMs xstate component clearing Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 05/21] x86/KVM: Convert to fpstate Thomas Gleixner
2021-10-13 15:11 ` Paolo Bonzini
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 06/21] x86/fpu: Convert tracing " Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 07/21] x86/fpu/regset: Convert " Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` Thomas Gleixner [this message]
2021-10-21 15:12 ` [tip: x86/fpu] x86/fpu/signal: " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 09/21] x86/fpu/core: " Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 10/21] x86/math-emu: " Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 11/21] x86/fpu: Remove fpu::state Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 12/21] x86/fpu: Do not leak fpstate pointer on fork Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 13/21] x86/process: Move arch_thread_struct_whitelist() out of line Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 14/21] x86/fpu: Add size and mask information to fpstate Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 15/21] x86/fpu: Use fpstate::size Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 16/21] x86/fpu/xstate: Use fpstate for os_xsave() Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 17/21] x86/fpu/xstate: Use fpstate for xsave_to_user_sigframe() Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 18/21] x86/fpu: Use fpstate in fpu_copy_kvm_uabi_to_fpstate() Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 19/21] x86/fpu: Use fpstate in __copy_xstate_to_uabi_buf() Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 20/21] x86/fpu/xstate: Use fpstate for copy_uabi_to_xstate() Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-10-13 14:55 ` [patch 21/21] x86/fpu/signal: Use fpstate for size and features Thomas Gleixner
2021-10-14 22:51 ` [patch V2 " Thomas Gleixner
2021-10-21 15:12 ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
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