From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>
Cc: Guo Ren <guoren@linux.alibaba.com>, Bin Meng <bmeng.cn@gmail.com>,
Xiang W <wxjstz@126.com>, Samuel Holland <samuel@sholland.org>,
Atish Patra <atish.patra@wdc.com>,
Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Anup Patel <anup.patel@wdc.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, opensbi@lists.infradead.org,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Subject: [PATCH 1/1] dt-bindings: T-HEAD CLINT
Date: Wed, 20 Oct 2021 11:36:03 +0200 [thread overview]
Message-ID: <20211020093603.28653-1-heinrich.schuchardt@canonical.com> (raw)
The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does
not support 64bit mmio access to the MTIMER device.
OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the
restriction and the "sifive,cling0" compatible string. An OpenSBI
patch suggested to use "reg-io-width = <4>;" as the reg-io-width property
is generally used in the devicetree schema for such a condition.
As the design is not SiFive based it is preferable to apply a compatible
string identifying T-HEAD instead.
Add a new yaml file describing the T-HEAD CLINT.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
@Palmer, @Anup
I copied you as maintainers from sifive,clint.yaml. Please, indicate if
this should be changed.
For the prior discussion see:
https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/
https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/
A release candidate of the ACLINT specification is available at
https://github.com/riscv/riscv-aclint/releases
---
.../bindings/timer/thead,clint.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/thead,clint.yaml
diff --git a/Documentation/devicetree/bindings/timer/thead,clint.yaml b/Documentation/devicetree/bindings/timer/thead,clint.yaml
new file mode 100644
index 000000000000..02463fb2043a
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/thead,clint.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/thead,clint.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive Core Local Interruptor
+
+maintainers:
+ - Palmer Dabbelt <palmer@dabbelt.com>
+ - Anup Patel <anup.patel@wdc.com>
+
+description:
+ T-HEAD (and other RISC-V) SOCs include an implementation of the T-HEAD
+ Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
+ interrupts. It directly connects to the timer and inter-processor interrupt
+ lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
+ interrupt controller is the parent interrupt controller for CLINT device.
+ The clock frequency of the CLINT is specified via "timebase-frequency" DT
+ property of "/cpus" DT node. The "timebase-frequency" DT property is
+ described in Documentation/devicetree/bindings/riscv/cpus.yaml
+
+properties:
+ compatible:
+ items:
+ - const:
+ - allwinner,sun20i-d1-clint
+ - const:
+ - thead,clint0
+
+ description:
+ Should be "<vendor>,<chip>-clint" and "thead,clint<version>" for
+ the T-HEAD derived CLINTs.
+ Supported compatible strings are -
+ "allwinner,sun20i-d1-clint" for the CLINT in the Allwinner D1 SoC
+ and "thead,clint0" for the T-HEAD IP block with no chip
+ integration tweaks.
+
+ reg:
+ maxItems: 1
+
+ interrupts-extended:
+ minItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+
+examples:
+ - |
+ timer@2000000 {
+ compatible = "allwinner,sun20i-d1-clint", "thead,clint0";
+ interrupts-extended = <&cpu1intc 3 &cpu1intc 7
+ &cpu2intc 3 &cpu2intc 7
+ &cpu3intc 3 &cpu3intc 7
+ &cpu4intc 3 &cpu4intc 7>;
+ reg = <0x2000000 0x10000>;
+ };
+...
--
2.32.0
next reply other threads:[~2021-10-20 9:36 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-20 9:36 Heinrich Schuchardt [this message]
2021-10-20 11:27 ` [PATCH 1/1] dt-bindings: T-HEAD CLINT Anup Patel
2021-10-20 11:32 ` Jessica Clarke
2021-10-20 11:42 ` Heinrich Schuchardt
2021-10-20 14:07 ` Anup Patel
2021-10-20 13:50 ` Rob Herring
2021-10-22 21:22 ` Rob Herring
2021-10-23 0:03 ` Heinrich Schuchardt
2021-10-24 5:04 ` Guo Ren
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211020093603.28653-1-heinrich.schuchardt@canonical.com \
--to=heinrich.schuchardt@canonical.com \
--cc=anup.patel@wdc.com \
--cc=atish.patra@wdc.com \
--cc=bmeng.cn@gmail.com \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=guoren@linux.alibaba.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=opensbi@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=samuel@sholland.org \
--cc=tglx@linutronix.de \
--cc=wxjstz@126.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).