From: Jessica Clarke <jrtc27@jrtc27.com>
To: Anup Patel <anup@brainfault.org>
Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Guo Ren <guoren@linux.alibaba.com>, Bin Meng <bmeng.cn@gmail.com>,
Xiang W <wxjstz@126.com>, Samuel Holland <samuel@sholland.org>,
Atish Patra <atish.patra@wdc.com>,
Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Anup Patel <anup.patel@wdc.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, DTML <devicetree@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
OpenSBI <opensbi@lists.infradead.org>
Subject: Re: [PATCH 1/1] dt-bindings: T-HEAD CLINT
Date: Wed, 20 Oct 2021 12:32:40 +0100 [thread overview]
Message-ID: <D1622375-A6BE-4B45-AD99-E4476D603E96@jrtc27.com> (raw)
In-Reply-To: <CAAhSdy22y3gWM0Y9x7m84CdmtHKo7VsDC4+ZDY7+mhkJ9HcYyA@mail.gmail.com>
On 20 Oct 2021, at 12:27, Anup Patel <anup@brainfault.org> wrote:
>
> On Wed, Oct 20, 2021 at 3:06 PM Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com> wrote:
>>
>> The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does
>> not support 64bit mmio access to the MTIMER device.
>>
>> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the
>> restriction and the "sifive,cling0" compatible string. An OpenSBI
>> patch suggested to use "reg-io-width = <4>;" as the reg-io-width property
>> is generally used in the devicetree schema for such a condition.
>>
>> As the design is not SiFive based it is preferable to apply a compatible
>> string identifying T-HEAD instead.
>>
>> Add a new yaml file describing the T-HEAD CLINT.
>>
>> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
>> ---
>> @Palmer, @Anup
>> I copied you as maintainers from sifive,clint.yaml. Please, indicate if
>> this should be changed.
>>
>> For the prior discussion see:
>> https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@canonical.com/
>> https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@canonical.com/
>>
>> A release candidate of the ACLINT specification is available at
>> https://github.com/riscv/riscv-aclint/releases
>
> T-HEAD supporting only 32bit accesses to MTIME and MTIMECMP
> registers are totally allowed. The RISC-V privileged specification does
> not enforce RV64 platforms to support 64bit accesses to MTIME and
> MTIMECMP registers
It does. See [1].
Jess
[1] https://github.com/riscv/riscv-isa-manual/commit/50694a2c0d5393690a9e0c8d309cf064f6c8c0e4
next prev parent reply other threads:[~2021-10-20 11:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-20 9:36 [PATCH 1/1] dt-bindings: T-HEAD CLINT Heinrich Schuchardt
2021-10-20 11:27 ` Anup Patel
2021-10-20 11:32 ` Jessica Clarke [this message]
2021-10-20 11:42 ` Heinrich Schuchardt
2021-10-20 14:07 ` Anup Patel
2021-10-20 13:50 ` Rob Herring
2021-10-22 21:22 ` Rob Herring
2021-10-23 0:03 ` Heinrich Schuchardt
2021-10-24 5:04 ` Guo Ren
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