From: wefu@redhat.com
To: anup.patel@wdc.com, atish.patra@wdc.com,
palmerdabbelt@google.com, guoren@kernel.org,
christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu,
hch@lst.de, liush@allwinnertech.com, wefu@redhat.com,
lazyparser@gmail.com, drew@beagleboard.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
heinrich.schuchardt@canonical.com, gordan.markus@canonical.com,
guoren@linux.alibaba.com, arnd@arndb.de, wens@csie.org,
maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com,
andrea.mondelli@huawei.com, behrensj@mit.edu,
xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr,
allen.baum@esperantotech.com, jscheid@ventanamicro.com,
rtrauben@gmail.com
Subject: [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports
Date: Mon, 25 Oct 2021 12:06:05 +0800 [thread overview]
Message-ID: <20211025040607.92786-1-wefu@redhat.com> (raw)
From: Fu Wei <wefu@redhat.com>
This patch follows the RISC-V standard Svpbmt extension in
privilege spec to solve the non-coherent SOC DMA synchronization
issues.
The svpbmt PTE format:
| 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
N MT RSW D A G U X W R V
^
Of the Reserved bits [63:54] in a leaf PTE, the bits [62:61] are used as
the MT (aka MemType) field. This field specifies one of three memory types
as shown in the following table:
MemType RISC-V Description
---------- ------------------------------------------------
00 - PMA Normal Cacheable, No change to implied PMA memory type
01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
11 - Rsvd Reserved for future standard use
The standard protection_map[] needn't be modified because the "PMA"
type keeps the highest bits zero.
And the whole modification is limited in the arch/riscv/* and using
a global variable(__riscv_svpbmt) as _PAGE_DMA_MASK/IO/NC for
pgprot_noncached (&writecombine) in pgtable.h.
We also add _PAGE_CHG_MASK to filter PFN than before.
Enable it in devicetree - (Add "mmu-supports-svpbmt" in cpu node)
- mmu-supports-svpbmt
Wei Fu (2):
dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt
riscv: add RISC-V Svpbmt extension supports
.../devicetree/bindings/riscv/cpus.yaml | 5 +++
arch/riscv/include/asm/fixmap.h | 2 +-
arch/riscv/include/asm/pgtable-64.h | 8 ++--
arch/riscv/include/asm/pgtable-bits.h | 41 ++++++++++++++++++-
arch/riscv/include/asm/pgtable.h | 39 ++++++++++++++----
arch/riscv/kernel/cpufeature.c | 32 +++++++++++++++
arch/riscv/mm/init.c | 5 +++
7 files changed, 117 insertions(+), 15 deletions(-)
--
2.25.4
next reply other threads:[~2021-10-25 4:06 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 4:06 wefu [this message]
2021-10-25 4:06 ` [RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt wefu
2021-10-25 4:17 ` Anup Patel
2021-10-25 6:00 ` Guo Ren
2021-10-25 6:08 ` Anup Patel
2021-10-25 13:21 ` Philipp Tomsich
2021-10-25 6:09 ` Guo Ren
2021-10-25 4:06 ` [RESEND PATCH V3 2/2] riscv: add RISC-V Svpbmt extension supports wefu
2021-10-25 6:55 ` Christoph Hellwig
2021-10-25 10:55 ` Wei Fu
2021-11-02 6:07 ` Christoph Hellwig
2021-11-07 7:23 ` Wei Fu
2021-10-25 14:49 ` Wei Fu
2021-11-02 6:04 ` Christoph Hellwig
2021-11-07 6:54 ` Wei Fu
2021-10-27 0:12 ` [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports Palmer Dabbelt
2021-10-27 7:54 ` Heinrich Schuchardt
2021-11-02 2:07 ` Guo Ren
2021-11-02 5:58 ` Christoph Hellwig
2021-11-02 8:51 ` Guo Ren
2021-11-07 7:12 ` Wei Fu
2021-11-08 7:52 ` Christoph Hellwig
2021-11-26 16:23 ` Wei Fu
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