* [PATCH 0/3] arm64: dts: r9a07g044: Add SCI{F} nodes to SoC DTSI
@ 2021-11-03 19:55 Lad Prabhakar
2021-11-03 19:55 ` [PATCH 1/3] arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes Lad Prabhakar
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Lad Prabhakar @ 2021-11-03 19:55 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc,
devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Hi All,
This patch series adds SCI{F} nodes to SoC dtsi and enables,
SCIF2 on SMARC EVK.
Note: patch 2/3 is dependent on series [1].
[1] https://patchwork.kernel.org/project/linux-renesas-soc/
cover/20211103173127.13701-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
Lad Prabhakar (3):
arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes
arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes
arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 102 +++++++++++++++++++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 28 +++++
2 files changed, 130 insertions(+)
--
2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/3] arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes
2021-11-03 19:55 [PATCH 0/3] arm64: dts: r9a07g044: Add SCI{F} nodes to SoC DTSI Lad Prabhakar
@ 2021-11-03 19:55 ` Lad Prabhakar
2021-11-08 16:45 ` Geert Uytterhoeven
2021-11-03 19:55 ` [PATCH 2/3] arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes Lad Prabhakar
2021-11-03 19:56 ` [PATCH 3/3] arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board Lad Prabhakar
2 siblings, 1 reply; 8+ messages in thread
From: Lad Prabhakar @ 2021-11-03 19:55 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc,
devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add SCIF[1-4] nodes to r9a07g044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 72 ++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 485ef5f0fea1..09bfdedfac2a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -194,6 +194,78 @@
status = "disabled";
};
+ scif1: serial@1004bc00 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004bc00 0 0x400>;
+ interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif2: serial@1004c000 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004c000 0 0x400>;
+ interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif3: serial@1004c400 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004c400 0 0x400>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif4: serial@1004c800 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004c800 0 0x400>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
canfd: can@10050000 {
compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
reg = <0 0x10050000 0 0x8000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes
2021-11-03 19:55 [PATCH 0/3] arm64: dts: r9a07g044: Add SCI{F} nodes to SoC DTSI Lad Prabhakar
2021-11-03 19:55 ` [PATCH 1/3] arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes Lad Prabhakar
@ 2021-11-03 19:55 ` Lad Prabhakar
2021-11-08 16:26 ` Geert Uytterhoeven
2021-11-03 19:56 ` [PATCH 3/3] arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board Lad Prabhakar
2 siblings, 1 reply; 8+ messages in thread
From: Lad Prabhakar @ 2021-11-03 19:55 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc,
devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add SCI[0-1] nodes to r9a07g044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 09bfdedfac2a..8f05d532d9be 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -176,6 +176,36 @@
status = "disabled";
};
+ sci0: serial@1004d000 {
+ compatible = "renesas,r9a07g044-sci", "renesas,sci";
+ reg = <0 0x1004d000 0 0x400>;
+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCI0_RST>;
+ status = "disabled";
+ };
+
+ sci1: serial@1004d400 {
+ compatible = "renesas,r9a07g044-sci", "renesas,sci";
+ reg = <0 0x1004d400 0 0x400>;
+ interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_SCI1_RST>;
+ status = "disabled";
+ };
+
scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board
2021-11-03 19:55 [PATCH 0/3] arm64: dts: r9a07g044: Add SCI{F} nodes to SoC DTSI Lad Prabhakar
2021-11-03 19:55 ` [PATCH 1/3] arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes Lad Prabhakar
2021-11-03 19:55 ` [PATCH 2/3] arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes Lad Prabhakar
@ 2021-11-03 19:56 ` Lad Prabhakar
2021-11-08 18:00 ` Geert Uytterhoeven
2 siblings, 1 reply; 8+ messages in thread
From: Lad Prabhakar @ 2021-11-03 19:56 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc,
devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
SCIF2 interface is available on PMOD1 connector (CN7) on carrier board,
This patch adds pinmux and scif2 node to carrier board dtsi file.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 28 ++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 2863e487a640..4c32f068a1f0 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -21,9 +21,13 @@
*
*/
+/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
/ {
aliases {
serial0 = &scif0;
+ serial1 = &scif2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c3 = &i2c3;
@@ -208,6 +212,13 @@
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
+ scif2_pins: scif2 {
+ pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
+ <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
+ <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
+ };
+
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
@@ -277,6 +288,23 @@
status = "okay";
};
+/*
+ * To enable SCIF2 (SER0) on PMOD1 (CN7)
+ * SW1 should be at position 2->3 so that SER0_CTS# line is activated
+ * SW2 should be at position 2->3 so that SER0_TX line is activated
+ * SW3 should be at position 2->3 so that SER0_RX line is activated
+ * SW4 should be at position 2->3 so that SER0_RTS# line is activated
+ */
+#if PMOD1_SER0
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+#endif
+
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes
2021-11-03 19:55 ` [PATCH 2/3] arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes Lad Prabhakar
@ 2021-11-08 16:26 ` Geert Uytterhoeven
2021-11-09 0:22 ` Lad, Prabhakar
0 siblings, 1 reply; 8+ messages in thread
From: Geert Uytterhoeven @ 2021-11-08 16:26 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
On Wed, Nov 3, 2021 at 8:56 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add SCI[0-1] nodes to r9a07g044 (RZ/G2L) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -176,6 +176,36 @@
> status = "disabled";
> };
>
> + sci0: serial@1004d000 {
Please keep sort order (by unit address, but grouped by type).
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes
2021-11-03 19:55 ` [PATCH 1/3] arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes Lad Prabhakar
@ 2021-11-08 16:45 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2021-11-08 16:45 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
On Wed, Nov 3, 2021 at 8:56 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add SCIF[1-4] nodes to r9a07g044 (RZ/G2L) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board
2021-11-03 19:56 ` [PATCH 3/3] arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board Lad Prabhakar
@ 2021-11-08 18:00 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2021-11-08 18:00 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Magnus Damm, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Prabhakar, Biju Das
On Wed, Nov 3, 2021 at 8:56 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> SCIF2 interface is available on PMOD1 connector (CN7) on carrier board,
> This patch adds pinmux and scif2 node to carrier board dtsi file.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.17.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes
2021-11-08 16:26 ` Geert Uytterhoeven
@ 2021-11-09 0:22 ` Lad, Prabhakar
0 siblings, 0 replies; 8+ messages in thread
From: Lad, Prabhakar @ 2021-11-09 0:22 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Biju Das
Hi Geert,
Thank you for the review.
On Mon, Nov 8, 2021 at 4:26 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> On Wed, Nov 3, 2021 at 8:56 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Add SCI[0-1] nodes to r9a07g044 (RZ/G2L) SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > @@ -176,6 +176,36 @@
> > status = "disabled";
> > };
> >
> > + sci0: serial@1004d000 {
>
> Please keep sort order (by unit address, but grouped by type).
>
Oops missed that, will fix it in v2.
Chers,
Prabhakar
> With the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-11-09 0:23 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2021-11-03 19:55 ` [PATCH 1/3] arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodes Lad Prabhakar
2021-11-08 16:45 ` Geert Uytterhoeven
2021-11-03 19:55 ` [PATCH 2/3] arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes Lad Prabhakar
2021-11-08 16:26 ` Geert Uytterhoeven
2021-11-09 0:22 ` Lad, Prabhakar
2021-11-03 19:56 ` [PATCH 3/3] arm64: dts: renesas: rzg2l-smarc: Enable SCIF2 on carrier board Lad Prabhakar
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