From: Peter Zijlstra <peterz@infradead.org>
To: x86@kernel.org
Cc: linux-kernel@vger.kernel.org, peterz@infradead.org,
jpoimboe@redhat.com, mark.rutland@arm.com, dvyukov@google.com,
seanjc@google.com, pbonzini@redhat.com, mbenes@suse.cz
Subject: [RFC][PATCH 17/22] x86,sgx: Remove .fixup usage
Date: Thu, 04 Nov 2021 17:47:46 +0100 [thread overview]
Message-ID: <20211104165525.527997216@infradead.org> (raw)
In-Reply-To: 20211104164729.226550532@infradead.org
Create EX_TYPE_FAULT_SGX which does as EX_TYPE_FAULT does, except adds
this extra bit that SGX really fanies having.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
arch/x86/include/asm/extable_fixup_types.h | 2 +
arch/x86/include/asm/sgx.h | 18 ++++++++++++++
arch/x86/kernel/cpu/sgx/encls.h | 36 ++++-------------------------
arch/x86/mm/extable.c | 10 ++++++++
4 files changed, 35 insertions(+), 31 deletions(-)
--- a/arch/x86/include/asm/extable_fixup_types.h
+++ b/arch/x86/include/asm/extable_fixup_types.h
@@ -39,4 +39,6 @@
#define EX_TYPE_ZERO_REG (EX_TYPE_IMM_REG | EX_TYPE_IMM(0))
#define EX_TYPE_ONE_REG (EX_TYPE_IMM_REG | EX_TYPE_IMM(1))
+#define EX_TYPE_FAULT_SGX 18
+
#endif
--- a/arch/x86/include/asm/sgx.h
+++ b/arch/x86/include/asm/sgx.h
@@ -46,6 +46,24 @@ enum sgx_encls_function {
};
/**
+ * SGX_ENCLS_FAULT_FLAG - flag signifying an ENCLS return code is a trapnr
+ *
+ * ENCLS has its own (positive value) error codes and also generates
+ * ENCLS specific #GP and #PF faults. And the ENCLS values get munged
+ * with system error codes as everything percolates back up the stack.
+ * Unfortunately (for us), we need to precisely identify each unique
+ * error code, e.g. the action taken if EWB fails varies based on the
+ * type of fault and on the exact SGX error code, i.e. we can't simply
+ * convert all faults to -EFAULT.
+ *
+ * To make all three error types coexist, we set bit 30 to identify an
+ * ENCLS fault. Bit 31 (technically bits N:31) is used to differentiate
+ * between positive (faults and SGX error codes) and negative (system
+ * error codes) values.
+ */
+#define SGX_ENCLS_FAULT_FLAG 0x40000000
+
+/**
* enum sgx_return_code - The return code type for ENCLS, ENCLU and ENCLV
* %SGX_NOT_TRACKED: Previous ETRACK's shootdown sequence has not
* been completed yet.
--- a/arch/x86/kernel/cpu/sgx/encls.h
+++ b/arch/x86/kernel/cpu/sgx/encls.h
@@ -11,26 +11,8 @@
#include <asm/traps.h>
#include "sgx.h"
-/**
- * ENCLS_FAULT_FLAG - flag signifying an ENCLS return code is a trapnr
- *
- * ENCLS has its own (positive value) error codes and also generates
- * ENCLS specific #GP and #PF faults. And the ENCLS values get munged
- * with system error codes as everything percolates back up the stack.
- * Unfortunately (for us), we need to precisely identify each unique
- * error code, e.g. the action taken if EWB fails varies based on the
- * type of fault and on the exact SGX error code, i.e. we can't simply
- * convert all faults to -EFAULT.
- *
- * To make all three error types coexist, we set bit 30 to identify an
- * ENCLS fault. Bit 31 (technically bits N:31) is used to differentiate
- * between positive (faults and SGX error codes) and negative (system
- * error codes) values.
- */
-#define ENCLS_FAULT_FLAG 0x40000000
-
/* Retrieve the encoded trapnr from the specified return code. */
-#define ENCLS_TRAPNR(r) ((r) & ~ENCLS_FAULT_FLAG)
+#define ENCLS_TRAPNR(r) ((r) & ~SGX_ENCLS_FAULT_FLAG)
/* Issue a WARN() about an ENCLS function. */
#define ENCLS_WARN(r, name) { \
@@ -50,7 +32,7 @@
*/
static inline bool encls_faulted(int ret)
{
- return ret & ENCLS_FAULT_FLAG;
+ return ret & SGX_ENCLS_FAULT_FLAG;
}
/**
@@ -88,11 +70,7 @@ static inline bool encls_failed(int ret)
asm volatile( \
"1: .byte 0x0f, 0x01, 0xcf;\n\t" \
"2:\n" \
- ".section .fixup,\"ax\"\n" \
- "3: orl $"__stringify(ENCLS_FAULT_FLAG)",%%eax\n" \
- " jmp 2b\n" \
- ".previous\n" \
- _ASM_EXTABLE_FAULT(1b, 3b) \
+ _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_FAULT_SGX) \
: "=a"(ret) \
: "a"(rax), inputs \
: "memory", "cc"); \
@@ -127,7 +105,7 @@ static inline bool encls_failed(int ret)
*
* Return:
* 0 on success,
- * trapnr with ENCLS_FAULT_FLAG set on fault
+ * trapnr with SGX_ENCLS_FAULT_FLAG set on fault
*/
#define __encls_N(rax, rbx_out, inputs...) \
({ \
@@ -136,11 +114,7 @@ static inline bool encls_failed(int ret)
"1: .byte 0x0f, 0x01, 0xcf;\n\t" \
" xor %%eax,%%eax;\n" \
"2:\n" \
- ".section .fixup,\"ax\"\n" \
- "3: orl $"__stringify(ENCLS_FAULT_FLAG)",%%eax\n" \
- " jmp 2b\n" \
- ".previous\n" \
- _ASM_EXTABLE_FAULT(1b, 3b) \
+ _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_FAULT_SGX) \
: "=a"(ret), "=b"(rbx_out) \
: "a"(rax), inputs \
: "memory"); \
--- a/arch/x86/mm/extable.c
+++ b/arch/x86/mm/extable.c
@@ -9,6 +9,7 @@
#include <asm/sev.h>
#include <asm/traps.h>
#include <asm/kdebug.h>
+#include <asm/sgx.h>
static inline unsigned long *pt_regs_nr(struct pt_regs *regs, int nr)
{
@@ -146,6 +147,13 @@ static bool ex_handler_imm_reg(const str
return ex_handler_default(fixup, regs);
}
+static bool ex_handler_sgx(const struct exception_table_entry *fixup,
+ struct pt_regs *regs, int trapnr)
+{
+ regs->ax = trapnr | SGX_ENCLS_FAULT_FLAG;
+ return ex_handler_default(fixup, regs);
+}
+
#define EX_TYPE_MASK 0x000000FF
#define EX_REG_MASK 0x00000F00
#define EX_FLAG_MASK 0x0000F000
@@ -221,6 +229,8 @@ int fixup_exception(struct pt_regs *regs
return ex_handler_pop_seg(e, regs);
case EX_TYPE_IMM_REG:
return ex_handler_imm_reg(e, regs, reg, imm);
+ case EX_TYPE_FAULT_SGX:
+ return ex_handler_sgx(e, regs, trapnr);
}
BUG();
}
next prev parent reply other threads:[~2021-11-04 17:01 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-04 16:47 [RFC][PATCH 00/22] x86: Remove anonymous out-of-line fixups Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 01/22] bitfield.h: Fix "type of reg too small for mask" test Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 02/22] x86,mmx_32: Remove .fixup usage Peter Zijlstra
2021-11-04 18:00 ` Borislav Petkov
2021-11-05 11:20 ` David Laight
2021-11-04 20:22 ` Josh Poimboeuf
2021-11-05 8:05 ` Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 03/22] x86,copy_user_64: " Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 04/22] x86,copy_mc_64: " Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 05/22] x86,entry_64: " Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 06/22] x86,entry_32: " Peter Zijlstra
2021-11-04 20:39 ` Josh Poimboeuf
2021-11-05 7:43 ` Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 07/22] x86,extable: Extend extable functionality Peter Zijlstra
2021-11-04 21:49 ` Josh Poimboeuf
2021-11-05 7:54 ` Peter Zijlstra
2021-11-05 10:16 ` Mark Rutland
2021-11-05 17:32 ` Sean Christopherson
2021-11-05 18:45 ` Peter Zijlstra
2021-11-05 19:17 ` Sean Christopherson
2021-11-05 19:32 ` Peter Zijlstra
2021-11-05 19:47 ` Sean Christopherson
2021-11-05 20:15 ` Peter Zijlstra
2021-11-05 20:26 ` Peter Zijlstra
2021-11-05 22:30 ` Sean Christopherson
2021-11-04 16:47 ` [RFC][PATCH 08/22] x86,msr: Remove .fixup usage Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 09/22] x86,futex: " Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 10/22] x86,uaccess: " Peter Zijlstra
2021-11-04 22:28 ` Josh Poimboeuf
2021-11-04 16:47 ` [RFC][PATCH 11/22] x86,xen: " Peter Zijlstra
2021-11-04 22:31 ` Josh Poimboeuf
2021-11-05 7:56 ` Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 12/22] x86,fpu: " Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 13/22] x86,segment: " Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 14/22] x86,ftrace: " Peter Zijlstra
2021-11-04 22:35 ` Josh Poimboeuf
2021-11-05 7:57 ` Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 15/22] x86,vmx: " Peter Zijlstra
2021-11-04 18:50 ` Paolo Bonzini
2021-11-05 18:17 ` Sean Christopherson
2021-11-05 18:52 ` Peter Zijlstra
2021-11-05 20:58 ` Peter Zijlstra
2021-11-05 22:29 ` Sean Christopherson
2021-11-06 7:05 ` Paolo Bonzini
2021-11-06 8:36 ` Peter Zijlstra
2021-11-07 19:13 ` Paolo Bonzini
2021-11-06 8:28 ` Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 16/22] x86,checksum_32: " Peter Zijlstra
2021-11-04 16:47 ` Peter Zijlstra [this message]
2021-11-04 16:47 ` [RFC][PATCH 18/22] x86,kvm: " Peter Zijlstra
2021-11-04 18:50 ` Paolo Bonzini
2021-11-05 7:58 ` Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 19/22] x86,usercopy_32: Simplify Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 20/22] x86,usercopy: Remove .fixup usage Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 21/22] x86,word-at-a-time: " Peter Zijlstra
2021-11-04 23:33 ` Josh Poimboeuf
2021-11-05 8:04 ` Peter Zijlstra
2021-11-04 16:47 ` [RFC][PATCH 22/22] x86: Remove .fixup section Peter Zijlstra
2021-11-04 23:00 ` Josh Poimboeuf
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211104165525.527997216@infradead.org \
--to=peterz@infradead.org \
--cc=dvyukov@google.com \
--cc=jpoimboe@redhat.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mbenes@suse.cz \
--cc=pbonzini@redhat.com \
--cc=seanjc@google.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).