From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Jinlong <quic_jinlmao@quicinc.com>
Cc: Tao Zhang <quic_taozha@quicinc.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Trilok Soni <quic_tsoni@quicinc.com>
Subject: Re: [PATCH 04/10] Coresight: Enable BC and GPR for TPDM driver
Date: Thu, 4 Nov 2021 11:02:24 -0600 [thread overview]
Message-ID: <20211104170224.GC491267@p14s> (raw)
In-Reply-To: <20211104111323.GA14135@jinlmao-gv.ap.qualcomm.com>
[...]
> > > +
> > > +static ssize_t reset_store(struct device *dev,
> > > + struct device_attribute *attr,
> > > + const char *buf,
> > > + size_t size)
> > > +{
> > > + int ret = 0;
> > > + unsigned long val;
> > > + struct mcmb_dataset *mcmb_temp = NULL;
> > > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > > +
> > > + ret = kstrtoul(buf, 10, &val);
> >
> > The coresight subsystem normally uses the hexadecimal base.
> >
>
> We will address you comments.
>
> > > + if (ret)
> > > + return ret;
> >
> > Shouldn't this be "if (!ret)" ?
> >
>
> When ret is not 0, it need to return.
I would expect something like this:
$ echo 1 > /sys/path/to/tpdm/device/reset
and not
$ echo 0 > /sys/path/to/tpdm/device/reset
The latter is what the code does.
Thanks,
Mathieu
>
> > > +
> > > + mutex_lock(&drvdata->lock);
> > > + /* Reset all datasets to ZERO */
> > > + if (drvdata->gpr != NULL)
> > > + memset(drvdata->gpr, 0, sizeof(struct gpr_dataset));
> > > +
> > > + if (drvdata->bc != NULL)
> > > + memset(drvdata->bc, 0, sizeof(struct bc_dataset));
> > > +
> > > + if (drvdata->tc != NULL)
> > > + memset(drvdata->tc, 0, sizeof(struct tc_dataset));
> > > +
> > > + if (drvdata->dsb != NULL)
> > > + memset(drvdata->dsb, 0, sizeof(struct dsb_dataset));
> > > +
> > > + if (drvdata->cmb != NULL) {
> > > + if (drvdata->cmb->mcmb != NULL) {
> > > + mcmb_temp = drvdata->cmb->mcmb;
> > > + memset(drvdata->cmb->mcmb, 0,
> > > + sizeof(struct mcmb_dataset));
> > > + }
> > > +
> > > + memset(drvdata->cmb, 0, sizeof(struct cmb_dataset));
> > > + drvdata->cmb->mcmb = mcmb_temp;
> > > + }
> > > + /* Init the default data */
> > > + tpdm_init_default_data(drvdata);
> > > +
> > > + mutex_unlock(&drvdata->lock);
> > > +
> > > + /* Disable tpdm if enabled */
> > > + if (drvdata->enable)
> > > + coresight_disable(drvdata->csdev);
> >
> > Why is this done out of the lock?
> >
>
> When call coresight_disable, tpdm_disable will be called. There is lock in tpdm_disable.
> If add it into the lock, there will be dead lock.
>
> > > +
> > > + return size;
> > > +}
> > > +static DEVICE_ATTR_WO(reset);
> > > +
> > > +static ssize_t integration_test_store(struct device *dev,
> > > + struct device_attribute *attr,
> > > + const char *buf,
> > > + size_t size)
> > > +{
> > > + int i, ret = 0;
> > > + unsigned long val;
> > > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > > +
> > > + ret = kstrtoul(buf, 10, &val);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + if (val != 1 && val != 2)
> > > + return -EINVAL;
> > > +
> > > + if (!drvdata->enable)
> > > + return -EINVAL;
> > > +
> > > + if (val == 1)
> > > + val = ATBCNTRL_VAL_64;
> > > + else
> > > + val = ATBCNTRL_VAL_32;
> > > + TPDM_UNLOCK(drvdata);
> > > + tpdm_writel(drvdata, 0x1, TPDM_ITCNTRL);
> > > +
> > > + for (i = 1; i < 5; i++)
> > > + tpdm_writel(drvdata, val, TPDM_ITATBCNTRL);
> > > +
> > > + tpdm_writel(drvdata, 0, TPDM_ITCNTRL);
> > > + TPDM_LOCK(drvdata);
> > > + return size;
> > > +}
> > > +static DEVICE_ATTR_WO(integration_test);
> >
> > Integration test interface should be conditional to a compile time option. Have
> > a look at what was done for CTIs.
> >
>
> We will check and update.
>
> > > +
> > > +static ssize_t gp_regs_show(struct device *dev,
> > > + struct device_attribute *attr,
> > > + char *buf)
> > > +{
> > > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > > + ssize_t size = 0;
> > > + int i = 0;
> > > +
> > > + if (!test_bit(TPDM_DS_GPR, drvdata->datasets))
> > > + return -EPERM;
> >
> > return -EINVAL;
> >
> > > +
> > > + mutex_lock(&drvdata->lock);
> > > + for (i = 0; i < TPDM_GPR_REGS_MAX; i++) {
> > > + if (!test_bit(i, drvdata->gpr->gpr_dirty))
> > > + continue;
> > > + size += scnprintf(buf + size, PAGE_SIZE - size,
> > > + "Index: 0x%x Value: 0x%x\n", i,
> > > + drvdata->gpr->gp_regs[i]);
> >
> > This should not be - the sysfs interface requires outputs of a single line.
> >
>
> We will check and update.
>
> > > + }
> > > + mutex_unlock(&drvdata->lock);
> > > + return size;
> > > +}
> > > +
> > > +static ssize_t gp_regs_store(struct device *dev,
> > > + struct device_attribute *attr,
> > > + const char *buf,
> > > + size_t size)
> > > +{
> > > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > > + unsigned long index, val;
> > > +
> > > + if (sscanf(buf, "%lx %lx", &index, &val) != 2)
> > > + return -EINVAL;
> > > + if (!test_bit(TPDM_DS_GPR, drvdata->datasets) ||
> > > + index >= TPDM_GPR_REGS_MAX)
> > > + return -EPERM;
> > > +
> > > + mutex_lock(&drvdata->lock);
> > > + drvdata->gpr->gp_regs[index] = val;
> > > + __set_bit(index, drvdata->gpr->gpr_dirty);
> > > + mutex_unlock(&drvdata->lock);
> > > + return size;
> > > +}
> > > +static DEVICE_ATTR_RW(gp_regs);
> > > +
> > > +static struct attribute *tpdm_attrs[] = {
> > > + &dev_attr_available_datasets.attr,
> > > + &dev_attr_enable_datasets.attr,
> > > + &dev_attr_reset.attr,
> > > + &dev_attr_integration_test.attr,
> > > + &dev_attr_gp_regs.attr,
> > > + NULL,
> > > +};
> >
> > All new sysfs interface need to be documented. See here:
> >
> > Documentation/ABI/testing/sysfs-bus-coresight-devices-xyz
> >
> > More comments to come...
> >
>
> We will add the comments.
>
> > Thanks,
> > Mathieu
> >
> > > +
> > > +static struct attribute_group tpdm_attr_grp = {
> > > + .attrs = tpdm_attrs,
> > > +};
> > > +static const struct attribute_group *tpdm_attr_grps[] = {
> > > + &tpdm_attr_grp,
> > > + NULL,
> > > +};
> > > +
> > > static int tpdm_datasets_alloc(struct tpdm_drvdata *drvdata)
> > > {
> > > if (test_bit(TPDM_DS_GPR, drvdata->datasets)) {
> > > @@ -513,6 +846,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
> > > desc.ops = &tpdm_cs_ops;
> > > desc.pdata = adev->dev.platform_data;
> > > desc.dev = &adev->dev;
> > > + desc.groups = tpdm_attr_grps;
> > > drvdata->csdev = coresight_register(&desc);
> > > if (IS_ERR(drvdata->csdev))
> > > return PTR_ERR(drvdata->csdev);
> > > --
> > > 2.17.1
> > >
next prev parent reply other threads:[~2021-11-04 17:02 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-21 7:38 [PATCH 00/10] Add support for TPDM and TPDA Tao Zhang
2021-10-21 7:38 ` [PATCH 01/10] coresight: add support to enable more coresight paths Tao Zhang
2021-10-28 18:06 ` Mathieu Poirier
2021-11-22 15:12 ` Jinlong Mao
2021-11-22 16:51 ` Mathieu Poirier
2021-10-21 7:38 ` [PATCH 02/10] coresight: funnel: add support for multiple output ports Tao Zhang
2021-10-29 17:48 ` Mathieu Poirier
2021-10-21 7:38 ` [PATCH 03/10] Coresight: Add driver to support Coresight device TPDM Tao Zhang
2021-11-02 17:59 ` Mathieu Poirier
2021-11-04 8:56 ` Jinlong
2021-11-04 16:55 ` Mathieu Poirier
2021-11-05 8:15 ` Jinlong
2021-11-04 9:37 ` Suzuki K Poulose
2021-11-05 8:12 ` Jinlong
2021-10-21 7:38 ` [PATCH 04/10] Coresight: Enable BC and GPR for TPDM driver Tao Zhang
2021-11-03 19:43 ` Mathieu Poirier
2021-11-04 11:13 ` Jinlong
2021-11-04 17:02 ` Mathieu Poirier [this message]
2021-11-05 8:17 ` Jinlong
2021-11-05 15:14 ` Mathieu Poirier
2021-10-21 7:38 ` [PATCH 05/10] Coresight: Add interface for TPDM BC subunit Tao Zhang
2021-11-04 18:01 ` Mathieu Poirier
2021-11-05 8:26 ` Jinlong
2021-11-12 8:42 ` Jinlong
2021-11-12 9:10 ` Jinlong
2021-11-12 16:37 ` Mathieu Poirier
2021-10-21 7:38 ` [PATCH 06/10] Coresight: Enable and add interface for TPDM TC subunit Tao Zhang
2021-10-21 7:38 ` [PATCH 07/10] Coresight: Enable DSB subunit for TPDM Tao Zhang
2021-10-21 7:38 ` [PATCH 08/10] Coresight: Enable CMB " Tao Zhang
2021-10-21 7:38 ` [PATCH 09/10] coresight: Add driver to support Coresight device TPDA Tao Zhang
2021-10-21 7:38 ` [PATCH 10/10] ARM: dts: msm: Add TPDA and TPDM support to DTS for RB5 Tao Zhang
2021-11-02 18:02 ` Mathieu Poirier
2021-11-03 8:14 ` Tao Zhang
2021-11-04 9:45 ` Suzuki K Poulose
2021-11-05 8:07 ` Jinlong
2021-10-28 17:16 ` [PATCH 00/10] Add support for TPDM and TPDA Mathieu Poirier
2021-10-29 15:11 ` Tao Zhang
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