From: luizluca@gmail.com
To: netdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org,
alsi@bang-olufsen.dk,
Luiz Angelo Daros de Luca <luizluca@gmail.com>
Subject: [PATCH v2] net: dsa: realtek-smi: fix indirect reg access for ports>3
Date: Fri, 26 Nov 2021 05:12:52 -0300 [thread overview]
Message-ID: <20211126081252.32254-1-luizluca@gmail.com> (raw)
In-Reply-To: <20211126063645.19094-1-luizluca@gmail.com>
From: Luiz Angelo Daros de Luca <luizluca@gmail.com>
This switch family can have up to 8 ports {0..7}. However,
INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK was using 2 bits instead of 3,
dropping the most significant bit during indirect register reads and
writes. Reading or writing ports 4, 5, 6, and 7 registers was actually
manipulating, respectively, ports 0, 1, 2, and 3 registers.
rtl8365mb_phy_{read,write} will now returns -EINVAL if phy is greater
than 7.
v2:
- fix affected ports in commit message
Fixes: 4af2950c50c8 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC")
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
drivers/net/dsa/rtl8365mb.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/rtl8365mb.c b/drivers/net/dsa/rtl8365mb.c
index baaae97283c5..f4414ac74b61 100644
--- a/drivers/net/dsa/rtl8365mb.c
+++ b/drivers/net/dsa/rtl8365mb.c
@@ -107,6 +107,7 @@
#define RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC 2112
/* Family-specific data and limits */
+#define RTL8365MB_PHYADDRMAX 7
#define RTL8365MB_NUM_PHYREGS 32
#define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)
#define RTL8365MB_MAX_NUM_PORTS (RTL8365MB_CPU_PORT_NUM_8365MB_VC + 1)
@@ -176,7 +177,7 @@
#define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01
#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02
#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0)
-#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(6, 5)
+#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5)
#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8)
#define RTL8365MB_PHY_BASE 0x2000
#define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03
@@ -679,6 +680,8 @@ static int rtl8365mb_phy_read(struct realtek_smi *smi, int phy, int regnum)
u16 val;
int ret;
+ if (phy > RTL8365MB_PHYADDRMAX)
+ return -EINVAL;
if (regnum > RTL8365MB_PHYREGMAX)
return -EINVAL;
@@ -704,6 +707,8 @@ static int rtl8365mb_phy_write(struct realtek_smi *smi, int phy, int regnum,
u32 ocp_addr;
int ret;
+ if (phy > RTL8365MB_PHYADDRMAX)
+ return -EINVAL;
if (regnum > RTL8365MB_PHYREGMAX)
return -EINVAL;
--
2.33.1
next prev parent reply other threads:[~2021-11-26 8:15 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 6:36 [PATCH] net: dsa: realtek-smi: fix indirect reg access for ports>4 luizluca
2021-11-26 8:12 ` luizluca [this message]
2021-11-26 8:21 ` [PATCH v2] net: dsa: realtek-smi: fix indirect reg access for ports>3 Greg KH
2021-11-26 9:34 ` Alvin Šipraga
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