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From: Huang Rui <ray.huang@amd.com>
To: "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	"Borislav Petkov" <bp@suse.de>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@kernel.org>,
	Giovanni Gherdovich <ggherdovich@suse.cz>,
	<linux-pm@vger.kernel.org>
Cc: Deepak Sharma <deepak.sharma@amd.com>,
	Alex Deucher <alexander.deucher@amd.com>,
	Mario Limonciello <mario.limonciello@amd.com>,
	Steven Noonan <steven@valvesoftware.com>,
	Nathan Fontenot <nathan.fontenot@amd.com>,
	Jinzhou Su <Jinzhou.Su@amd.com>,
	Xiaojian Du <Xiaojian.Du@amd.com>, <linux-kernel@vger.kernel.org>,
	<x86@kernel.org>, Huang Rui <ray.huang@amd.com>
Subject: [PATCH v5 05/22] ACPI: CPPC: add cppc enable register function
Date: Tue, 30 Nov 2021 20:36:24 +0800	[thread overview]
Message-ID: <20211130123641.1449041-6-ray.huang@amd.com> (raw)
In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com>

From: Jinzhou Su <Jinzhou.Su@amd.com>

Add a new function to enable CPPC feature. This function
will write Continuous Performance Control package
EnableRegister field on the processor.

CPPC EnableRegister register described in section 8.4.7.1 of ACPI 6.4:
This element is optional. If supported, contains a resource descriptor
with a single Register() descriptor that describes a register to which
OSPM writes a One to enable CPPC on this processor. Before this register
is set, the processor will be controlled by legacy mechanisms (ACPI
Pstates, firmware, etc.).

This register will be used for AMD processors to enable amd-pstate
function instead of legacy ACPI P-States.

Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/acpi/cppc_acpi.c | 45 ++++++++++++++++++++++++++++++++++++++++
 include/acpi/cppc_acpi.h |  5 +++++
 2 files changed, 50 insertions(+)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index a46f227dc254..003df9fba122 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -1262,6 +1262,51 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
 }
 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
 
+/**
+ * cppc_set_enable - Set to enable CPPC on the processor by writing the
+ * Continuous Performance Control package EnableRegister field.
+ * @cpu: CPU for which to enable CPPC register.
+ * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
+ *
+ * Return: 0 for success, -ERRNO or -EIO otherwise.
+ */
+int cppc_set_enable(int cpu, bool enable)
+{
+	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
+	struct cpc_register_resource *enable_reg;
+	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
+	struct cppc_pcc_data *pcc_ss_data = NULL;
+	int ret = -EINVAL;
+
+	if (!cpc_desc) {
+		pr_debug("No CPC descriptor for CPU:%d\n", cpu);
+		return -EINVAL;
+	}
+
+	enable_reg = &cpc_desc->cpc_regs[ENABLE];
+
+	if (CPC_IN_PCC(enable_reg)) {
+
+		if (pcc_ss_id < 0)
+			return -EIO;
+
+		ret = cpc_write(cpu, enable_reg, enable);
+		if (ret)
+			return ret;
+
+		pcc_ss_data = pcc_data[pcc_ss_id];
+
+		down_write(&pcc_ss_data->pcc_lock);
+		/* after writing CPC, transfer the ownership of PCC to platfrom */
+		ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
+		up_write(&pcc_ss_data->pcc_lock);
+		return ret;
+	}
+
+	return cpc_write(cpu, enable_reg, enable);
+}
+EXPORT_SYMBOL_GPL(cppc_set_enable);
+
 /**
  * cppc_set_perf - Set a CPU's performance controls.
  * @cpu: CPU for which to set performance controls.
diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
index bc159a9b4a73..92b7ea8d8f5e 100644
--- a/include/acpi/cppc_acpi.h
+++ b/include/acpi/cppc_acpi.h
@@ -138,6 +138,7 @@ extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf);
 extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf);
 extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs);
 extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
+extern int cppc_set_enable(int cpu, bool enable);
 extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps);
 extern bool acpi_cpc_valid(void);
 extern int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data);
@@ -162,6 +163,10 @@ static inline int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
 {
 	return -ENOTSUPP;
 }
+static inline int cppc_set_enable(int cpu, bool enable)
+{
+	return -ENOTSUPP;
+}
 static inline int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps)
 {
 	return -ENOTSUPP;
-- 
2.25.1


  parent reply	other threads:[~2021-11-30 12:37 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-30 12:36 [PATCH v5 00/22] cpufreq: introduce a new AMD CPU frequency control mechanism Huang Rui
2021-11-30 12:36 ` [PATCH v5 01/22] x86/cpufeatures: add AMD Collaborative Processor Performance Control feature flag Huang Rui
2021-11-30 12:36 ` [PATCH v5 02/22] x86/msr: add AMD CPPC MSR definitions Huang Rui
2021-12-16 17:23   ` Rafael J. Wysocki
2021-12-17  3:09     ` Huang Rui
2021-11-30 12:36 ` [PATCH v5 03/22] ACPI: CPPC: implement support for SystemIO registers Huang Rui
2021-12-16 17:40   ` Rafael J. Wysocki
2021-12-17  4:30     ` Huang Rui
2021-11-30 12:36 ` [PATCH v5 04/22] ACPI: CPPC: Check present CPUs for determining _CPC is valid Huang Rui
2021-11-30 12:36 ` Huang Rui [this message]
2021-11-30 12:36 ` [PATCH v5 06/22] cpufreq: amd: introduce a new amd pstate driver to support future processors Huang Rui
2021-12-16 17:59   ` Rafael J. Wysocki
2021-12-17  7:34     ` Huang Rui
2021-12-17 14:03       ` Rafael J. Wysocki
2021-11-30 12:36 ` [PATCH v5 07/22] cpufreq: amd: add fast switch function for amd-pstate Huang Rui
2021-11-30 12:36 ` [PATCH v5 08/22] cpufreq: amd: introduce the support for the processors with shared memory solution Huang Rui
2021-12-16 18:04   ` Rafael J. Wysocki
2021-12-17  7:37     ` Huang Rui
2021-11-30 12:36 ` [PATCH v5 09/22] cpufreq: amd: add trace for amd-pstate module Huang Rui
2021-12-16 18:12   ` Rafael J. Wysocki
2021-12-17  7:52     ` Huang Rui
2021-12-17 14:05       ` Rafael J. Wysocki
2021-11-30 12:36 ` [PATCH v5 10/22] cpufreq: amd: add boost mode support for amd-pstate Huang Rui
2021-11-30 12:36 ` [PATCH v5 11/22] cpufreq: amd: add amd-pstate frequencies attributes Huang Rui
2021-11-30 12:36 ` [PATCH v5 12/22] cpufreq: amd: add amd-pstate performance attributes Huang Rui
2021-11-30 12:36 ` [PATCH v5 13/22] cpupower: add AMD P-state capability flag Huang Rui
2021-11-30 12:36 ` [PATCH v5 14/22] cpupower: add the function to check amd-pstate enabled Huang Rui
2021-11-30 12:36 ` [PATCH v5 15/22] cpupower: initial AMD P-state capability Huang Rui
2021-11-30 12:36 ` [PATCH v5 16/22] cpupower: add the function to get the sysfs value from specific table Huang Rui
2021-11-30 12:36 ` [PATCH v5 17/22] cpupower: introduce acpi cppc library Huang Rui
2021-11-30 12:36 ` [PATCH v5 18/22] cpupower: add amd-pstate sysfs definition and access helper Huang Rui
2021-11-30 12:36 ` [PATCH v5 19/22] cpupower: enable boost state support for amd-pstate module Huang Rui
2021-11-30 12:36 ` [PATCH v5 20/22] cpupower: move print_speed function into misc helper Huang Rui
2021-11-30 12:36 ` [PATCH v5 21/22] cpupower: print amd-pstate information on cpupower Huang Rui
2021-11-30 12:36 ` [PATCH v5 22/22] Documentation: amd-pstate: add amd-pstate driver introduction Huang Rui
2021-12-16 18:20 ` [PATCH v5 00/22] cpufreq: introduce a new AMD CPU frequency control mechanism Rafael J. Wysocki

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