* [PATCH] PCI: apple: Fix REFCLK1 enable/poll logic
@ 2021-11-17 14:00 Hector Martin
2021-11-17 17:56 ` Marc Zyngier
2021-12-06 10:45 ` Lorenzo Pieralisi
0 siblings, 2 replies; 5+ messages in thread
From: Hector Martin @ 2021-11-17 14:00 UTC (permalink / raw)
To: Marc Zyngier, Alyssa Rosenzweig
Cc: Lorenzo Pieralisi, Rob Herring, Krzysztof Wilczyński,
Bjorn Helgaas, linux-pci, linux-kernel, Hector Martin
REFCLK1 has req/ack bits just like REFCLK0
Signed-off-by: Hector Martin <marcan@marcan.st>
---
drivers/pci/controller/pcie-apple.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c
index b665d29af77a..420c291a5c68 100644
--- a/drivers/pci/controller/pcie-apple.c
+++ b/drivers/pci/controller/pcie-apple.c
@@ -42,8 +42,9 @@
#define CORE_FABRIC_STAT_MASK 0x001F001F
#define CORE_LANE_CFG(port) (0x84000 + 0x4000 * (port))
#define CORE_LANE_CFG_REFCLK0REQ BIT(0)
-#define CORE_LANE_CFG_REFCLK1 BIT(1)
+#define CORE_LANE_CFG_REFCLK1REQ BIT(1)
#define CORE_LANE_CFG_REFCLK0ACK BIT(2)
+#define CORE_LANE_CFG_REFCLK1ACK BIT(3)
#define CORE_LANE_CFG_REFCLKEN (BIT(9) | BIT(10))
#define CORE_LANE_CTL(port) (0x84004 + 0x4000 * (port))
#define CORE_LANE_CTL_CFGACC BIT(15)
@@ -481,9 +482,9 @@ static int apple_pcie_setup_refclk(struct apple_pcie *pcie,
if (res < 0)
return res;
- rmw_set(CORE_LANE_CFG_REFCLK1, pcie->base + CORE_LANE_CFG(port->idx));
+ rmw_set(CORE_LANE_CFG_REFCLK1REQ, pcie->base + CORE_LANE_CFG(port->idx));
res = readl_relaxed_poll_timeout(pcie->base + CORE_LANE_CFG(port->idx),
- stat, stat & CORE_LANE_CFG_REFCLK1,
+ stat, stat & CORE_LANE_CFG_REFCLK1ACK,
100, 50000);
if (res < 0)
--
2.33.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] PCI: apple: Fix REFCLK1 enable/poll logic
2021-11-17 14:00 [PATCH] PCI: apple: Fix REFCLK1 enable/poll logic Hector Martin
@ 2021-11-17 17:56 ` Marc Zyngier
2021-11-30 16:49 ` Lorenzo Pieralisi
2021-12-06 10:45 ` Lorenzo Pieralisi
1 sibling, 1 reply; 5+ messages in thread
From: Marc Zyngier @ 2021-11-17 17:56 UTC (permalink / raw)
To: Hector Martin
Cc: Alyssa Rosenzweig, Lorenzo Pieralisi, Rob Herring,
Krzysztof Wilczyński, Bjorn Helgaas, linux-pci,
linux-kernel
On Wed, 17 Nov 2021 14:00:44 +0000,
Hector Martin <marcan@marcan.st> wrote:
>
> REFCLK1 has req/ack bits just like REFCLK0
>
> Signed-off-by: Hector Martin <marcan@marcan.st>
> ---
> drivers/pci/controller/pcie-apple.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c
> index b665d29af77a..420c291a5c68 100644
> --- a/drivers/pci/controller/pcie-apple.c
> +++ b/drivers/pci/controller/pcie-apple.c
> @@ -42,8 +42,9 @@
> #define CORE_FABRIC_STAT_MASK 0x001F001F
> #define CORE_LANE_CFG(port) (0x84000 + 0x4000 * (port))
> #define CORE_LANE_CFG_REFCLK0REQ BIT(0)
> -#define CORE_LANE_CFG_REFCLK1 BIT(1)
> +#define CORE_LANE_CFG_REFCLK1REQ BIT(1)
> #define CORE_LANE_CFG_REFCLK0ACK BIT(2)
> +#define CORE_LANE_CFG_REFCLK1ACK BIT(3)
> #define CORE_LANE_CFG_REFCLKEN (BIT(9) | BIT(10))
> #define CORE_LANE_CTL(port) (0x84004 + 0x4000 * (port))
> #define CORE_LANE_CTL_CFGACC BIT(15)
> @@ -481,9 +482,9 @@ static int apple_pcie_setup_refclk(struct apple_pcie *pcie,
> if (res < 0)
> return res;
>
> - rmw_set(CORE_LANE_CFG_REFCLK1, pcie->base + CORE_LANE_CFG(port->idx));
> + rmw_set(CORE_LANE_CFG_REFCLK1REQ, pcie->base + CORE_LANE_CFG(port->idx));
> res = readl_relaxed_poll_timeout(pcie->base + CORE_LANE_CFG(port->idx),
> - stat, stat & CORE_LANE_CFG_REFCLK1,
> + stat, stat & CORE_LANE_CFG_REFCLK1ACK,
> 100, 50000);
>
> if (res < 0)
> --
> 2.33.0
>
>
Fixes: 1e33888fbe44 ("PCI: apple: Add initial hardware bring-up")
Acked-by: Marc Zyngier <maz@kernel.org>
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] PCI: apple: Fix REFCLK1 enable/poll logic
2021-11-17 17:56 ` Marc Zyngier
@ 2021-11-30 16:49 ` Lorenzo Pieralisi
2021-11-30 17:26 ` Hector Martin
0 siblings, 1 reply; 5+ messages in thread
From: Lorenzo Pieralisi @ 2021-11-30 16:49 UTC (permalink / raw)
To: Marc Zyngier, bhelgaas
Cc: Hector Martin, Alyssa Rosenzweig, Rob Herring,
Krzysztof Wilczyński, linux-pci, linux-kernel
On Wed, Nov 17, 2021 at 05:56:12PM +0000, Marc Zyngier wrote:
> On Wed, 17 Nov 2021 14:00:44 +0000,
> Hector Martin <marcan@marcan.st> wrote:
> >
> > REFCLK1 has req/ack bits just like REFCLK0
> >
> > Signed-off-by: Hector Martin <marcan@marcan.st>
> > ---
> > drivers/pci/controller/pcie-apple.c | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c
> > index b665d29af77a..420c291a5c68 100644
> > --- a/drivers/pci/controller/pcie-apple.c
> > +++ b/drivers/pci/controller/pcie-apple.c
> > @@ -42,8 +42,9 @@
> > #define CORE_FABRIC_STAT_MASK 0x001F001F
> > #define CORE_LANE_CFG(port) (0x84000 + 0x4000 * (port))
> > #define CORE_LANE_CFG_REFCLK0REQ BIT(0)
> > -#define CORE_LANE_CFG_REFCLK1 BIT(1)
> > +#define CORE_LANE_CFG_REFCLK1REQ BIT(1)
> > #define CORE_LANE_CFG_REFCLK0ACK BIT(2)
> > +#define CORE_LANE_CFG_REFCLK1ACK BIT(3)
> > #define CORE_LANE_CFG_REFCLKEN (BIT(9) | BIT(10))
> > #define CORE_LANE_CTL(port) (0x84004 + 0x4000 * (port))
> > #define CORE_LANE_CTL_CFGACC BIT(15)
> > @@ -481,9 +482,9 @@ static int apple_pcie_setup_refclk(struct apple_pcie *pcie,
> > if (res < 0)
> > return res;
> >
> > - rmw_set(CORE_LANE_CFG_REFCLK1, pcie->base + CORE_LANE_CFG(port->idx));
> > + rmw_set(CORE_LANE_CFG_REFCLK1REQ, pcie->base + CORE_LANE_CFG(port->idx));
> > res = readl_relaxed_poll_timeout(pcie->base + CORE_LANE_CFG(port->idx),
> > - stat, stat & CORE_LANE_CFG_REFCLK1,
> > + stat, stat & CORE_LANE_CFG_REFCLK1ACK,
> > 100, 50000);
> >
> > if (res < 0)
> > --
> > 2.33.0
> >
> >
>
> Fixes: 1e33888fbe44 ("PCI: apple: Add initial hardware bring-up")
> Acked-by: Marc Zyngier <maz@kernel.org>
Hi Hector, Bjorn,
if this is a fix we can aim at one of the upcoming -rcX.
It would be nicer though to explain a bit better what it is
fixing in the commit log (and what's broken if we don't merge it),
as it stands it is a bit terse.
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] PCI: apple: Fix REFCLK1 enable/poll logic
2021-11-30 16:49 ` Lorenzo Pieralisi
@ 2021-11-30 17:26 ` Hector Martin
0 siblings, 0 replies; 5+ messages in thread
From: Hector Martin @ 2021-11-30 17:26 UTC (permalink / raw)
To: Lorenzo Pieralisi, Marc Zyngier, bhelgaas
Cc: Alyssa Rosenzweig, Rob Herring, Krzysztof Wilczyński,
linux-pci, linux-kernel
On 01/12/2021 01.49, Lorenzo Pieralisi wrote:
> On Wed, Nov 17, 2021 at 05:56:12PM +0000, Marc Zyngier wrote:
>> On Wed, 17 Nov 2021 14:00:44 +0000,
>> Hector Martin <marcan@marcan.st> wrote:
>>>
>>> REFCLK1 has req/ack bits just like REFCLK0
>>>
>>> Signed-off-by: Hector Martin <marcan@marcan.st>
>>> ---
>>> drivers/pci/controller/pcie-apple.c | 7 ++++---
>>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c
>>> index b665d29af77a..420c291a5c68 100644
>>> --- a/drivers/pci/controller/pcie-apple.c
>>> +++ b/drivers/pci/controller/pcie-apple.c
>>> @@ -42,8 +42,9 @@
>>> #define CORE_FABRIC_STAT_MASK 0x001F001F
>>> #define CORE_LANE_CFG(port) (0x84000 + 0x4000 * (port))
>>> #define CORE_LANE_CFG_REFCLK0REQ BIT(0)
>>> -#define CORE_LANE_CFG_REFCLK1 BIT(1)
>>> +#define CORE_LANE_CFG_REFCLK1REQ BIT(1)
>>> #define CORE_LANE_CFG_REFCLK0ACK BIT(2)
>>> +#define CORE_LANE_CFG_REFCLK1ACK BIT(3)
>>> #define CORE_LANE_CFG_REFCLKEN (BIT(9) | BIT(10))
>>> #define CORE_LANE_CTL(port) (0x84004 + 0x4000 * (port))
>>> #define CORE_LANE_CTL_CFGACC BIT(15)
>>> @@ -481,9 +482,9 @@ static int apple_pcie_setup_refclk(struct apple_pcie *pcie,
>>> if (res < 0)
>>> return res;
>>>
>>> - rmw_set(CORE_LANE_CFG_REFCLK1, pcie->base + CORE_LANE_CFG(port->idx));
>>> + rmw_set(CORE_LANE_CFG_REFCLK1REQ, pcie->base + CORE_LANE_CFG(port->idx));
>>> res = readl_relaxed_poll_timeout(pcie->base + CORE_LANE_CFG(port->idx),
>>> - stat, stat & CORE_LANE_CFG_REFCLK1,
>>> + stat, stat & CORE_LANE_CFG_REFCLK1ACK,
>>> 100, 50000);
>>>
>>> if (res < 0)
>>> --
>>> 2.33.0
>>>
>>>
>>
>> Fixes: 1e33888fbe44 ("PCI: apple: Add initial hardware bring-up")
>> Acked-by: Marc Zyngier <maz@kernel.org>
>
> Hi Hector, Bjorn,
>
> if this is a fix we can aim at one of the upcoming -rcX.
>
> It would be nicer though to explain a bit better what it is
> fixing in the commit log (and what's broken if we don't merge it),
> as it stands it is a bit terse.
I don't think anything is broken per se, it still works without this
patch (probably because the refclk gets enabled fast enough that we
don't have to wait for it); it's just that I think this is the correct
logic. This is all reverse engineered anyway, so ultimately there is no
hardware documentation to point to to say what's right and what's wrong...
--
Hector Martin (marcan@marcan.st)
Public Key: https://mrcn.st/pub
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] PCI: apple: Fix REFCLK1 enable/poll logic
2021-11-17 14:00 [PATCH] PCI: apple: Fix REFCLK1 enable/poll logic Hector Martin
2021-11-17 17:56 ` Marc Zyngier
@ 2021-12-06 10:45 ` Lorenzo Pieralisi
1 sibling, 0 replies; 5+ messages in thread
From: Lorenzo Pieralisi @ 2021-12-06 10:45 UTC (permalink / raw)
To: Alyssa Rosenzweig, Marc Zyngier, Hector Martin
Cc: Lorenzo Pieralisi, linux-pci, Krzysztof Wilczyński,
Rob Herring, linux-kernel, Bjorn Helgaas
On Wed, 17 Nov 2021 23:00:44 +0900, Hector Martin wrote:
> REFCLK1 has req/ack bits just like REFCLK0
>
>
Applied to pci/apple, thanks!
[1/1] PCI: apple: Fix REFCLK1 enable/poll logic
https://git.kernel.org/lpieralisi/pci/c/75d36df680
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 5+ messages in thread
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2021-11-17 14:00 [PATCH] PCI: apple: Fix REFCLK1 enable/poll logic Hector Martin
2021-11-17 17:56 ` Marc Zyngier
2021-11-30 16:49 ` Lorenzo Pieralisi
2021-11-30 17:26 ` Hector Martin
2021-12-06 10:45 ` Lorenzo Pieralisi
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