[PATCH] arm64: dts: ti: k3-j721e: Fix the L2 cache sets

[PATCH] arm64: dts: ti: k3-j721e: Fix the L2 cache sets

[Nishanth Menon]

A72's L2 cache[1] on J721e[2] is 1MB. A53's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.

1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] http://www.ti.com/lit/pdf/spruil1

Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 214359e7288b..0f674bc8f1c7 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -88,7 +88,7 @@ L2_0: l2-cache0 {
 		cache-level = <2>;
 		cache-size = <0x100000>;
 		cache-line-size = <64>;
-		cache-sets = <2048>;
+		cache-sets = <1024>;
 		next-level-cache = <&msmc_l3>;
 	};
 
-- 
2.32.0

Re: [PATCH] arm64: dts: ti: k3-j721e: Fix the L2 cache sets

[Pratyush Yadav]

On 12/11/21 10:36PM, Nishanth Menon wrote:
> A72's L2 cache[1] on J721e[2] is 1MB. A53's L2 is fixed line length of
                                        ^^^

Do you mean A72? J721E does not have an A53 core, and this cache node is 
for A72 cores anyway.

Other than this,

Reviewed-by: Pratyush Yadav <p.yadav@ti.com>

> 64 bytes and 16-way set-associative cache structure.
> 
> 1MB of L2 / 64 (line length) = 16384 ways
> 16384 ways / 16 = 1024 sets
> 
> Fix the l2 cache-sets.
> 
> [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
> [2] http://www.ti.com/lit/pdf/spruil1
> 
> Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC")
> Reported-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> index 214359e7288b..0f674bc8f1c7 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> @@ -88,7 +88,7 @@ L2_0: l2-cache0 {
>  		cache-level = <2>;
>  		cache-size = <0x100000>;
>  		cache-line-size = <64>;
> -		cache-sets = <2048>;
> +		cache-sets = <1024>;
>  		next-level-cache = <&msmc_l3>;
>  	};
>  

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

Re: [PATCH] arm64: dts: ti: k3-j721e: Fix the L2 cache sets

[Vignesh Raghavendra]

Hi Nishanth Menon,
 
On Fri, 12 Nov 2021 22:36:39 -0600, Nishanth Menon wrote:
> A72's L2 cache[1] on J721e[2] is 1MB. A53's L2 is fixed line length of
> 64 bytes and 16-way set-associative cache structure.
> 

Replaced A53 reference with A72 locally and applied.


> 1MB of L2 / 64 (line length) = 16384 ways
> 16384 ways / 16 = 1024 sets
> 
> Fix the l2 cache-sets.
> 
> [...]
 
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
 
[1/1] arm64: dts: ti: k3-j721e: Fix the L2 cache sets
      commit: e9ba3a5bc6fdc2c796c69fdaf5ed6c9957cf9f9d
 
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
 
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
 
If any updates are required or you are submitting further changes they
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh