* [PATCH] x86/perf: Avoid warning for Arch LBR without XSAVE
@ 2021-12-15 20:40 Andi Kleen
2022-01-18 11:17 ` [tip: perf/urgent] " tip-bot2 for Andi Kleen
0 siblings, 1 reply; 2+ messages in thread
From: Andi Kleen @ 2021-12-15 20:40 UTC (permalink / raw)
To: peterz; +Cc: linux-kernel, kan.liang, Andi Kleen
Some hypervisors support Arch LBR, but without the LBR XSAVE support.
The current Arch LBR init code prints a warning when the xsave size (0) is
unexpected. Avoid printing the warning for the "no LBR XSAVE" case.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/events/intel/lbr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 8043213b75a5..1b8fef8545fb 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1726,6 +1726,8 @@ static bool is_arch_lbr_xsave_available(void)
* Check the LBR state with the corresponding software structure.
* Disable LBR XSAVES support if the size doesn't match.
*/
+ if (xfeature_size(XFEATURE_LBR) == 0)
+ return false;
if (WARN_ON(xfeature_size(XFEATURE_LBR) != get_lbr_state_size()))
return false;
--
2.33.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [tip: perf/urgent] x86/perf: Avoid warning for Arch LBR without XSAVE
2021-12-15 20:40 [PATCH] x86/perf: Avoid warning for Arch LBR without XSAVE Andi Kleen
@ 2022-01-18 11:17 ` tip-bot2 for Andi Kleen
0 siblings, 0 replies; 2+ messages in thread
From: tip-bot2 for Andi Kleen @ 2022-01-18 11:17 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Andi Kleen, Peter Zijlstra (Intel), x86, linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 8c16dc047b5dd8f7b3bf4584fa75733ea0dde7dc
Gitweb: https://git.kernel.org/tip/8c16dc047b5dd8f7b3bf4584fa75733ea0dde7dc
Author: Andi Kleen <ak@linux.intel.com>
AuthorDate: Wed, 15 Dec 2021 12:40:29 -08:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Tue, 18 Jan 2022 12:09:49 +01:00
x86/perf: Avoid warning for Arch LBR without XSAVE
Some hypervisors support Arch LBR, but without the LBR XSAVE support.
The current Arch LBR init code prints a warning when the xsave size (0) is
unexpected. Avoid printing the warning for the "no LBR XSAVE" case.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20211215204029.150686-1-ak@linux.intel.com
---
arch/x86/events/intel/lbr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index f8fd255..669c2be 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1751,6 +1751,9 @@ static bool is_arch_lbr_xsave_available(void)
* Check the LBR state with the corresponding software structure.
* Disable LBR XSAVES support if the size doesn't match.
*/
+ if (xfeature_size(XFEATURE_LBR) == 0)
+ return false;
+
if (WARN_ON(xfeature_size(XFEATURE_LBR) != get_lbr_state_size()))
return false;
^ permalink raw reply related [flat|nested] 2+ messages in thread
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