* [PATCH 0/3]
@ 2022-01-03 9:21 Antoniu Miclaus
2022-01-03 9:21 ` [PATCH 1/3] iio:frequency:admv1014: add support for ADMV1014 Antoniu Miclaus
` (2 more replies)
0 siblings, 3 replies; 17+ messages in thread
From: Antoniu Miclaus @ 2022-01-03 9:21 UTC (permalink / raw)
To: jic23, robh+dt, linux-iio, devicetree, linux-kernel; +Cc: Antoniu Miclaus
The ADMV1014 is a silicon germanium (SiGe), wideband,
microwave downconverter optimized for point to point microwave
radio designs operating in the 24 GHz to 44 GHz frequency range.
Datasheet:
https://www.analog.com/media/en/technical-documentation/data-sheets/ADMV1014.pdf
NOTE:
Currently depends on 64-bit architecture since the input
clock that server as Local Oscillator should support values
in the range 24 GHz to 44 GHz.
We might need some scaling implementation in the clock
framework so that u64 types are supported when using 32-bit
architectures.
Antoniu Miclaus (3):
iio:frequency:admv1014: add support for ADMV1014
dt-bindings:iio:frequency: add admv1014 doc
Documentation:ABI:testing:admv1014: add ABI docs
.../testing/sysfs-bus-iio-frequency-admv1014 | 23 +
.../bindings/iio/frequency/adi,admv1014.yaml | 97 +++
drivers/iio/frequency/Kconfig | 10 +
drivers/iio/frequency/Makefile | 1 +
drivers/iio/frequency/admv1014.c | 784 ++++++++++++++++++
5 files changed, 915 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014
create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml
create mode 100644 drivers/iio/frequency/admv1014.c
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 1/3] iio:frequency:admv1014: add support for ADMV1014 2022-01-03 9:21 [PATCH 0/3] Antoniu Miclaus @ 2022-01-03 9:21 ` Antoniu Miclaus 2022-01-09 18:01 ` Jonathan Cameron 2022-01-03 9:22 ` [PATCH 2/3] dt-bindings:iio:frequency: add admv1014 doc Antoniu Miclaus 2022-01-03 9:22 ` [PATCH 3/3] Documentation:ABI:testing:admv1014: add ABI docs Antoniu Miclaus 2 siblings, 1 reply; 17+ messages in thread From: Antoniu Miclaus @ 2022-01-03 9:21 UTC (permalink / raw) To: jic23, robh+dt, linux-iio, devicetree, linux-kernel; +Cc: Antoniu Miclaus The ADMV1014 is a silicon germanium (SiGe), wideband, microwave downconverter optimized for point to point microwave radio designs operating in the 24 GHz to 44 GHz frequency range. Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ADMV1014.pdf Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> --- drivers/iio/frequency/Kconfig | 10 + drivers/iio/frequency/Makefile | 1 + drivers/iio/frequency/admv1014.c | 784 +++++++++++++++++++++++++++++++ 3 files changed, 795 insertions(+) create mode 100644 drivers/iio/frequency/admv1014.c diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig index 2c9e0559e8a4..493221f42077 100644 --- a/drivers/iio/frequency/Kconfig +++ b/drivers/iio/frequency/Kconfig @@ -50,6 +50,16 @@ config ADF4371 To compile this driver as a module, choose M here: the module will be called adf4371. +config ADMV1014 + tristate "Analog Devices ADMV1014 Microwave Downconverter" + depends on SPI && COMMON_CLK && 64BIT + help + Say yes here to build support for Analog Devices ADMV1014 + 24 GHz to 44 GHz, Wideband, Microwave Downconverter. + + To compile this driver as a module, choose M here: the + module will be called admv1014. + config ADRF6780 tristate "Analog Devices ADRF6780 Microwave Upconverter" depends on SPI diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile index ae3136c79202..5f0348e5eb53 100644 --- a/drivers/iio/frequency/Makefile +++ b/drivers/iio/frequency/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_AD9523) += ad9523.o obj-$(CONFIG_ADF4350) += adf4350.o obj-$(CONFIG_ADF4371) += adf4371.o +obj-$(CONFIG_ADMV1014) += admv1014.o obj-$(CONFIG_ADRF6780) += adrf6780.o diff --git a/drivers/iio/frequency/admv1014.c b/drivers/iio/frequency/admv1014.c new file mode 100644 index 000000000000..2b6c38e82f92 --- /dev/null +++ b/drivers/iio/frequency/admv1014.c @@ -0,0 +1,784 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ADMV1014 driver + * + * Copyright 2021 Analog Devices Inc. + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/iio/iio.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/notifier.h> +#include <linux/property.h> +#include <linux/regulator/consumer.h> +#include <linux/spi/spi.h> +#include <linux/units.h> + +#include <asm/unaligned.h> + +/* ADMV1014 Register Map */ +#define ADMV1014_REG_SPI_CONTROL 0x00 +#define ADMV1014_REG_ALARM 0x01 +#define ADMV1014_REG_ALARM_MASKS 0x02 +#define ADMV1014_REG_ENABLE 0x03 +#define ADMV1014_REG_QUAD 0x04 +#define ADMV1014_REG_LO_AMP_PHASE_ADJUST1 0x05 +#define ADMV1014_REG_MIXER 0x07 +#define ADMV1014_REG_IF_AMP 0x08 +#define ADMV1014_REG_IF_AMP_BB_AMP 0x09 +#define ADMV1014_REG_BB_AMP_AGC 0x0A +#define ADMV1014_REG_VVA_TEMP_COMP 0x0B + +/* ADMV1014_REG_SPI_CONTROL Map */ +#define ADMV1014_PARITY_EN_MSK BIT(15) +#define ADMV1014_SPI_SOFT_RESET_MSK BIT(14) +#define ADMV1014_CHIP_ID_MSK GENMASK(11, 4) +#define ADMV1014_CHIP_ID 0x9 +#define ADMV1014_REVISION_ID_MSK GENMASK(3, 0) + +/* ADMV1014_REG_ALARM Map */ +#define ADMV1014_PARITY_ERROR_MSK BIT(15) +#define ADMV1014_TOO_FEW_ERRORS_MSK BIT(14) +#define ADMV1014_TOO_MANY_ERRORS_MSK BIT(13) +#define ADMV1014_ADDRESS_RANGE_ERROR_MSK BIT(12) + +/* ADMV1014_REG_ENABLE Map */ +#define ADMV1014_IBIAS_PD_MSK BIT(14) +#define ADMV1014_P1DB_COMPENSATION_MSK GENMASK(13, 12) +#define ADMV1014_IF_AMP_PD_MSK BIT(11) +#define ADMV1014_QUAD_BG_PD_MSK BIT(9) +#define ADMV1014_BB_AMP_PD_MSK BIT(8) +#define ADMV1014_QUAD_IBIAS_PD_MSK BIT(7) +#define ADMV1014_DET_EN_MSK BIT(6) +#define ADMV1014_BG_PD_MSK BIT(5) + +/* ADMV1014_REG_QUAD Map */ +#define ADMV1014_QUAD_SE_MODE_MSK GENMASK(9, 6) +#define ADMV1014_QUAD_FILTERS_MSK GENMASK(3, 0) + +/* ADMV1014_REG_LO_AMP_PHASE_ADJUST1 Map */ +#define ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK GENMASK(15, 9) +#define ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK GENMASK(8, 2) + +/* ADMV1014_REG_MIXER Map */ +#define ADMV1014_MIXER_VGATE_MSK GENMASK(15, 9) +#define ADMV1014_DET_PROG_MSK GENMASK(6, 0) + +/* ADMV1014_REG_IF_AMP Map */ +#define ADMV1014_IF_AMP_COARSE_GAIN_I_MSK GENMASK(11, 8) +#define ADMV1014_IF_AMP_FINE_GAIN_Q_MSK GENMASK(7, 4) +#define ADMV1014_IF_AMP_FINE_GAIN_I_MSK GENMASK(3, 0) + +/* ADMV1014_REG_IF_AMP_BB_AMP Map */ +#define ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK GENMASK(15, 12) +#define ADMV1014_BB_AMP_OFFSET_Q_MSK GENMASK(9, 5) +#define ADMV1014_BB_AMP_OFFSET_I_MSK GENMASK(4, 0) + +/* ADMV1014_REG_BB_AMP_AGC Map */ +#define ADMV1014_BB_AMP_REF_GEN_MSK GENMASK(6, 3) +#define ADMV1014_BB_AMP_GAIN_CTRL_MSK GENMASK(2, 1) +#define ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK BIT(0) + +/* ADMV1014_REG_VVA_TEMP_COMP Map */ +#define ADMV1014_VVA_TEMP_COMP_MSK GENMASK(15, 0) + +/* ADMV1014 Miscellaneous Defines */ +#define ADMV1014_READ BIT(7) +#define ADMV1014_REG_ADDR_READ_MSK GENMASK(6, 1) +#define ADMV1014_REG_ADDR_WRITE_MSK GENMASK(22, 17) +#define ADMV1014_REG_DATA_MSK GENMASK(16, 1) + +enum { + ADMV1014_IQ_MODE, + ADMV1014_IF_MODE +}; + +enum { + ADMV1014_SE_MODE_POS = 6, + ADMV1014_SE_MODE_NEG = 9, + ADMV1014_SE_MODE_DIFF = 12 +}; + +enum { + ADMV1014_GAIN_COARSE, + ADMV1014_GAIN_FINE, +}; + +static const int detector_table[] = {0, 1, 2, 4, 8, 16, 32, 64}; + +struct admv1014_state { + struct spi_device *spi; + struct clk *clkin; + struct notifier_block nb; + /* Protect against concurrent accesses to the device and to data*/ + struct mutex lock; + struct regulator *reg; + unsigned int input_mode; + unsigned int quad_se_mode; + unsigned int p1db_comp; + bool det_en; + u8 data[3] ____cacheline_aligned; +}; + +static const int mixer_vgate_table[] = {106, 107, 108, 110, 111, 112, 113, 114, 117, 118, 119, 120, 122, 123, 44, 45}; + +static int __admv1014_spi_read(struct admv1014_state *st, unsigned int reg, + unsigned int *val) +{ + int ret; + struct spi_transfer t = {0}; + + st->data[0] = ADMV1014_READ | FIELD_PREP(ADMV1014_REG_ADDR_READ_MSK, reg); + st->data[1] = 0x0; + st->data[2] = 0x0; + + t.rx_buf = &st->data[0]; + t.tx_buf = &st->data[0]; + t.len = 3; + + ret = spi_sync_transfer(st->spi, &t, 1); + if (ret) + return ret; + + *val = FIELD_GET(ADMV1014_REG_DATA_MSK, get_unaligned_be24(&st->data[0])); + + return ret; +} + +static int admv1014_spi_read(struct admv1014_state *st, unsigned int reg, + unsigned int *val) +{ + int ret; + + mutex_lock(&st->lock); + ret = __admv1014_spi_read(st, reg, val); + mutex_unlock(&st->lock); + + return ret; +} + +static int __admv1014_spi_write(struct admv1014_state *st, + unsigned int reg, + unsigned int val) +{ + put_unaligned_be24(FIELD_PREP(ADMV1014_REG_DATA_MSK, val) | + FIELD_PREP(ADMV1014_REG_ADDR_WRITE_MSK, reg), &st->data[0]); + + return spi_write(st->spi, &st->data[0], 3); +} + +static int admv1014_spi_write(struct admv1014_state *st, unsigned int reg, + unsigned int val) +{ + int ret; + + mutex_lock(&st->lock); + ret = __admv1014_spi_write(st, reg, val); + mutex_unlock(&st->lock); + + return ret; +} + +static int __admv1014_spi_update_bits(struct admv1014_state *st, unsigned int reg, + unsigned int mask, unsigned int val) +{ + int ret; + unsigned int data, temp; + + ret = __admv1014_spi_read(st, reg, &data); + if (ret) + return ret; + + temp = (data & ~mask) | (val & mask); + + return __admv1014_spi_write(st, reg, temp); +} + +static int admv1014_spi_update_bits(struct admv1014_state *st, unsigned int reg, + unsigned int mask, unsigned int val) +{ + int ret; + + mutex_lock(&st->lock); + ret = __admv1014_spi_update_bits(st, reg, mask, val); + mutex_unlock(&st->lock); + + return ret; +} + +static int admv1014_update_quad_filters(struct admv1014_state *st) +{ + unsigned int filt_raw; + u64 rate = clk_get_rate(st->clkin); + + if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ)) + filt_raw = 15; + else if (rate >= (5400 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ)) + filt_raw = 10; + else if (rate >= (6600 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ)) + filt_raw = 5; + else + filt_raw = 0; + + return __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD, + ADMV1014_QUAD_FILTERS_MSK, + FIELD_PREP(ADMV1014_QUAD_FILTERS_MSK, filt_raw)); +} + +static int admv1014_update_vcm_settings(struct admv1014_state *st) +{ + unsigned int i, vcm_mv, vcm_comp, bb_sw_high_low_cm; + int ret; + + vcm_mv = regulator_get_voltage(st->reg) / 1000; + for (i = 0; i < ARRAY_SIZE(mixer_vgate_table); i++) { + vcm_comp = 1050 + (i * 50) + (i / 8 * 50); + if (vcm_mv == vcm_comp) { + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_MIXER, + ADMV1014_MIXER_VGATE_MSK, + FIELD_PREP(ADMV1014_MIXER_VGATE_MSK, + mixer_vgate_table[i])); + if (ret) + return ret; + + bb_sw_high_low_cm = ~(i / 8); + + return __admv1014_spi_update_bits(st, ADMV1014_REG_BB_AMP_AGC, + ADMV1014_BB_AMP_REF_GEN_MSK | + ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK, + FIELD_PREP(ADMV1014_BB_AMP_REF_GEN_MSK, i) | + FIELD_PREP(ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK, bb_sw_high_low_cm)); + } + } + + return -EINVAL; +} + +static int admv1014_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct admv1014_state *st = iio_priv(indio_dev); + unsigned int data; + int ret; + + switch (info) { + case IIO_CHAN_INFO_OFFSET: + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP_BB_AMP, &data); + if (ret) + return ret; + + if (chan->channel2 == IIO_MOD_I) + *val = FIELD_GET(ADMV1014_BB_AMP_OFFSET_I_MSK, data); + else + *val = FIELD_GET(ADMV1014_BB_AMP_OFFSET_Q_MSK, data); + + return IIO_VAL_INT; + case IIO_CHAN_INFO_PHASE: + ret = admv1014_spi_read(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, &data); + if (ret) + return ret; + + if (chan->channel2 == IIO_MOD_I) + *val = FIELD_GET(ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, data); + else + *val = FIELD_GET(ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, data); + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + ret = admv1014_spi_read(st, ADMV1014_REG_MIXER, &data); + if (ret) + return ret; + + *val = FIELD_GET(ADMV1014_DET_PROG_MSK, data); + return IIO_VAL_INT; + case IIO_CHAN_INFO_HARDWAREGAIN: + ret = admv1014_spi_read(st, ADMV1014_REG_BB_AMP_AGC, &data); + if (ret) + return ret; + + *val = FIELD_GET(ADMV1014_BB_AMP_GAIN_CTRL_MSK, data); + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int admv1014_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + struct admv1014_state *st = iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_OFFSET: + if (chan->channel2 == IIO_MOD_I) + return admv1014_spi_update_bits(st, ADMV1014_REG_IF_AMP_BB_AMP, + ADMV1014_BB_AMP_OFFSET_I_MSK, + FIELD_PREP(ADMV1014_BB_AMP_OFFSET_I_MSK, val)); + else + return admv1014_spi_update_bits(st, ADMV1014_REG_IF_AMP_BB_AMP, + ADMV1014_BB_AMP_OFFSET_Q_MSK, + FIELD_PREP(ADMV1014_BB_AMP_OFFSET_Q_MSK, val)); + case IIO_CHAN_INFO_PHASE: + if (chan->channel2 == IIO_MOD_I) + return admv1014_spi_update_bits(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, + ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, + FIELD_PREP(ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, val)); + else + return admv1014_spi_update_bits(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, + ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, + FIELD_PREP(ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, val)); + case IIO_CHAN_INFO_SCALE: + return admv1014_spi_update_bits(st, ADMV1014_REG_MIXER, + ADMV1014_DET_PROG_MSK, + FIELD_PREP(ADMV1014_DET_PROG_MSK, val)); + case IIO_CHAN_INFO_HARDWAREGAIN: + return admv1014_spi_update_bits(st, ADMV1014_REG_BB_AMP_AGC, + ADMV1014_BB_AMP_GAIN_CTRL_MSK, + FIELD_PREP(ADMV1014_BB_AMP_GAIN_CTRL_MSK, val)); + default: + return -EINVAL; + } +} + +static ssize_t admv1014_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct admv1014_state *st = iio_priv(indio_dev); + unsigned int data; + int ret; + + switch ((u32)private) { + case ADMV1014_GAIN_COARSE: + if (chan->channel2 == IIO_MOD_I) { + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP, &data); + if (ret) + return ret; + + data = FIELD_GET(ADMV1014_IF_AMP_COARSE_GAIN_I_MSK, data); + } else { + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP_BB_AMP, &data); + if (ret) + return ret; + + data = FIELD_GET(ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK, data); + } + break; + case ADMV1014_GAIN_FINE: + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP, &data); + if (ret) + return ret; + + if (chan->channel2 == IIO_MOD_I) + data = FIELD_GET(ADMV1014_IF_AMP_FINE_GAIN_I_MSK, data); + else + data = FIELD_GET(ADMV1014_IF_AMP_FINE_GAIN_Q_MSK, data); + break; + default: + return -EINVAL; + } + + return sysfs_emit(buf, "%u\n", data); +} + +static ssize_t admv1014_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct admv1014_state *st = iio_priv(indio_dev); + unsigned int data, addr, msk; + int ret; + + ret = kstrtou32(buf, 10, &data); + if (ret) + return ret; + + switch ((u32)private) { + case ADMV1014_GAIN_COARSE: + if (chan->channel2 == IIO_MOD_I) { + addr = ADMV1014_REG_IF_AMP; + msk = ADMV1014_IF_AMP_COARSE_GAIN_I_MSK; + data = FIELD_PREP(ADMV1014_IF_AMP_COARSE_GAIN_I_MSK, data); + } else { + addr = ADMV1014_REG_IF_AMP_BB_AMP; + msk = ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK; + data = FIELD_PREP(ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK, data); + } + break; + case ADMV1014_GAIN_FINE: + addr = ADMV1014_REG_IF_AMP; + + if (chan->channel2 == IIO_MOD_I) { + msk = ADMV1014_IF_AMP_FINE_GAIN_I_MSK; + data = FIELD_PREP(ADMV1014_IF_AMP_FINE_GAIN_I_MSK, data); + } else { + msk = ADMV1014_IF_AMP_FINE_GAIN_Q_MSK; + data = FIELD_PREP(ADMV1014_IF_AMP_FINE_GAIN_Q_MSK, data); + } + break; + default: + return -EINVAL; + } + + ret = admv1014_spi_update_bits(st, addr, msk, data); + + return ret ? ret : len; +} + +static int admv1014_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + switch (info) { + case IIO_CHAN_INFO_SCALE: + *vals = detector_table; + *type = IIO_VAL_INT; + *length = ARRAY_SIZE(detector_table); + + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static int admv1014_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int write_val, + unsigned int *read_val) +{ + struct admv1014_state *st = iio_priv(indio_dev); + int ret; + + if (read_val) + ret = admv1014_spi_read(st, reg, read_val); + else + ret = admv1014_spi_write(st, reg, write_val); + + return ret; +} + +static const struct iio_info admv1014_info = { + .read_raw = admv1014_read_raw, + .write_raw = admv1014_write_raw, + .read_avail = &admv1014_read_avail, + .debugfs_reg_access = &admv1014_reg_access, +}; + +static int admv1014_freq_change(struct notifier_block *nb, unsigned long action, void *data) +{ + struct admv1014_state *st = container_of(nb, struct admv1014_state, nb); + int ret; + + if (action == POST_RATE_CHANGE) { + mutex_lock(&st->lock); + ret = notifier_from_errno(admv1014_update_quad_filters(st)); + mutex_unlock(&st->lock); + return ret; + } + + return NOTIFY_OK; +} + +#define _ADMV1014_EXT_INFO(_name, _shared, _ident) { \ + .name = _name, \ + .read = admv1014_read, \ + .write = admv1014_write, \ + .private = _ident, \ + .shared = _shared, \ +} + +static const struct iio_chan_spec_ext_info admv1014_ext_info[] = { + _ADMV1014_EXT_INFO("gain_coarse", IIO_SEPARATE, ADMV1014_GAIN_COARSE), + _ADMV1014_EXT_INFO("gain_fine", IIO_SEPARATE, ADMV1014_GAIN_FINE), + { }, +}; + +#define ADMV1014_CHAN(_channel, rf_comp) { \ + .type = IIO_ALTVOLTAGE, \ + .modified = 1, \ + .output = 0, \ + .indexed = 1, \ + .channel2 = IIO_MOD_##rf_comp, \ + .channel = _channel, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_HARDWAREGAIN) \ + } + +#define ADMV1014_CHAN_GAIN(_channel, rf_comp, _admv1014_ext_info) { \ + .type = IIO_ALTVOLTAGE, \ + .modified = 1, \ + .output = 0, \ + .indexed = 1, \ + .channel2 = IIO_MOD_##rf_comp, \ + .channel = _channel, \ + .ext_info = _admv1014_ext_info \ + } + +#define ADMV1014_CHAN_DETECTOR(_channel) { \ + .type = IIO_POWER, \ + .modified = 1, \ + .output = 0, \ + .indexed = 1, \ + .channel = _channel, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) \ + } + +static const struct iio_chan_spec admv1014_channels[] = { + ADMV1014_CHAN(0, I), + ADMV1014_CHAN(0, Q), + ADMV1014_CHAN_GAIN(0, I, admv1014_ext_info), + ADMV1014_CHAN_GAIN(0, Q, admv1014_ext_info), + ADMV1014_CHAN_DETECTOR(0) +}; + +static int admv1014_init(struct admv1014_state *st) +{ + int ret; + unsigned int chip_id, enable_reg, enable_reg_msk; + struct spi_device *spi = st->spi; + + /* Perform a software reset */ + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL, + ADMV1014_SPI_SOFT_RESET_MSK, + FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 1)); + if (ret) { + dev_err(&spi->dev, "ADMV1014 SPI software reset failed.\n"); + return ret; + } + + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL, + ADMV1014_SPI_SOFT_RESET_MSK, + FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 0)); + if (ret) { + dev_err(&spi->dev, "ADMV1014 SPI software reset disable failed.\n"); + return ret; + } + + ret = admv1014_spi_write(st, ADMV1014_REG_VVA_TEMP_COMP, 0x727C); + if (ret) { + dev_err(&spi->dev, "Writing default Temperature Compensation value failed.\n"); + return ret; + } + + ret = admv1014_spi_read(st, ADMV1014_REG_SPI_CONTROL, &chip_id); + if (ret) + return ret; + + chip_id = (chip_id & ADMV1014_CHIP_ID_MSK) >> 4; + if (chip_id != ADMV1014_CHIP_ID) { + dev_err(&spi->dev, "Invalid Chip ID.\n"); + return -EINVAL; + } + + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD, + ADMV1014_QUAD_SE_MODE_MSK, + FIELD_PREP(ADMV1014_QUAD_SE_MODE_MSK, + st->quad_se_mode)); + if (ret) { + dev_err(&spi->dev, "Writing Quad SE Mode failed.\n"); + return ret; + } + + ret = admv1014_update_quad_filters(st); + if (ret) { + dev_err(&spi->dev, "Update Quad Filters failed.\n"); + return ret; + } + + ret = admv1014_update_vcm_settings(st); + if (ret) { + dev_err(&spi->dev, "Update VCM Settings failed.\n"); + return ret; + } + + enable_reg_msk = ADMV1014_P1DB_COMPENSATION_MSK | + ADMV1014_IF_AMP_PD_MSK | + ADMV1014_BB_AMP_PD_MSK | + ADMV1014_DET_EN_MSK; + + enable_reg = FIELD_PREP(ADMV1014_P1DB_COMPENSATION_MSK, st->p1db_comp) | + FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, !(st->input_mode)) | + FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, st->input_mode) | + FIELD_PREP(ADMV1014_DET_EN_MSK, st->det_en); + + return __admv1014_spi_update_bits(st, ADMV1014_REG_ENABLE, enable_reg_msk, enable_reg); +} + +static void admv1014_clk_disable(void *data) +{ + clk_disable_unprepare(data); +} + +static void admv1014_reg_disable(void *data) +{ + regulator_disable(data); +} + +static void admv1014_powerdown(void *data) +{ + unsigned int enable_reg, enable_reg_msk; + + /* Disable all components in the Enable Register */ + enable_reg_msk = ADMV1014_IBIAS_PD_MSK | + ADMV1014_IF_AMP_PD_MSK | + ADMV1014_QUAD_BG_PD_MSK | + ADMV1014_BB_AMP_PD_MSK | + ADMV1014_QUAD_IBIAS_PD_MSK | + ADMV1014_BG_PD_MSK; + + enable_reg = FIELD_PREP(ADMV1014_IBIAS_PD_MSK, 1) | + FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, 1) | + FIELD_PREP(ADMV1014_QUAD_BG_PD_MSK, 1) | + FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, 1) | + FIELD_PREP(ADMV1014_QUAD_IBIAS_PD_MSK, 1) | + FIELD_PREP(ADMV1014_BG_PD_MSK, 1); + + admv1014_spi_update_bits(data, ADMV1014_REG_ENABLE, enable_reg_msk, enable_reg); +} + +static int admv1014_properties_parse(struct admv1014_state *st) +{ + int ret; + const char *str; + struct spi_device *spi = st->spi; + + st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable"); + + st->p1db_comp = device_property_read_bool(&spi->dev, "adi,p1db-comp-enable"); + if (st->p1db_comp) + st->p1db_comp = 3; + + ret = device_property_read_string(&spi->dev, "adi,input-mode", &str); + if (ret) + st->input_mode = ADMV1014_IQ_MODE; + + if (!strcmp(str, "iq")) + st->input_mode = ADMV1014_IQ_MODE; + else if (!strcmp(str, "if")) + st->input_mode = ADMV1014_IF_MODE; + else + return -EINVAL; + + ret = device_property_read_string(&spi->dev, "adi,quad-se-mode", &str); + if (ret) + st->quad_se_mode = ADMV1014_SE_MODE_DIFF; + + if (!strcmp(str, "diff")) + st->quad_se_mode = ADMV1014_SE_MODE_DIFF; + else if (!strcmp(str, "se-pos")) + st->quad_se_mode = ADMV1014_SE_MODE_POS; + else if (!strcmp(str, "se-neg")) + st->quad_se_mode = ADMV1014_SE_MODE_NEG; + else + return -EINVAL; + + st->reg = devm_regulator_get(&spi->dev, "vcm"); + if (IS_ERR(st->reg)) + return dev_err_probe(&spi->dev, PTR_ERR(st->reg), + "failed to get the common-mode voltage\n"); + + st->clkin = devm_clk_get(&spi->dev, "lo_in"); + if (IS_ERR(st->clkin)) + return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), + "failed to get the LO input clock\n"); + + return 0; +} + +static int admv1014_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct admv1014_state *st; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + + indio_dev->info = &admv1014_info; + indio_dev->name = "admv1014"; + indio_dev->channels = admv1014_channels; + indio_dev->num_channels = ARRAY_SIZE(admv1014_channels); + + st->spi = spi; + + ret = admv1014_properties_parse(st); + if (ret) + return ret; + + ret = regulator_enable(st->reg); + if (ret) { + dev_err(&spi->dev, "Failed to enable specified Common-Mode Voltage!\n"); + return ret; + } + + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->reg); + if (ret) + return ret; + + ret = clk_prepare_enable(st->clkin); + if (ret) + return ret; + + ret = devm_add_action_or_reset(&spi->dev, admv1014_clk_disable, st->clkin); + if (ret) + return ret; + + st->nb.notifier_call = admv1014_freq_change; + ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb); + if (ret) + return ret; + + mutex_init(&st->lock); + + ret = admv1014_init(st); + if (ret) + return ret; + + ret = devm_add_action_or_reset(&spi->dev, admv1014_powerdown, st); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct spi_device_id admv1014_id[] = { + { "admv1014", 0 }, + {} +}; +MODULE_DEVICE_TABLE(spi, admv1014_id); + +static const struct of_device_id admv1014_of_match[] = { + { .compatible = "adi,admv1014" }, + {}, +}; +MODULE_DEVICE_TABLE(of, admv1014_of_match); + +static struct spi_driver admv1014_driver = { + .driver = { + .name = "admv1014", + .of_match_table = admv1014_of_match, + }, + .probe = admv1014_probe, + .id_table = admv1014_id, +}; +module_spi_driver(admv1014_driver); + +MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); +MODULE_DESCRIPTION("Analog Devices ADMV1014"); +MODULE_LICENSE("GPL v2"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 1/3] iio:frequency:admv1014: add support for ADMV1014 2022-01-03 9:21 ` [PATCH 1/3] iio:frequency:admv1014: add support for ADMV1014 Antoniu Miclaus @ 2022-01-09 18:01 ` Jonathan Cameron 0 siblings, 0 replies; 17+ messages in thread From: Jonathan Cameron @ 2022-01-09 18:01 UTC (permalink / raw) To: Antoniu Miclaus; +Cc: robh+dt, linux-iio, devicetree, linux-kernel On Mon, 3 Jan 2022 11:21:59 +0200 Antoniu Miclaus <antoniu.miclaus@analog.com> wrote: > The ADMV1014 is a silicon germanium (SiGe), wideband, > microwave downconverter optimized for point to point microwave > radio designs operating in the 24 GHz to 44 GHz frequency range. > > Datasheet: > https://www.analog.com/media/en/technical-documentation/data-sheets/ADMV1014.pdf One line as it's a tag. (doesn't matter it if is too long in this case :) > Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> > --- > drivers/iio/frequency/Kconfig | 10 + > drivers/iio/frequency/Makefile | 1 + > drivers/iio/frequency/admv1014.c | 784 +++++++++++++++++++++++++++++++ > 3 files changed, 795 insertions(+) > create mode 100644 drivers/iio/frequency/admv1014.c > > diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig > index 2c9e0559e8a4..493221f42077 100644 > --- a/drivers/iio/frequency/Kconfig > +++ b/drivers/iio/frequency/Kconfig > @@ -50,6 +50,16 @@ config ADF4371 > To compile this driver as a module, choose M here: the > module will be called adf4371. > > +config ADMV1014 > + tristate "Analog Devices ADMV1014 Microwave Downconverter" > + depends on SPI && COMMON_CLK && 64BIT > + help > + Say yes here to build support for Analog Devices ADMV1014 > + 24 GHz to 44 GHz, Wideband, Microwave Downconverter. > + > + To compile this driver as a module, choose M here: the > + module will be called admv1014. > + > config ADRF6780 > tristate "Analog Devices ADRF6780 Microwave Upconverter" > depends on SPI > diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile > index ae3136c79202..5f0348e5eb53 100644 > --- a/drivers/iio/frequency/Makefile > +++ b/drivers/iio/frequency/Makefile > @@ -7,4 +7,5 @@ > obj-$(CONFIG_AD9523) += ad9523.o > obj-$(CONFIG_ADF4350) += adf4350.o > obj-$(CONFIG_ADF4371) += adf4371.o > +obj-$(CONFIG_ADMV1014) += admv1014.o > obj-$(CONFIG_ADRF6780) += adrf6780.o > diff --git a/drivers/iio/frequency/admv1014.c b/drivers/iio/frequency/admv1014.c > new file mode 100644 > index 000000000000..2b6c38e82f92 > --- /dev/null > +++ b/drivers/iio/frequency/admv1014.c > @@ -0,0 +1,784 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * ADMV1014 driver > + * > + * Copyright 2021 Analog Devices Inc. 2022? :) > + */ > + > +#include <linux/bitfield.h> > +#include <linux/bits.h> > +#include <linux/clk.h> > +#include <linux/clkdev.h> > +#include <linux/clk-provider.h> > +#include <linux/device.h> > +#include <linux/iio/iio.h> > +#include <linux/module.h> > +#include <linux/mod_devicetable.h> > +#include <linux/notifier.h> > +#include <linux/property.h> > +#include <linux/regulator/consumer.h> > +#include <linux/spi/spi.h> > +#include <linux/units.h> > + > +#include <asm/unaligned.h> > + > +/* ADMV1014 Register Map */ > +#define ADMV1014_REG_SPI_CONTROL 0x00 > +#define ADMV1014_REG_ALARM 0x01 > +#define ADMV1014_REG_ALARM_MASKS 0x02 > +#define ADMV1014_REG_ENABLE 0x03 > +#define ADMV1014_REG_QUAD 0x04 > +#define ADMV1014_REG_LO_AMP_PHASE_ADJUST1 0x05 > +#define ADMV1014_REG_MIXER 0x07 > +#define ADMV1014_REG_IF_AMP 0x08 > +#define ADMV1014_REG_IF_AMP_BB_AMP 0x09 > +#define ADMV1014_REG_BB_AMP_AGC 0x0A > +#define ADMV1014_REG_VVA_TEMP_COMP 0x0B > + > +/* ADMV1014_REG_SPI_CONTROL Map */ > +#define ADMV1014_PARITY_EN_MSK BIT(15) > +#define ADMV1014_SPI_SOFT_RESET_MSK BIT(14) > +#define ADMV1014_CHIP_ID_MSK GENMASK(11, 4) > +#define ADMV1014_CHIP_ID 0x9 > +#define ADMV1014_REVISION_ID_MSK GENMASK(3, 0) > + > +/* ADMV1014_REG_ALARM Map */ > +#define ADMV1014_PARITY_ERROR_MSK BIT(15) > +#define ADMV1014_TOO_FEW_ERRORS_MSK BIT(14) > +#define ADMV1014_TOO_MANY_ERRORS_MSK BIT(13) > +#define ADMV1014_ADDRESS_RANGE_ERROR_MSK BIT(12) > + > +/* ADMV1014_REG_ENABLE Map */ > +#define ADMV1014_IBIAS_PD_MSK BIT(14) > +#define ADMV1014_P1DB_COMPENSATION_MSK GENMASK(13, 12) > +#define ADMV1014_IF_AMP_PD_MSK BIT(11) > +#define ADMV1014_QUAD_BG_PD_MSK BIT(9) > +#define ADMV1014_BB_AMP_PD_MSK BIT(8) > +#define ADMV1014_QUAD_IBIAS_PD_MSK BIT(7) > +#define ADMV1014_DET_EN_MSK BIT(6) > +#define ADMV1014_BG_PD_MSK BIT(5) > + > +/* ADMV1014_REG_QUAD Map */ > +#define ADMV1014_QUAD_SE_MODE_MSK GENMASK(9, 6) > +#define ADMV1014_QUAD_FILTERS_MSK GENMASK(3, 0) > + > +/* ADMV1014_REG_LO_AMP_PHASE_ADJUST1 Map */ > +#define ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK GENMASK(15, 9) > +#define ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK GENMASK(8, 2) > + > +/* ADMV1014_REG_MIXER Map */ > +#define ADMV1014_MIXER_VGATE_MSK GENMASK(15, 9) > +#define ADMV1014_DET_PROG_MSK GENMASK(6, 0) > + > +/* ADMV1014_REG_IF_AMP Map */ > +#define ADMV1014_IF_AMP_COARSE_GAIN_I_MSK GENMASK(11, 8) > +#define ADMV1014_IF_AMP_FINE_GAIN_Q_MSK GENMASK(7, 4) > +#define ADMV1014_IF_AMP_FINE_GAIN_I_MSK GENMASK(3, 0) > + > +/* ADMV1014_REG_IF_AMP_BB_AMP Map */ > +#define ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK GENMASK(15, 12) > +#define ADMV1014_BB_AMP_OFFSET_Q_MSK GENMASK(9, 5) > +#define ADMV1014_BB_AMP_OFFSET_I_MSK GENMASK(4, 0) > + > +/* ADMV1014_REG_BB_AMP_AGC Map */ > +#define ADMV1014_BB_AMP_REF_GEN_MSK GENMASK(6, 3) > +#define ADMV1014_BB_AMP_GAIN_CTRL_MSK GENMASK(2, 1) > +#define ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK BIT(0) > + > +/* ADMV1014_REG_VVA_TEMP_COMP Map */ > +#define ADMV1014_VVA_TEMP_COMP_MSK GENMASK(15, 0) > + > +/* ADMV1014 Miscellaneous Defines */ > +#define ADMV1014_READ BIT(7) > +#define ADMV1014_REG_ADDR_READ_MSK GENMASK(6, 1) > +#define ADMV1014_REG_ADDR_WRITE_MSK GENMASK(22, 17) > +#define ADMV1014_REG_DATA_MSK GENMASK(16, 1) > + > +enum { > + ADMV1014_IQ_MODE, > + ADMV1014_IF_MODE > +}; > + > +enum { > + ADMV1014_SE_MODE_POS = 6, > + ADMV1014_SE_MODE_NEG = 9, > + ADMV1014_SE_MODE_DIFF = 12 > +}; > + > +enum { > + ADMV1014_GAIN_COARSE, > + ADMV1014_GAIN_FINE, > +}; > + > +static const int detector_table[] = {0, 1, 2, 4, 8, 16, 32, 64}; > + > +struct admv1014_state { > + struct spi_device *spi; > + struct clk *clkin; > + struct notifier_block nb; > + /* Protect against concurrent accesses to the device and to data*/ > + struct mutex lock; > + struct regulator *reg; > + unsigned int input_mode; > + unsigned int quad_se_mode; > + unsigned int p1db_comp; > + bool det_en; > + u8 data[3] ____cacheline_aligned; > +}; > + > +static const int mixer_vgate_table[] = {106, 107, 108, 110, 111, 112, 113, 114, 117, 118, 119, 120, 122, 123, 44, 45}; > + > +static int __admv1014_spi_read(struct admv1014_state *st, unsigned int reg, > + unsigned int *val) > +{ > + int ret; > + struct spi_transfer t = {0}; > + > + st->data[0] = ADMV1014_READ | FIELD_PREP(ADMV1014_REG_ADDR_READ_MSK, reg); > + st->data[1] = 0x0; > + st->data[2] = 0x0; > + > + t.rx_buf = &st->data[0]; > + t.tx_buf = &st->data[0]; > + t.len = 3; > + > + ret = spi_sync_transfer(st->spi, &t, 1); > + if (ret) > + return ret; > + > + *val = FIELD_GET(ADMV1014_REG_DATA_MSK, get_unaligned_be24(&st->data[0])); This looks like it would be easy enough to support with regmap and that might reduce the number of custom read/write functions + let you use caching etc for free. > + > + return ret; > +} > + > +static int admv1014_spi_read(struct admv1014_state *st, unsigned int reg, > + unsigned int *val) > +{ > + int ret; > + > + mutex_lock(&st->lock); > + ret = __admv1014_spi_read(st, reg, val); > + mutex_unlock(&st->lock); > + > + return ret; > +} > + > +static int __admv1014_spi_write(struct admv1014_state *st, > + unsigned int reg, > + unsigned int val) > +{ > + put_unaligned_be24(FIELD_PREP(ADMV1014_REG_DATA_MSK, val) | > + FIELD_PREP(ADMV1014_REG_ADDR_WRITE_MSK, reg), &st->data[0]); > + > + return spi_write(st->spi, &st->data[0], 3); > +} > + > +static int admv1014_spi_write(struct admv1014_state *st, unsigned int reg, > + unsigned int val) > +{ > + int ret; > + > + mutex_lock(&st->lock); > + ret = __admv1014_spi_write(st, reg, val); > + mutex_unlock(&st->lock); > + > + return ret; > +} > + > +static int __admv1014_spi_update_bits(struct admv1014_state *st, unsigned int reg, > + unsigned int mask, unsigned int val) > +{ > + int ret; > + unsigned int data, temp; > + > + ret = __admv1014_spi_read(st, reg, &data); > + if (ret) > + return ret; > + > + temp = (data & ~mask) | (val & mask); > + > + return __admv1014_spi_write(st, reg, temp); > +} > + > +static int admv1014_spi_update_bits(struct admv1014_state *st, unsigned int reg, > + unsigned int mask, unsigned int val) > +{ > + int ret; > + > + mutex_lock(&st->lock); > + ret = __admv1014_spi_update_bits(st, reg, mask, val); > + mutex_unlock(&st->lock); > + > + return ret; > +} > + > +static int admv1014_update_quad_filters(struct admv1014_state *st) > +{ > + unsigned int filt_raw; > + u64 rate = clk_get_rate(st->clkin); > + > + if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ)) > + filt_raw = 15; > + else if (rate >= (5400 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ)) > + filt_raw = 10; > + else if (rate >= (6600 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ)) > + filt_raw = 5; > + else > + filt_raw = 0; > + > + return __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD, > + ADMV1014_QUAD_FILTERS_MSK, > + FIELD_PREP(ADMV1014_QUAD_FILTERS_MSK, filt_raw)); > +} > + > +static int admv1014_update_vcm_settings(struct admv1014_state *st) > +{ > + unsigned int i, vcm_mv, vcm_comp, bb_sw_high_low_cm; > + int ret; > + > + vcm_mv = regulator_get_voltage(st->reg) / 1000; > + for (i = 0; i < ARRAY_SIZE(mixer_vgate_table); i++) { > + vcm_comp = 1050 + (i * 50) + (i / 8 * 50); > + if (vcm_mv == vcm_comp) { Where you can invert a condition to reduce indenting, do so. if (vcm_mv != vcm_comp) continue; ret = > + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_MIXER, > + ADMV1014_MIXER_VGATE_MSK, > + FIELD_PREP(ADMV1014_MIXER_VGATE_MSK, > + mixer_vgate_table[i])); > + if (ret) > + return ret; > + > + bb_sw_high_low_cm = ~(i / 8); > + > + return __admv1014_spi_update_bits(st, ADMV1014_REG_BB_AMP_AGC, > + ADMV1014_BB_AMP_REF_GEN_MSK | > + ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK, > + FIELD_PREP(ADMV1014_BB_AMP_REF_GEN_MSK, i) | > + FIELD_PREP(ADMV1014_BB_SWITCH_HIGH_LOW_CM_MSK, bb_sw_high_low_cm)); Local varaibles to shorten these lines are a must. > + } > + } > + > + return -EINVAL; > +} > + > +static int admv1014_read_raw(struct iio_dev *indio_dev, > + struct iio_chan_spec const *chan, > + int *val, int *val2, long info) > +{ > + struct admv1014_state *st = iio_priv(indio_dev); > + unsigned int data; > + int ret; > + > + switch (info) { > + case IIO_CHAN_INFO_OFFSET: > + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP_BB_AMP, &data); > + if (ret) > + return ret; > + > + if (chan->channel2 == IIO_MOD_I) > + *val = FIELD_GET(ADMV1014_BB_AMP_OFFSET_I_MSK, data); > + else > + *val = FIELD_GET(ADMV1014_BB_AMP_OFFSET_Q_MSK, data); > + > + return IIO_VAL_INT; > + case IIO_CHAN_INFO_PHASE: > + ret = admv1014_spi_read(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, &data); > + if (ret) > + return ret; > + > + if (chan->channel2 == IIO_MOD_I) > + *val = FIELD_GET(ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, data); > + else > + *val = FIELD_GET(ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, data); > + > + return IIO_VAL_INT; > + case IIO_CHAN_INFO_SCALE: > + ret = admv1014_spi_read(st, ADMV1014_REG_MIXER, &data); > + if (ret) > + return ret; > + > + *val = FIELD_GET(ADMV1014_DET_PROG_MSK, data); > + return IIO_VAL_INT; > + case IIO_CHAN_INFO_HARDWAREGAIN: > + ret = admv1014_spi_read(st, ADMV1014_REG_BB_AMP_AGC, &data); > + if (ret) > + return ret; > + > + *val = FIELD_GET(ADMV1014_BB_AMP_GAIN_CTRL_MSK, data); > + return IIO_VAL_INT; > + default: > + return -EINVAL; > + } > +} > + > +static int admv1014_write_raw(struct iio_dev *indio_dev, > + struct iio_chan_spec const *chan, > + int val, int val2, long info) > +{ > + struct admv1014_state *st = iio_priv(indio_dev); > + > + switch (info) { > + case IIO_CHAN_INFO_OFFSET: > + if (chan->channel2 == IIO_MOD_I) > + return admv1014_spi_update_bits(st, ADMV1014_REG_IF_AMP_BB_AMP, > + ADMV1014_BB_AMP_OFFSET_I_MSK, > + FIELD_PREP(ADMV1014_BB_AMP_OFFSET_I_MSK, val)); > + else > + return admv1014_spi_update_bits(st, ADMV1014_REG_IF_AMP_BB_AMP, > + ADMV1014_BB_AMP_OFFSET_Q_MSK, > + FIELD_PREP(ADMV1014_BB_AMP_OFFSET_Q_MSK, val)); > + case IIO_CHAN_INFO_PHASE: > + if (chan->channel2 == IIO_MOD_I) > + return admv1014_spi_update_bits(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, > + ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, > + FIELD_PREP(ADMV1014_LOAMP_PH_ADJ_I_FINE_MSK, val)); Lines too long. I'd suggest using some local variables. > + else > + return admv1014_spi_update_bits(st, ADMV1014_REG_LO_AMP_PHASE_ADJUST1, > + ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, > + FIELD_PREP(ADMV1014_LOAMP_PH_ADJ_Q_FINE_MSK, val)); > + case IIO_CHAN_INFO_SCALE: > + return admv1014_spi_update_bits(st, ADMV1014_REG_MIXER, > + ADMV1014_DET_PROG_MSK, > + FIELD_PREP(ADMV1014_DET_PROG_MSK, val)); > + case IIO_CHAN_INFO_HARDWAREGAIN: > + return admv1014_spi_update_bits(st, ADMV1014_REG_BB_AMP_AGC, > + ADMV1014_BB_AMP_GAIN_CTRL_MSK, > + FIELD_PREP(ADMV1014_BB_AMP_GAIN_CTRL_MSK, val)); > + default: > + return -EINVAL; > + } > +} > + > +static ssize_t admv1014_read(struct iio_dev *indio_dev, > + uintptr_t private, > + const struct iio_chan_spec *chan, > + char *buf) > +{ > + struct admv1014_state *st = iio_priv(indio_dev); > + unsigned int data; > + int ret; > + > + switch ((u32)private) { > + case ADMV1014_GAIN_COARSE: > + if (chan->channel2 == IIO_MOD_I) { > + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP, &data); > + if (ret) > + return ret; > + > + data = FIELD_GET(ADMV1014_IF_AMP_COARSE_GAIN_I_MSK, data); > + } else { > + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP_BB_AMP, &data); > + if (ret) > + return ret; > + > + data = FIELD_GET(ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK, data); > + } > + break; > + case ADMV1014_GAIN_FINE: > + ret = admv1014_spi_read(st, ADMV1014_REG_IF_AMP, &data); > + if (ret) > + return ret; > + > + if (chan->channel2 == IIO_MOD_I) > + data = FIELD_GET(ADMV1014_IF_AMP_FINE_GAIN_I_MSK, data); > + else > + data = FIELD_GET(ADMV1014_IF_AMP_FINE_GAIN_Q_MSK, data); > + break; > + default: > + return -EINVAL; > + } > + > + return sysfs_emit(buf, "%u\n", data); > +} > + > +static ssize_t admv1014_write(struct iio_dev *indio_dev, > + uintptr_t private, > + const struct iio_chan_spec *chan, > + const char *buf, size_t len) > +{ > + struct admv1014_state *st = iio_priv(indio_dev); > + unsigned int data, addr, msk; > + int ret; > + > + ret = kstrtou32(buf, 10, &data); > + if (ret) > + return ret; > + > + switch ((u32)private) { > + case ADMV1014_GAIN_COARSE: > + if (chan->channel2 == IIO_MOD_I) { > + addr = ADMV1014_REG_IF_AMP; > + msk = ADMV1014_IF_AMP_COARSE_GAIN_I_MSK; > + data = FIELD_PREP(ADMV1014_IF_AMP_COARSE_GAIN_I_MSK, data); > + } else { > + addr = ADMV1014_REG_IF_AMP_BB_AMP; > + msk = ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK; > + data = FIELD_PREP(ADMV1014_IF_AMP_COARSE_GAIN_Q_MSK, data); > + } > + break; > + case ADMV1014_GAIN_FINE: > + addr = ADMV1014_REG_IF_AMP; > + > + if (chan->channel2 == IIO_MOD_I) { > + msk = ADMV1014_IF_AMP_FINE_GAIN_I_MSK; > + data = FIELD_PREP(ADMV1014_IF_AMP_FINE_GAIN_I_MSK, data); > + } else { > + msk = ADMV1014_IF_AMP_FINE_GAIN_Q_MSK; > + data = FIELD_PREP(ADMV1014_IF_AMP_FINE_GAIN_Q_MSK, data); > + } > + break; > + default: > + return -EINVAL; > + } > + > + ret = admv1014_spi_update_bits(st, addr, msk, data); > + > + return ret ? ret : len; > +} > + > +static int admv1014_read_avail(struct iio_dev *indio_dev, > + struct iio_chan_spec const *chan, > + const int **vals, int *type, int *length, > + long info) > +{ > + switch (info) { > + case IIO_CHAN_INFO_SCALE: > + *vals = detector_table; > + *type = IIO_VAL_INT; > + *length = ARRAY_SIZE(detector_table); > + > + return IIO_AVAIL_LIST; > + default: > + return -EINVAL; > + } > +} > + > +static int admv1014_reg_access(struct iio_dev *indio_dev, > + unsigned int reg, > + unsigned int write_val, > + unsigned int *read_val) > +{ > + struct admv1014_state *st = iio_priv(indio_dev); > + int ret; > + > + if (read_val) > + ret = admv1014_spi_read(st, reg, read_val); return... > + else > + ret = admv1014_spi_write(st, reg, write_val); return... > + > + return ret; > +} > + > +static const struct iio_info admv1014_info = { > + .read_raw = admv1014_read_raw, > + .write_raw = admv1014_write_raw, > + .read_avail = &admv1014_read_avail, > + .debugfs_reg_access = &admv1014_reg_access, > +}; > + > +static int admv1014_freq_change(struct notifier_block *nb, unsigned long action, void *data) > +{ > + struct admv1014_state *st = container_of(nb, struct admv1014_state, nb); > + int ret; > + > + if (action == POST_RATE_CHANGE) { > + mutex_lock(&st->lock); > + ret = notifier_from_errno(admv1014_update_quad_filters(st)); > + mutex_unlock(&st->lock); > + return ret; > + } > + > + return NOTIFY_OK; > +} > + > +#define _ADMV1014_EXT_INFO(_name, _shared, _ident) { \ > + .name = _name, \ > + .read = admv1014_read, \ > + .write = admv1014_write, \ > + .private = _ident, \ > + .shared = _shared, \ > +} > + > +static const struct iio_chan_spec_ext_info admv1014_ext_info[] = { > + _ADMV1014_EXT_INFO("gain_coarse", IIO_SEPARATE, ADMV1014_GAIN_COARSE), > + _ADMV1014_EXT_INFO("gain_fine", IIO_SEPARATE, ADMV1014_GAIN_FINE), > + { }, > +}; > + > +#define ADMV1014_CHAN(_channel, rf_comp) { \ > + .type = IIO_ALTVOLTAGE, \ > + .modified = 1, \ > + .output = 0, \ > + .indexed = 1, \ > + .channel2 = IIO_MOD_##rf_comp, \ > + .channel = _channel, \ > + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | \ > + BIT(IIO_CHAN_INFO_OFFSET), \ > + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_HARDWAREGAIN) \ Some of this ABI is non obvious enough that I'd like to see the whole thing in the patch description with some info on what they are actually being used for alongside. > + } > + > +#define ADMV1014_CHAN_GAIN(_channel, rf_comp, _admv1014_ext_info) { \ > + .type = IIO_ALTVOLTAGE, \ > + .modified = 1, \ > + .output = 0, \ > + .indexed = 1, \ > + .channel2 = IIO_MOD_##rf_comp, \ > + .channel = _channel, \ > + .ext_info = _admv1014_ext_info \ > + } > + > +#define ADMV1014_CHAN_DETECTOR(_channel) { \ If only one use, probably better to just put this inline as it'll be slightly more readable when not a macro. > + .type = IIO_POWER, \ > + .modified = 1, \ > + .output = 0, \ > + .indexed = 1, \ > + .channel = _channel, \ > + .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \ > + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) \ > + } > + > +static const struct iio_chan_spec admv1014_channels[] = { > + ADMV1014_CHAN(0, I), > + ADMV1014_CHAN(0, Q), > + ADMV1014_CHAN_GAIN(0, I, admv1014_ext_info), > + ADMV1014_CHAN_GAIN(0, Q, admv1014_ext_info), > + ADMV1014_CHAN_DETECTOR(0) > +}; > + > +static int admv1014_init(struct admv1014_state *st) > +{ > + int ret; > + unsigned int chip_id, enable_reg, enable_reg_msk; > + struct spi_device *spi = st->spi; > + > + /* Perform a software reset */ > + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL, > + ADMV1014_SPI_SOFT_RESET_MSK, > + FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 1)); > + if (ret) { > + dev_err(&spi->dev, "ADMV1014 SPI software reset failed.\n"); > + return ret; > + } > + > + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_SPI_CONTROL, > + ADMV1014_SPI_SOFT_RESET_MSK, > + FIELD_PREP(ADMV1014_SPI_SOFT_RESET_MSK, 0)); > + if (ret) { > + dev_err(&spi->dev, "ADMV1014 SPI software reset disable failed.\n"); > + return ret; > + } > + > + ret = admv1014_spi_write(st, ADMV1014_REG_VVA_TEMP_COMP, 0x727C); > + if (ret) { > + dev_err(&spi->dev, "Writing default Temperature Compensation value failed.\n"); > + return ret; > + } > + > + ret = admv1014_spi_read(st, ADMV1014_REG_SPI_CONTROL, &chip_id); > + if (ret) > + return ret; > + > + chip_id = (chip_id & ADMV1014_CHIP_ID_MSK) >> 4; > + if (chip_id != ADMV1014_CHIP_ID) { > + dev_err(&spi->dev, "Invalid Chip ID.\n"); > + return -EINVAL; > + } > + > + ret = __admv1014_spi_update_bits(st, ADMV1014_REG_QUAD, > + ADMV1014_QUAD_SE_MODE_MSK, > + FIELD_PREP(ADMV1014_QUAD_SE_MODE_MSK, > + st->quad_se_mode)); > + if (ret) { > + dev_err(&spi->dev, "Writing Quad SE Mode failed.\n"); > + return ret; > + } > + > + ret = admv1014_update_quad_filters(st); > + if (ret) { > + dev_err(&spi->dev, "Update Quad Filters failed.\n"); > + return ret; > + } > + > + ret = admv1014_update_vcm_settings(st); > + if (ret) { > + dev_err(&spi->dev, "Update VCM Settings failed.\n"); > + return ret; > + } > + > + enable_reg_msk = ADMV1014_P1DB_COMPENSATION_MSK | > + ADMV1014_IF_AMP_PD_MSK | > + ADMV1014_BB_AMP_PD_MSK | > + ADMV1014_DET_EN_MSK; > + > + enable_reg = FIELD_PREP(ADMV1014_P1DB_COMPENSATION_MSK, st->p1db_comp) | > + FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, !(st->input_mode)) | > + FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, st->input_mode) | > + FIELD_PREP(ADMV1014_DET_EN_MSK, st->det_en); > + > + return __admv1014_spi_update_bits(st, ADMV1014_REG_ENABLE, enable_reg_msk, enable_reg); > +} > + > +static void admv1014_clk_disable(void *data) > +{ > + clk_disable_unprepare(data); > +} > + > +static void admv1014_reg_disable(void *data) > +{ > + regulator_disable(data); > +} > + > +static void admv1014_powerdown(void *data) > +{ > + unsigned int enable_reg, enable_reg_msk; > + > + /* Disable all components in the Enable Register */ > + enable_reg_msk = ADMV1014_IBIAS_PD_MSK | > + ADMV1014_IF_AMP_PD_MSK | > + ADMV1014_QUAD_BG_PD_MSK | > + ADMV1014_BB_AMP_PD_MSK | > + ADMV1014_QUAD_IBIAS_PD_MSK | > + ADMV1014_BG_PD_MSK; > + > + enable_reg = FIELD_PREP(ADMV1014_IBIAS_PD_MSK, 1) | > + FIELD_PREP(ADMV1014_IF_AMP_PD_MSK, 1) | > + FIELD_PREP(ADMV1014_QUAD_BG_PD_MSK, 1) | > + FIELD_PREP(ADMV1014_BB_AMP_PD_MSK, 1) | > + FIELD_PREP(ADMV1014_QUAD_IBIAS_PD_MSK, 1) | > + FIELD_PREP(ADMV1014_BG_PD_MSK, 1); > + > + admv1014_spi_update_bits(data, ADMV1014_REG_ENABLE, enable_reg_msk, enable_reg); Where it doesn't hurt, keep lines under 80 chars. > +} > + > +static int admv1014_properties_parse(struct admv1014_state *st) > +{ > + int ret; > + const char *str; > + struct spi_device *spi = st->spi; > + > + st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable"); > + > + st->p1db_comp = device_property_read_bool(&spi->dev, "adi,p1db-comp-enable"); > + if (st->p1db_comp) > + st->p1db_comp = 3; Why? I'd just make this a bool and then do any necessary conversion to 3 where it is used. > + > + ret = device_property_read_string(&spi->dev, "adi,input-mode", &str); > + if (ret) > + st->input_mode = ADMV1014_IQ_MODE; Be lazy :) str = "iq"; device_property_read_string(&spi->dev, "adi,input-mode", &str); as it should not change str unless it succeeds thus we can set a default. Note the binding should have a default: entry for this. > + > + if (!strcmp(str, "iq")) > + st->input_mode = ADMV1014_IQ_MODE; > + else if (!strcmp(str, "if")) > + st->input_mode = ADMV1014_IF_MODE; > + else > + return -EINVAL; > + > + ret = device_property_read_string(&spi->dev, "adi,quad-se-mode", &str); > + if (ret) > + st->quad_se_mode = ADMV1014_SE_MODE_DIFF; Same suggestion as above to set a default value. > + > + if (!strcmp(str, "diff")) > + st->quad_se_mode = ADMV1014_SE_MODE_DIFF; > + else if (!strcmp(str, "se-pos")) > + st->quad_se_mode = ADMV1014_SE_MODE_POS; > + else if (!strcmp(str, "se-neg")) > + st->quad_se_mode = ADMV1014_SE_MODE_NEG; > + else > + return -EINVAL; > + > + st->reg = devm_regulator_get(&spi->dev, "vcm"); > + if (IS_ERR(st->reg)) > + return dev_err_probe(&spi->dev, PTR_ERR(st->reg), > + "failed to get the common-mode voltage\n"); > + > + st->clkin = devm_clk_get(&spi->dev, "lo_in"); > + if (IS_ERR(st->clkin)) > + return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), > + "failed to get the LO input clock\n"); > + > + return 0; > +} > + > +static int admv1014_probe(struct spi_device *spi) > +{ > + struct iio_dev *indio_dev; > + struct admv1014_state *st; > + int ret; > + > + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); > + if (!indio_dev) > + return -ENOMEM; > + > + st = iio_priv(indio_dev); > + > + indio_dev->info = &admv1014_info; > + indio_dev->name = "admv1014"; > + indio_dev->channels = admv1014_channels; > + indio_dev->num_channels = ARRAY_SIZE(admv1014_channels); > + > + st->spi = spi; > + > + ret = admv1014_properties_parse(st); > + if (ret) > + return ret; > + > + ret = regulator_enable(st->reg); > + if (ret) { > + dev_err(&spi->dev, "Failed to enable specified Common-Mode Voltage!\n"); > + return ret; > + } > + > + ret = devm_add_action_or_reset(&spi->dev, admv1014_reg_disable, st->reg); > + if (ret) > + return ret; > + > + ret = clk_prepare_enable(st->clkin); > + if (ret) > + return ret; > + > + ret = devm_add_action_or_reset(&spi->dev, admv1014_clk_disable, st->clkin); > + if (ret) > + return ret; > + > + st->nb.notifier_call = admv1014_freq_change; > + ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb); > + if (ret) > + return ret; > + > + mutex_init(&st->lock); > + > + ret = admv1014_init(st); > + if (ret) > + return ret; > + > + ret = devm_add_action_or_reset(&spi->dev, admv1014_powerdown, st); > + if (ret) > + return ret; > + > + return devm_iio_device_register(&spi->dev, indio_dev); > +} > + > +static const struct spi_device_id admv1014_id[] = { > + { "admv1014", 0 }, > + {} > +}; > +MODULE_DEVICE_TABLE(spi, admv1014_id); > + > +static const struct of_device_id admv1014_of_match[] = { > + { .compatible = "adi,admv1014" }, > + {}, No comma after the 'null' terminator. > +}; > +MODULE_DEVICE_TABLE(of, admv1014_of_match); > + > +static struct spi_driver admv1014_driver = { > + .driver = { > + .name = "admv1014", > + .of_match_table = admv1014_of_match, > + }, > + .probe = admv1014_probe, > + .id_table = admv1014_id, > +}; > +module_spi_driver(admv1014_driver); > + > +MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com"); > +MODULE_DESCRIPTION("Analog Devices ADMV1014"); > +MODULE_LICENSE("GPL v2"); ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/3] dt-bindings:iio:frequency: add admv1014 doc 2022-01-03 9:21 [PATCH 0/3] Antoniu Miclaus 2022-01-03 9:21 ` [PATCH 1/3] iio:frequency:admv1014: add support for ADMV1014 Antoniu Miclaus @ 2022-01-03 9:22 ` Antoniu Miclaus 2022-01-09 17:46 ` Jonathan Cameron 2022-01-03 9:22 ` [PATCH 3/3] Documentation:ABI:testing:admv1014: add ABI docs Antoniu Miclaus 2 siblings, 1 reply; 17+ messages in thread From: Antoniu Miclaus @ 2022-01-03 9:22 UTC (permalink / raw) To: jic23, robh+dt, linux-iio, devicetree, linux-kernel; +Cc: Antoniu Miclaus Add device tree bindings for the ADMV1014 Upconverter. Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> --- .../bindings/iio/frequency/adi,admv1014.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml new file mode 100644 index 000000000000..a3e5e61c8ade --- /dev/null +++ b/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,admv1014.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADMV1014 Microwave Downconverter + +maintainers: + - Antoniu Miclaus <antoniu.miclaus@analog.com> + +description: | + Wideband, microwave downconverter optimized for point to point microwave + radio designs operating in the 24 GHz to 44 GHz frequency range. + + https://www.analog.com/en/products/admv1014.html + +properties: + compatible: + enum: + - adi,admv1014 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 1000000 + + clocks: + description: + Definition of the external clock. + minItems: 1 + + clock-names: + items: + - const: lo_in + + vcm-supply: + description: + Analog voltage regulator. + + adi,input-mode: + description: + Select the input mode. + iq - in-phase quadrature (I/Q) input + if - complex intermediate frequency (IF) input + enum: [iq, if] + + adi,detector-enable: + description: + Digital Rx Detector Enable. The Square Law Detector output is + available at output pin VDET. + type: boolean + + adi,p1db-comp-enable: + description: + Turn on bits to optimize P1dB. + type: boolean + + adi,quad-se-mode: + description: + Switch the LO path from differential to single-ended operation. + se-neg - Single-Ended Mode, Negative Side Disabled. + se-pos - Single-Ended Mode, Positive Side Disabled. + diff - Differential Mode. + enum: [se-neg, se-pos, diff] + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - vcm-supply + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + admv1014@0{ + compatible = "adi,admv1014"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&admv1014_lo>; + clock-names = "lo_in"; + vcm-supply = <&vcm>; + adi,quad-se-mode = "diff"; + adi,detector-enable; + adi,p1db-comp-enable; + }; + }; +... -- 2.34.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 2/3] dt-bindings:iio:frequency: add admv1014 doc 2022-01-03 9:22 ` [PATCH 2/3] dt-bindings:iio:frequency: add admv1014 doc Antoniu Miclaus @ 2022-01-09 17:46 ` Jonathan Cameron 0 siblings, 0 replies; 17+ messages in thread From: Jonathan Cameron @ 2022-01-09 17:46 UTC (permalink / raw) To: Antoniu Miclaus; +Cc: robh+dt, linux-iio, devicetree, linux-kernel On Mon, 3 Jan 2022 11:22:00 +0200 Antoniu Miclaus <antoniu.miclaus@analog.com> wrote: binding rather than doc. Yaml is code a well as documentation afterall. > Add device tree bindings for the ADMV1014 Upconverter. > > Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> > --- > .../bindings/iio/frequency/adi,admv1014.yaml | 97 +++++++++++++++++++ > 1 file changed, 97 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml > > diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml > new file mode 100644 > index 000000000000..a3e5e61c8ade > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml > @@ -0,0 +1,97 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/frequency/adi,admv1014.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ADMV1014 Microwave Downconverter > + > +maintainers: > + - Antoniu Miclaus <antoniu.miclaus@analog.com> > + > +description: | > + Wideband, microwave downconverter optimized for point to point microwave > + radio designs operating in the 24 GHz to 44 GHz frequency range. > + > + https://www.analog.com/en/products/admv1014.html > + > +properties: > + compatible: > + enum: > + - adi,admv1014 > + > + reg: > + maxItems: 1 > + > + spi-max-frequency: > + maximum: 1000000 > + > + clocks: > + description: > + Definition of the external clock. Not a particularly helpful way of describing it. This is the local oscillator input. I'd put the description in clock-names rather than here as then it's obvious what lo_in means. > + minItems: 1 > + > + clock-names: > + items: > + - const: lo_in > + > + vcm-supply: > + description: > + Analog voltage regulator. There seem to be a whole load of other VCC_X supplies from the datasheet. They should all be here. > + > + adi,input-mode: > + description: > + Select the input mode. > + iq - in-phase quadrature (I/Q) input > + if - complex intermediate frequency (IF) input > + enum: [iq, if] > + > + adi,detector-enable: > + description: > + Digital Rx Detector Enable. The Square Law Detector output is > + available at output pin VDET. > + type: boolean > + > + adi,p1db-comp-enable: > + description: > + Turn on bits to optimize P1dB. Expand comp to compensation perhaps as not a totally clear abbreviation. > + type: boolean > + > + adi,quad-se-mode: > + description: > + Switch the LO path from differential to single-ended operation. > + se-neg - Single-Ended Mode, Negative Side Disabled. > + se-pos - Single-Ended Mode, Positive Side Disabled. > + diff - Differential Mode. > + enum: [se-neg, se-pos, diff] > + > + '#clock-cells': > + const: 0 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - vcm-supply > + > +additionalProperties: false > + > +examples: > + - | > + spi { > + #address-cells = <1>; > + #size-cells = <0>; > + admv1014@0{ > + compatible = "adi,admv1014"; > + reg = <0>; > + spi-max-frequency = <1000000>; > + clocks = <&admv1014_lo>; > + clock-names = "lo_in"; > + vcm-supply = <&vcm>; > + adi,quad-se-mode = "diff"; > + adi,detector-enable; > + adi,p1db-comp-enable; > + }; > + }; > +... ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/3] Documentation:ABI:testing:admv1014: add ABI docs 2022-01-03 9:21 [PATCH 0/3] Antoniu Miclaus 2022-01-03 9:21 ` [PATCH 1/3] iio:frequency:admv1014: add support for ADMV1014 Antoniu Miclaus 2022-01-03 9:22 ` [PATCH 2/3] dt-bindings:iio:frequency: add admv1014 doc Antoniu Miclaus @ 2022-01-03 9:22 ` Antoniu Miclaus 2022-01-09 17:38 ` Jonathan Cameron 2 siblings, 1 reply; 17+ messages in thread From: Antoniu Miclaus @ 2022-01-03 9:22 UTC (permalink / raw) To: jic23, robh+dt, linux-iio, devicetree, linux-kernel; +Cc: Antoniu Miclaus Add documentation for the use of the Digital Attenuator gain. Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> --- .../testing/sysfs-bus-iio-frequency-admv1014 | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014 diff --git a/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014 b/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014 new file mode 100644 index 000000000000..385bf5b4b399 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014 @@ -0,0 +1,23 @@ +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_gain_coarse +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Read/write value for the digital attenuator gain (IF_I) with coarse steps. + +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_gain_coarse +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Read/write value for the digital attenuator gain (IF_Q) with coarse steps. + +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_gain_fine +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Read/write value for the digital attenuator gain (IF_I) with fine steps. + +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_gain_fine +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Read/write value for the digital attenuator gain (IF_Q) with fine steps. -- 2.34.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 3/3] Documentation:ABI:testing:admv1014: add ABI docs 2022-01-03 9:22 ` [PATCH 3/3] Documentation:ABI:testing:admv1014: add ABI docs Antoniu Miclaus @ 2022-01-09 17:38 ` Jonathan Cameron 0 siblings, 0 replies; 17+ messages in thread From: Jonathan Cameron @ 2022-01-09 17:38 UTC (permalink / raw) To: Antoniu Miclaus; +Cc: robh+dt, linux-iio, devicetree, linux-kernel On Mon, 3 Jan 2022 11:22:01 +0200 Antoniu Miclaus <antoniu.miclaus@analog.com> wrote: > Add documentation for the use of the Digital Attenuator gain. > > Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> > --- > .../testing/sysfs-bus-iio-frequency-admv1014 | 23 +++++++++++++++++++ > 1 file changed, 23 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014 > > diff --git a/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014 b/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014 > new file mode 100644 > index 000000000000..385bf5b4b399 > --- /dev/null > +++ b/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014 > @@ -0,0 +1,23 @@ > +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_gain_coarse > +KernelVersion: > +Contact: linux-iio@vger.kernel.org > +Description: > + Read/write value for the digital attenuator gain (IF_I) with coarse steps. > + > +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_gain_coarse > +KernelVersion: > +Contact: linux-iio@vger.kernel.org > +Description: > + Read/write value for the digital attenuator gain (IF_Q) with coarse steps. > + > +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_gain_fine > +KernelVersion: > +Contact: linux-iio@vger.kernel.org > +Description: > + Read/write value for the digital attenuator gain (IF_I) with fine steps. > + > +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_gain_fine > +KernelVersion: > +Contact: linux-iio@vger.kernel.org > +Description: > + Read/write value for the digital attenuator gain (IF_Q) with fine steps. I guess it's horribly optimistic to wonder if these can be expressed as a single gain? I'm going to guess no as they are basically 'twiddle' functions with frequency dependent gain characteristics. My gut feeling is these are meant for for calibration tweaking so is calibbscale as currently defined applicable? " Hardware applied calibration scale factor (assumed to fix production inaccuracies). If shared across all channels, <type>_calibscale is used. " you'd still need the fine and coarse postfix unfortunately. A nice thing about calibscale is it's defined unit free as it's normally a tweak on an input amplifier or similar. Jonathan ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/3] @ 2020-06-05 18:46 Matthias Kaehlcke 0 siblings, 0 replies; 17+ messages in thread From: Matthias Kaehlcke @ 2020-06-05 18:46 UTC (permalink / raw) To: Marcel Holtmann, Johan Hedberg Cc: linux-bluetooth, Rocky Liao, Zijun Hu, linux-kernel, Balakrishna Godavarthi, Abhishek Pandit-Subedi, Claire Chang, Matthias Kaehlcke This series includes a fix for a possible race in qca_suspend() and some minor refactoring of the same function. Matthias Kaehlcke (3): Bluetooth: hci_qca: Only remove TX clock vote after TX is completed Bluetooth: hci_qca: Skip serdev wait when no transfer is pending Bluetooth: hci_qca: Refactor error handling in qca_suspend() drivers/bluetooth/hci_qca.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) -- 2.27.0.278.ge193c7cf3a9-goog ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/3] @ 2020-04-27 8:21 Gareth Williams 2020-04-27 13:21 ` Gareth Williams 0 siblings, 1 reply; 17+ messages in thread From: Gareth Williams @ 2020-04-27 8:21 UTC (permalink / raw) To: Maarten Lankhorst, Maxime Ripard, Sean Paul, David Airlie, Daniel Vetter, Rob Herring, Mark Rutland, Hans Verkuil, Icenowy Zheng, Mauro Carvalho Chehab, Vivek Unune, Stephen Rothwell, Thierry Reding, Sam Ravnborg Cc: Gareth Williams, Phil Edworthy, dri-devel, devicetree, linux-kernel This series adds DRM support for the Digital Blocks db9000 LCD controller with RZ/N1 specific changes and updates simple-panel to include the associated panel. As this has not previously been documented, also include a yaml file to provide this. Gareth Williams (3): drm/db9000: Add Digital Blocks DB9000 LCD Controller drm/db9000: Add bindings documentation for LCD controller drm/panel: simple: Add Newhaven ATXL#-CTP panel .../devicetree/bindings/display/db9000,du.yaml | 87 ++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/digital-blocks/Kconfig | 13 + drivers/gpu/drm/digital-blocks/Makefile | 3 + drivers/gpu/drm/digital-blocks/db9000-du.c | 953 +++++++++++++++++++++ drivers/gpu/drm/digital-blocks/db9000-du.h | 192 +++++ drivers/gpu/drm/panel/panel-simple.c | 27 + 9 files changed, 1280 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/db9000,du.yaml create mode 100644 drivers/gpu/drm/digital-blocks/Kconfig create mode 100644 drivers/gpu/drm/digital-blocks/Makefile create mode 100644 drivers/gpu/drm/digital-blocks/db9000-du.c create mode 100644 drivers/gpu/drm/digital-blocks/db9000-du.h -- 2.7.4 ^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH 0/3] 2020-04-27 8:21 Gareth Williams @ 2020-04-27 13:21 ` Gareth Williams 0 siblings, 0 replies; 17+ messages in thread From: Gareth Williams @ 2020-04-27 13:21 UTC (permalink / raw) To: Gareth Williams, Maarten Lankhorst, Maxime Ripard, Sean Paul, David Airlie, Daniel Vetter, Rob Herring, Mark Rutland, Hans Verkuil, Icenowy Zheng, Mauro Carvalho Chehab, Vivek Unune, Stephen Rothwell, Thierry Reding, Sam Ravnborg Cc: Phil Edworthy, Sam Ravnborg, dri-devel, devicetree, linux-kernel Hi All, I noticed some API changes that were not present when I first wrote this driver. This will need correcting so I will send out a second version and respond to Sam Ravnborg's feedback at the same time. I recommend waiting for that version before reviewing as this will not function on Linux-next otherwise. Gareth On Mon, Apr 27, 2020 at 09:21:49AM +0100, Gareth Williams wrote: > > This series adds DRM support for the Digital Blocks db9000 LCD controller with > RZ/N1 specific changes and updates simple-panel to include the associated > panel. As this has not previously been documented, also include a yaml file to > provide this. > > Gareth Williams (3): > drm/db9000: Add Digital Blocks DB9000 LCD Controller > drm/db9000: Add bindings documentation for LCD controller > drm/panel: simple: Add Newhaven ATXL#-CTP panel > > .../devicetree/bindings/display/db9000,du.yaml | 87 ++ > .../devicetree/bindings/vendor-prefixes.yaml | 2 + > drivers/gpu/drm/Kconfig | 2 + > drivers/gpu/drm/Makefile | 1 + > drivers/gpu/drm/digital-blocks/Kconfig | 13 + > drivers/gpu/drm/digital-blocks/Makefile | 3 + > drivers/gpu/drm/digital-blocks/db9000-du.c | 953 > +++++++++++++++++++++ > drivers/gpu/drm/digital-blocks/db9000-du.h | 192 +++++ > drivers/gpu/drm/panel/panel-simple.c | 27 + > 9 files changed, 1280 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/db9000,du.yaml > create mode 100644 drivers/gpu/drm/digital-blocks/Kconfig > create mode 100644 drivers/gpu/drm/digital-blocks/Makefile > create mode 100644 drivers/gpu/drm/digital-blocks/db9000-du.c > create mode 100644 drivers/gpu/drm/digital-blocks/db9000-du.h > > -- > 2.7.4 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/3] @ 2013-09-21 13:05 Fan Rong 0 siblings, 0 replies; 17+ messages in thread From: Fan Rong @ 2013-09-21 13:05 UTC (permalink / raw) To: coosty, maxime.ripard, daniel.lezcano, linux, tglx, linux-arm-kernel, linux-kernel, mark.rutland, pawel.moll, rob.herring, linux-sunxi Cc: Fan Rong Fan Rong (3): Add smp support for Allwinner A20(sunxi 7i). Add cpuconfig nodes in dts for smp configure. Add arch count timer node in dts for Allwinner A20(sunxi 7i). arch/arm/boot/dts/sun7i-a20.dtsi | 19 ++- arch/arm/mach-sunxi/Makefile | 2 + arch/arm/mach-sunxi/headsmp.S | 12 ++ arch/arm/mach-sunxi/platform.h | 347 +++++++++++++++++++++++++++++++++++++++ arch/arm/mach-sunxi/platsmp.c | 100 +++++++++++ arch/arm/mach-sunxi/sunxi.c | 34 +++- 6 files changed, 511 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-sunxi/headsmp.S create mode 100644 arch/arm/mach-sunxi/platform.h create mode 100644 arch/arm/mach-sunxi/platsmp.c -- 1.8.1.2 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/3]
@ 2013-06-06 13:53 Jani Nikula
2013-06-06 13:59 ` Jani Nikula
2013-06-06 14:33 ` Daniel Vetter
0 siblings, 2 replies; 17+ messages in thread
From: Jani Nikula @ 2013-06-06 13:53 UTC (permalink / raw)
To: linux-kernel, intel-gfx, Andrew Morton, Greg Kroah-Hartman
Cc: chris, daniel, jani.nikula
Hi Greg, Andrew -
Patch 1 is for DMI, bugfixes in patches 2-3 for i915 and included for
completeness. After a tested-by they should be good for stable. I'll
leave it to Daniel to sort out how the last two get in.
BR,
Jani.
Chris Wilson (1):
drm/i915: Quirk away phantom LVDS on Intel's D510MO mainboard
Jani Nikula (2):
dmi: add support for exact DMI matches in addition to substring
matching
drm/i915: Quirk away phantom LVDS on Intel's D525MW mainboard
drivers/firmware/dmi_scan.c | 12 +++++++++---
drivers/gpu/drm/i915/intel_lvds.c | 16 ++++++++++++++++
include/linux/mod_devicetable.h | 6 ++++--
3 files changed, 29 insertions(+), 5 deletions(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 0/3] 2013-06-06 13:53 Jani Nikula @ 2013-06-06 13:59 ` Jani Nikula 2013-06-13 8:22 ` Daniel Vetter 2013-06-06 14:33 ` Daniel Vetter 1 sibling, 1 reply; 17+ messages in thread From: Jani Nikula @ 2013-06-06 13:59 UTC (permalink / raw) To: linux-kernel, intel-gfx, Andrew Morton, Greg Kroah-Hartman; +Cc: chris, daniel With Greg's address fixed. Please drop the old one from any replies. Sorry for the noise. On Thu, 06 Jun 2013, Jani Nikula <jani.nikula@intel.com> wrote: > Hi Greg, Andrew - > > Patch 1 is for DMI, bugfixes in patches 2-3 for i915 and included for > completeness. After a tested-by they should be good for stable. I'll > leave it to Daniel to sort out how the last two get in. > > BR, > Jani. > > Chris Wilson (1): > drm/i915: Quirk away phantom LVDS on Intel's D510MO mainboard > > Jani Nikula (2): > dmi: add support for exact DMI matches in addition to substring > matching > drm/i915: Quirk away phantom LVDS on Intel's D525MW mainboard > > drivers/firmware/dmi_scan.c | 12 +++++++++--- > drivers/gpu/drm/i915/intel_lvds.c | 16 ++++++++++++++++ > include/linux/mod_devicetable.h | 6 ++++-- > 3 files changed, 29 insertions(+), 5 deletions(-) > > -- > 1.7.9.5 > -- Jani Nikula, Intel Open Source Technology Center ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/3] 2013-06-06 13:59 ` Jani Nikula @ 2013-06-13 8:22 ` Daniel Vetter 2013-06-14 16:23 ` Greg Kroah-Hartman 0 siblings, 1 reply; 17+ messages in thread From: Daniel Vetter @ 2013-06-13 8:22 UTC (permalink / raw) To: Jani Nikula Cc: linux-kernel, intel-gfx, Andrew Morton, Greg Kroah-Hartman, chris, daniel On Thu, Jun 06, 2013 at 04:59:26PM +0300, Jani Nikula wrote: > > With Greg's address fixed. Please drop the old one from any > replies. Sorry for the noise. Oops, replied with the old one still there. Greg, Andrew: Imo it's best to merge all three patches through the same tree, so: Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> on the i915 parts of it. If you want I can also slurp them in through the intel tree, including the new dmi match code. Thanks, Daniel > > On Thu, 06 Jun 2013, Jani Nikula <jani.nikula@intel.com> wrote: > > Hi Greg, Andrew - > > > > Patch 1 is for DMI, bugfixes in patches 2-3 for i915 and included for > > completeness. After a tested-by they should be good for stable. I'll > > leave it to Daniel to sort out how the last two get in. > > > > BR, > > Jani. > > > > Chris Wilson (1): > > drm/i915: Quirk away phantom LVDS on Intel's D510MO mainboard > > > > Jani Nikula (2): > > dmi: add support for exact DMI matches in addition to substring > > matching > > drm/i915: Quirk away phantom LVDS on Intel's D525MW mainboard > > > > drivers/firmware/dmi_scan.c | 12 +++++++++--- > > drivers/gpu/drm/i915/intel_lvds.c | 16 ++++++++++++++++ > > include/linux/mod_devicetable.h | 6 ++++-- > > 3 files changed, 29 insertions(+), 5 deletions(-) > > > > -- > > 1.7.9.5 > > > > -- > Jani Nikula, Intel Open Source Technology Center -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/3] 2013-06-13 8:22 ` Daniel Vetter @ 2013-06-14 16:23 ` Greg Kroah-Hartman 0 siblings, 0 replies; 17+ messages in thread From: Greg Kroah-Hartman @ 2013-06-14 16:23 UTC (permalink / raw) To: Jani Nikula, linux-kernel, intel-gfx, Andrew Morton, chris On Thu, Jun 13, 2013 at 10:22:05AM +0200, Daniel Vetter wrote: > On Thu, Jun 06, 2013 at 04:59:26PM +0300, Jani Nikula wrote: > > > > With Greg's address fixed. Please drop the old one from any > > replies. Sorry for the noise. > > Oops, replied with the old one still there. > > Greg, Andrew: Imo it's best to merge all three patches through the same > tree, so: > > Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> > > on the i915 parts of it. If you want I can also slurp them in through the > intel tree, including the new dmi match code. Please feel free to take them through your tree, I don't need to take them. thanks, greg k-h ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/3] 2013-06-06 13:53 Jani Nikula 2013-06-06 13:59 ` Jani Nikula @ 2013-06-06 14:33 ` Daniel Vetter 1 sibling, 0 replies; 17+ messages in thread From: Daniel Vetter @ 2013-06-06 14:33 UTC (permalink / raw) To: Jani Nikula Cc: linux-kernel, intel-gfx, Andrew Morton, Greg Kroah-Hartman, chris, daniel On Thu, Jun 06, 2013 at 04:53:01PM +0300, Jani Nikula wrote: > Hi Greg, Andrew - > > Patch 1 is for DMI, bugfixes in patches 2-3 for i915 and included for > completeness. After a tested-by they should be good for stable. I'll > leave it to Daniel to sort out how the last two get in. I'd prefer all to go through the same tree (to avoid tracking them), and conflicts around lvds quirks will be trivial at most. So no problem for me if this doesn't go in through drm-next. So Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> on the i915 patches for merging through whatever tree the drm stuff goes through. -Daniel > > BR, > Jani. > > Chris Wilson (1): > drm/i915: Quirk away phantom LVDS on Intel's D510MO mainboard > > Jani Nikula (2): > dmi: add support for exact DMI matches in addition to substring > matching > drm/i915: Quirk away phantom LVDS on Intel's D525MW mainboard > > drivers/firmware/dmi_scan.c | 12 +++++++++--- > drivers/gpu/drm/i915/intel_lvds.c | 16 ++++++++++++++++ > include/linux/mod_devicetable.h | 6 ++++-- > 3 files changed, 29 insertions(+), 5 deletions(-) > > -- > 1.7.9.5 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/3] @ 2005-12-12 0:41 Petr Baudis 0 siblings, 0 replies; 17+ messages in thread From: Petr Baudis @ 2005-12-12 0:41 UTC (permalink / raw) To: zippel; +Cc: linux-kernel, sam, kbuild-devel The following series implements... -- And on the eigth day, God started debugging. ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-01-09 17:56 UTC | newest] Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-01-03 9:21 [PATCH 0/3] Antoniu Miclaus 2022-01-03 9:21 ` [PATCH 1/3] iio:frequency:admv1014: add support for ADMV1014 Antoniu Miclaus 2022-01-09 18:01 ` Jonathan Cameron 2022-01-03 9:22 ` [PATCH 2/3] dt-bindings:iio:frequency: add admv1014 doc Antoniu Miclaus 2022-01-09 17:46 ` Jonathan Cameron 2022-01-03 9:22 ` [PATCH 3/3] Documentation:ABI:testing:admv1014: add ABI docs Antoniu Miclaus 2022-01-09 17:38 ` Jonathan Cameron -- strict thread matches above, loose matches on Subject: below -- 2020-06-05 18:46 [PATCH 0/3] Matthias Kaehlcke 2020-04-27 8:21 Gareth Williams 2020-04-27 13:21 ` Gareth Williams 2013-09-21 13:05 Fan Rong 2013-06-06 13:53 Jani Nikula 2013-06-06 13:59 ` Jani Nikula 2013-06-13 8:22 ` Daniel Vetter 2013-06-14 16:23 ` Greg Kroah-Hartman 2013-06-06 14:33 ` Daniel Vetter 2005-12-12 0:41 Petr Baudis
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