* [PATCH 01/10] dt-bindings: devfreq: rk3399_dmc: Convert to YAML
2022-01-07 23:53 [PATCH 00/10] rk3399: Clean up and enable DDR DVFS Brian Norris
@ 2022-01-07 23:53 ` Brian Norris
2022-01-09 16:33 ` Rob Herring
2022-01-10 17:16 ` Rob Herring
2022-01-07 23:53 ` [PATCH 02/10] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties Brian Norris
` (8 subsequent siblings)
9 siblings, 2 replies; 16+ messages in thread
From: Brian Norris @ 2022-01-07 23:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring
Cc: Heiko Stuebner, linux-arm-kernel, Lin Huang, devicetree,
linux-rockchip, linux-pm, Derek Basehore, linux-kernel,
Brian Norris
I want to add, deprecate, and bugfix some properties, as well as add the
first users. This is easier with a proper schema.
The transformation is mostly straightforward, plus a few notable tweaks:
* Renamed rockchip,dram_speed_bin to rockchip,ddr3_speed_bin. The
driver code and the example matched, but the description was
different. I went with the implementation.
* Drop upthreshold and downdifferential properties from the example.
These were undocumented (so, wouldn't pass validation), but were
representing software properties (governor tweaks). I drop them from
the driver in subsequent patches.
* Rename clock from pclk_ddr_mon to dmc_clk. The driver, DT example,
and all downstream users matched -- the binding definition was the
exception. Anyway, "dmc_clk" is a more appropriately generic name.
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
.../bindings/devfreq/rk3399_dmc.txt | 212 -------------
.../bindings/devfreq/rk3399_dmc.yaml | 297 ++++++++++++++++++
2 files changed, 297 insertions(+), 212 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
deleted file mode 100644
index 58fc8a6cebc7..000000000000
--- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
+++ /dev/null
@@ -1,212 +0,0 @@
-* Rockchip rk3399 DMC (Dynamic Memory Controller) device
-
-Required properties:
-- compatible: Must be "rockchip,rk3399-dmc".
-- devfreq-events: Node to get DDR loading, Refer to
- Documentation/devicetree/bindings/devfreq/event/
- rockchip-dfi.txt
-- clocks: Phandles for clock specified in "clock-names" property
-- clock-names : The name of clock used by the DFI, must be
- "pclk_ddr_mon";
-- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
- for details.
-- center-supply: DMC supply node.
-- status: Marks the node enabled/disabled.
-- rockchip,pmu: Phandle to the syscon managing the "PMU general register
- files".
-
-Optional properties:
-- interrupts: The CPU interrupt number. The interrupt specifier
- format depends on the interrupt controller.
- It should be a DCF interrupt. When DDR DVFS finishes
- a DCF interrupt is triggered.
-- rockchip,pmu: Phandle to the syscon managing the "PMU general register
- files".
-
-Following properties relate to DDR timing:
-
-- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
- it selects the DDR3 cl-trp-trcd type. It must be
- set according to "Speed Bin" in DDR3 datasheet,
- DO NOT use a smaller "Speed Bin" than specified
- for the DDR3 being used.
-
-- rockchip,pd_idle : Configure the PD_IDLE value. Defines the
- power-down idle period in which memories are
- placed into power-down mode if bus is idle
- for PD_IDLE DFI clock cycles.
-
-- rockchip,sr_idle : Configure the SR_IDLE value. Defines the
- self-refresh idle period in which memories are
- placed into self-refresh mode if bus is idle
- for SR_IDLE * 1024 DFI clock cycles (DFI
- clocks freq is half of DRAM clock), default
- value is "0".
-
-- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
- clock gating idle period. Memories are placed
- into self-refresh mode and memory controller
- clock arg gating started if bus is idle for
- sr_mc_gate_idle*1024 DFI clock cycles.
-
-- rockchip,srpd_lite_idle : Defines the self-refresh power down idle
- period in which memories are placed into
- self-refresh power down mode if bus is idle
- for srpd_lite_idle * 1024 DFI clock cycles.
- This parameter is for LPDDR4 only.
-
-- rockchip,standby_idle : Defines the standby idle period in which
- memories are placed into self-refresh mode.
- The controller, pi, PHY and DRAM clock will
- be gated if bus is idle for standby_idle * DFI
- clock cycles.
-
-- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
- When DDR frequency is less than DRAM_DLL_DISB_FREQ,
- DDR3 DLL will be bypassed. Note: if DLL was bypassed,
- the odt will also stop working.
-
-- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
- MHz (Mega Hz). When DDR frequency is less than
- DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
- Note: PHY DLL and PHY ODT are independent.
-
-- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
- the ODT disable frequency in MHz (Mega Hz).
- when the DDR frequency is less then ddr3_odt_dis_freq,
- the ODT on the DRAM side and controller side are
- both disabled.
-
-- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
- the DRAM side driver strength in ohms. Default
- value is 40.
-
-- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
- the DRAM side ODT strength in ohms. Default value
- is 120.
-
-- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
- the phy side CA line (incluing command line,
- address line and clock line) driver strength.
- Default value is 40.
-
-- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
- the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is 40.
-
-- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
- the PHY side ODT strength. Default value is 240.
-
-- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
- then ODT disable frequency in MHz (Mega Hz).
- When DDR frequency is less then ddr3_odt_dis_freq,
- the ODT on the DRAM side and controller side are
- both disabled.
-
-- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
- the DRAM side driver strength in ohms. Default
- value is 34.
-
-- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
- the DRAM side ODT strength in ohms. Default value
- is 240.
-
-- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
- the PHY side CA line (including command line,
- address line and clock line) driver strength.
- Default value is 40.
-
-- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
- the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is 40.
-
-- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
- the phy side odt strength, default value is 240.
-
-- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
- defines the ODT disable frequency in
- MHz (Mega Hz). When the DDR frequency is less then
- ddr3_odt_dis_freq, the ODT on the DRAM side and
- controller side are both disabled.
-
-- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
- the DRAM side driver strength in ohms. Default
- value is 60.
-
-- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
- the DRAM side ODT on DQS/DQ line strength in ohms.
- Default value is 40.
-
-- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
- the DRAM side ODT on CA line strength in ohms.
- Default value is 40.
-
-- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
- the PHY side CA line (including command address
- line) driver strength. Default value is 40.
-
-- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
- the PHY side clock line and CS line driver
- strength. Default value is 80.
-
-- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
- the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is 80.
-
-- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
- the PHY side ODT strength. Default value is 60.
-
-Example:
- dmc_opp_table: dmc_opp_table {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <900000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <666000000>;
- opp-microvolt = <900000>;
- };
- };
-
- dmc: dmc {
- compatible = "rockchip,rk3399-dmc";
- devfreq-events = <&dfi>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_DDRC>;
- clock-names = "dmc_clk";
- operating-points-v2 = <&dmc_opp_table>;
- center-supply = <&ppvar_centerlogic>;
- upthreshold = <15>;
- downdifferential = <10>;
- rockchip,ddr3_speed_bin = <21>;
- rockchip,pd_idle = <0x40>;
- rockchip,sr_idle = <0x2>;
- rockchip,sr_mc_gate_idle = <0x3>;
- rockchip,srpd_lite_idle = <0x4>;
- rockchip,standby_idle = <0x2000>;
- rockchip,dram_dll_dis_freq = <300>;
- rockchip,phy_dll_dis_freq = <125>;
- rockchip,auto_pd_dis_freq = <666>;
- rockchip,ddr3_odt_dis_freq = <333>;
- rockchip,ddr3_drv = <40>;
- rockchip,ddr3_odt = <120>;
- rockchip,phy_ddr3_ca_drv = <40>;
- rockchip,phy_ddr3_dq_drv = <40>;
- rockchip,phy_ddr3_odt = <240>;
- rockchip,lpddr3_odt_dis_freq = <333>;
- rockchip,lpddr3_drv = <34>;
- rockchip,lpddr3_odt = <240>;
- rockchip,phy_lpddr3_ca_drv = <40>;
- rockchip,phy_lpddr3_dq_drv = <40>;
- rockchip,phy_lpddr3_odt = <240>;
- rockchip,lpddr4_odt_dis_freq = <333>;
- rockchip,lpddr4_drv = <60>;
- rockchip,lpddr4_dq_odt = <40>;
- rockchip,lpddr4_ca_odt = <40>;
- rockchip,phy_lpddr4_ca_drv = <40>;
- rockchip,phy_lpddr4_ck_cs_drv = <80>;
- rockchip,phy_lpddr4_dq_drv = <80>;
- rockchip,phy_lpddr4_odt = <60>;
- };
diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
new file mode 100644
index 000000000000..f12f34d93378
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
@@ -0,0 +1,297 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# %YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/rk3399_dmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
+
+maintainers:
+ - Brian Norris <briannorris@chromium.org>
+
+required:
+ - compatible
+ - devfreq-events
+ - clocks
+ - clock-names
+ - operating-points-v2
+ - center-supply
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3399-dmc
+
+ devfreq-events:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ description:
+ Node to get DDR loading. Refer to
+ Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: dmc_clk
+
+ operating-points-v2:
+ description:
+ Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml for details.
+
+ center-supply:
+ description:
+ DMC regulator supply.
+
+ rockchip,pmu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description:
+ Phandle to the syscon managing the "PMU general register files".
+
+ interrupts:
+ maxItems: 1
+ description:
+ The CPU interrupt number. The interrupt specifier format depends on the
+ interrupt controller. It should be a DCF interrupt. When DDR DVFS
+ finishes a DCF interrupt is triggered.
+
+ rockchip,ddr3_speed_bin:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
+ DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
+ datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
+ being used.
+
+ rockchip,pd_idle:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Configure the PD_IDLE value. Defines the power-down idle period in which
+ memories are placed into power-down mode if bus is idle for PD_IDLE DFI
+ clock cycles.
+
+ rockchip,sr_idle:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Configure the SR_IDLE value. Defines the self-refresh idle period in
+ which memories are placed into self-refresh mode if bus is idle for
+ SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock),
+ default value is "0".
+
+ rockchip,sr_mc_gate_idle:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines the memory self-refresh and controller clock gating idle period.
+ Memories are placed into self-refresh mode and memory controller clock
+ arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
+ cycles.
+
+ rockchip,srpd_lite_idle:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines the self-refresh power down idle period in which memories are
+ placed into self-refresh power down mode if bus is idle for
+ srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
+ only.
+
+ rockchip,standby_idle:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines the standby idle period in which memories are placed into
+ self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
+ if bus is idle for standby_idle * DFI clock cycles.
+
+ rockchip,dram_dll_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
+ than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
+ Note: if DLL was bypassed, the odt will also stop working.
+
+ rockchip,phy_dll_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
+ is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
+ Note: PHY DLL and PHY ODT are independent.
+
+ rockchip,auto_pd_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines the auto PD disable frequency in MHz.
+
+ rockchip,ddr3_odt_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is DDR3, this parameter defines the ODT disable
+ frequency in MHz (Mega Hz). When the DDR frequency is less then
+ ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
+ disabled.
+
+ rockchip,ddr3_drv:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is DDR3, this parameter defines the DRAM side drive
+ strength in ohms. Default value is 40.
+
+ rockchip,ddr3_odt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is DDR3, this parameter defines the DRAM side ODT
+ strength in ohms. Default value is 120.
+
+ rockchip,phy_ddr3_ca_drv:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is DDR3, this parameter defines the phy side CA line
+ (incluing command line, address line and clock line) drive strength.
+ Default value is 40.
+
+ rockchip,phy_ddr3_dq_drv:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is DDR3, this parameter defines the PHY side DQ line
+ (including DQS/DQ/DM line) drive strength. Default value is 40.
+
+ rockchip,phy_ddr3_odt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is DDR3, this parameter defines the PHY side ODT
+ strength. Default value is 240.
+
+ rockchip,lpddr3_odt_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR3, this parameter defines then ODT disable
+ frequency in MHz (Mega Hz). When DDR frequency is less then
+ ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
+ disabled.
+
+ rockchip,lpddr3_drv:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
+ strength in ohms. Default value is 34.
+
+ rockchip,lpddr3_odt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
+ strength in ohms. Default value is 240.
+
+ rockchip,phy_lpddr3_ca_drv:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
+ (including command line, address line and clock line) drive strength.
+ Default value is 40.
+
+ rockchip,phy_lpddr3_dq_drv:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
+ (including DQS/DQ/DM line) drive strength. Default value is 40.
+
+ rockchip,phy_lpddr3_odt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When dram type is LPDDR3, this parameter define the phy side odt
+ strength, default value is 240.
+
+ rockchip,lpddr4_odt_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR4, this parameter defines the ODT disable
+ frequency in MHz (Mega Hz). When the DDR frequency is less then
+ ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
+ disabled.
+
+ rockchip,lpddr4_drv:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
+ strength in ohms. Default value is 60.
+
+ rockchip,lpddr4_dq_odt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
+ DQS/DQ line strength in ohms. Default value is 40.
+
+ rockchip,lpddr4_ca_odt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
+ CA line strength in ohms. Default value is 40.
+
+ rockchip,phy_lpddr4_ca_drv:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
+ (including command address line) drive strength. Default value is 40.
+
+ rockchip,phy_lpddr4_ck_cs_drv:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR4, this parameter defines the PHY side clock
+ line and CS line drive strength. Default value is 80.
+
+ rockchip,phy_lpddr4_dq_drv:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
+ (including DQS/DQ/DM line) drive strength. Default value is 80.
+
+ rockchip,phy_lpddr4_odt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
+ strength. Default value is 60.
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ dmc: dmc {
+ compatible = "rockchip,rk3399-dmc";
+ devfreq-events = <&dfi>;
+ rockchip,pmu = <&pmu>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_DDRC>;
+ clock-names = "dmc_clk";
+ operating-points-v2 = <&dmc_opp_table>;
+ center-supply = <&ppvar_centerlogic>;
+ rockchip,ddr3_speed_bin = <21>;
+ rockchip,pd_idle = <0x40>;
+ rockchip,sr_idle = <0x2>;
+ rockchip,sr_mc_gate_idle = <0x3>;
+ rockchip,srpd_lite_idle = <0x4>;
+ rockchip,standby_idle = <0x2000>;
+ rockchip,dram_dll_dis_freq = <300>;
+ rockchip,phy_dll_dis_freq = <125>;
+ rockchip,auto_pd_dis_freq = <666>;
+ rockchip,ddr3_odt_dis_freq = <333>;
+ rockchip,ddr3_drv = <40>;
+ rockchip,ddr3_odt = <120>;
+ rockchip,phy_ddr3_ca_drv = <40>;
+ rockchip,phy_ddr3_dq_drv = <40>;
+ rockchip,phy_ddr3_odt = <240>;
+ rockchip,lpddr3_odt_dis_freq = <333>;
+ rockchip,lpddr3_drv = <34>;
+ rockchip,lpddr3_odt = <240>;
+ rockchip,phy_lpddr3_ca_drv = <40>;
+ rockchip,phy_lpddr3_dq_drv = <40>;
+ rockchip,phy_lpddr3_odt = <240>;
+ rockchip,lpddr4_odt_dis_freq = <333>;
+ rockchip,lpddr4_drv = <60>;
+ rockchip,lpddr4_dq_odt = <40>;
+ rockchip,lpddr4_ca_odt = <40>;
+ rockchip,phy_lpddr4_ca_drv = <40>;
+ rockchip,phy_lpddr4_ck_cs_drv = <80>;
+ rockchip,phy_lpddr4_dq_drv = <80>;
+ rockchip,phy_lpddr4_odt = <60>;
+ };
--
2.34.1.575.g55b058a8bb-goog
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 01/10] dt-bindings: devfreq: rk3399_dmc: Convert to YAML
2022-01-07 23:53 ` [PATCH 01/10] dt-bindings: devfreq: rk3399_dmc: Convert to YAML Brian Norris
@ 2022-01-09 16:33 ` Rob Herring
2022-01-10 17:16 ` Rob Herring
1 sibling, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-01-09 16:33 UTC (permalink / raw)
To: Brian Norris
Cc: Kyungmin Park, linux-arm-kernel, Rob Herring, linux-kernel,
Chanwoo Choi, devicetree, linux-pm, Heiko Stuebner, MyungJoo Ham,
Derek Basehore, linux-rockchip, Lin Huang
On Fri, 07 Jan 2022 15:53:11 -0800, Brian Norris wrote:
> I want to add, deprecate, and bugfix some properties, as well as add the
> first users. This is easier with a proper schema.
>
> The transformation is mostly straightforward, plus a few notable tweaks:
>
> * Renamed rockchip,dram_speed_bin to rockchip,ddr3_speed_bin. The
> driver code and the example matched, but the description was
> different. I went with the implementation.
>
> * Drop upthreshold and downdifferential properties from the example.
> These were undocumented (so, wouldn't pass validation), but were
> representing software properties (governor tweaks). I drop them from
> the driver in subsequent patches.
>
> * Rename clock from pclk_ddr_mon to dmc_clk. The driver, DT example,
> and all downstream users matched -- the binding definition was the
> exception. Anyway, "dmc_clk" is a more appropriately generic name.
>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
>
> .../bindings/devfreq/rk3399_dmc.txt | 212 -------------
> .../bindings/devfreq/rk3399_dmc.yaml | 297 ++++++++++++++++++
> 2 files changed, 297 insertions(+), 212 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml:37:5: [warning] wrong indentation: expected 6 but found 4 (indentation)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1577007
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 01/10] dt-bindings: devfreq: rk3399_dmc: Convert to YAML
2022-01-07 23:53 ` [PATCH 01/10] dt-bindings: devfreq: rk3399_dmc: Convert to YAML Brian Norris
2022-01-09 16:33 ` Rob Herring
@ 2022-01-10 17:16 ` Rob Herring
1 sibling, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-01-10 17:16 UTC (permalink / raw)
To: Brian Norris
Cc: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Heiko Stuebner,
linux-arm-kernel, Lin Huang, devicetree, linux-rockchip,
linux-pm, Derek Basehore, linux-kernel
On Fri, Jan 07, 2022 at 03:53:11PM -0800, Brian Norris wrote:
> I want to add, deprecate, and bugfix some properties, as well as add the
> first users. This is easier with a proper schema.
>
> The transformation is mostly straightforward, plus a few notable tweaks:
>
> * Renamed rockchip,dram_speed_bin to rockchip,ddr3_speed_bin. The
> driver code and the example matched, but the description was
> different. I went with the implementation.
>
> * Drop upthreshold and downdifferential properties from the example.
> These were undocumented (so, wouldn't pass validation), but were
> representing software properties (governor tweaks). I drop them from
> the driver in subsequent patches.
>
> * Rename clock from pclk_ddr_mon to dmc_clk. The driver, DT example,
> and all downstream users matched -- the binding definition was the
> exception. Anyway, "dmc_clk" is a more appropriately generic name.
generic is not really better, but okay.
>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
>
> .../bindings/devfreq/rk3399_dmc.txt | 212 -------------
> .../bindings/devfreq/rk3399_dmc.yaml | 297 ++++++++++++++++++
> 2 files changed, 297 insertions(+), 212 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> deleted file mode 100644
> index 58fc8a6cebc7..000000000000
> --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> +++ /dev/null
> @@ -1,212 +0,0 @@
> -* Rockchip rk3399 DMC (Dynamic Memory Controller) device
> -
> -Required properties:
> -- compatible: Must be "rockchip,rk3399-dmc".
> -- devfreq-events: Node to get DDR loading, Refer to
> - Documentation/devicetree/bindings/devfreq/event/
> - rockchip-dfi.txt
> -- clocks: Phandles for clock specified in "clock-names" property
> -- clock-names : The name of clock used by the DFI, must be
> - "pclk_ddr_mon";
> -- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
> - for details.
> -- center-supply: DMC supply node.
> -- status: Marks the node enabled/disabled.
> -- rockchip,pmu: Phandle to the syscon managing the "PMU general register
> - files".
> -
> -Optional properties:
> -- interrupts: The CPU interrupt number. The interrupt specifier
> - format depends on the interrupt controller.
> - It should be a DCF interrupt. When DDR DVFS finishes
> - a DCF interrupt is triggered.
> -- rockchip,pmu: Phandle to the syscon managing the "PMU general register
> - files".
> -
> -Following properties relate to DDR timing:
> -
> -- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
> - it selects the DDR3 cl-trp-trcd type. It must be
> - set according to "Speed Bin" in DDR3 datasheet,
> - DO NOT use a smaller "Speed Bin" than specified
> - for the DDR3 being used.
> -
> -- rockchip,pd_idle : Configure the PD_IDLE value. Defines the
> - power-down idle period in which memories are
> - placed into power-down mode if bus is idle
> - for PD_IDLE DFI clock cycles.
> -
> -- rockchip,sr_idle : Configure the SR_IDLE value. Defines the
> - self-refresh idle period in which memories are
> - placed into self-refresh mode if bus is idle
> - for SR_IDLE * 1024 DFI clock cycles (DFI
> - clocks freq is half of DRAM clock), default
> - value is "0".
> -
> -- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
> - clock gating idle period. Memories are placed
> - into self-refresh mode and memory controller
> - clock arg gating started if bus is idle for
> - sr_mc_gate_idle*1024 DFI clock cycles.
> -
> -- rockchip,srpd_lite_idle : Defines the self-refresh power down idle
> - period in which memories are placed into
> - self-refresh power down mode if bus is idle
> - for srpd_lite_idle * 1024 DFI clock cycles.
> - This parameter is for LPDDR4 only.
> -
> -- rockchip,standby_idle : Defines the standby idle period in which
> - memories are placed into self-refresh mode.
> - The controller, pi, PHY and DRAM clock will
> - be gated if bus is idle for standby_idle * DFI
> - clock cycles.
> -
> -- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
> - When DDR frequency is less than DRAM_DLL_DISB_FREQ,
> - DDR3 DLL will be bypassed. Note: if DLL was bypassed,
> - the odt will also stop working.
> -
> -- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
> - MHz (Mega Hz). When DDR frequency is less than
> - DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
> - Note: PHY DLL and PHY ODT are independent.
> -
> -- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
> - the ODT disable frequency in MHz (Mega Hz).
> - when the DDR frequency is less then ddr3_odt_dis_freq,
> - the ODT on the DRAM side and controller side are
> - both disabled.
> -
> -- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
> - the DRAM side driver strength in ohms. Default
> - value is 40.
> -
> -- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
> - the DRAM side ODT strength in ohms. Default value
> - is 120.
> -
> -- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
> - the phy side CA line (incluing command line,
> - address line and clock line) driver strength.
> - Default value is 40.
> -
> -- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
> - the PHY side DQ line (including DQS/DQ/DM line)
> - driver strength. Default value is 40.
> -
> -- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
> - the PHY side ODT strength. Default value is 240.
> -
> -- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
> - then ODT disable frequency in MHz (Mega Hz).
> - When DDR frequency is less then ddr3_odt_dis_freq,
> - the ODT on the DRAM side and controller side are
> - both disabled.
> -
> -- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
> - the DRAM side driver strength in ohms. Default
> - value is 34.
> -
> -- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
> - the DRAM side ODT strength in ohms. Default value
> - is 240.
> -
> -- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
> - the PHY side CA line (including command line,
> - address line and clock line) driver strength.
> - Default value is 40.
> -
> -- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
> - the PHY side DQ line (including DQS/DQ/DM line)
> - driver strength. Default value is 40.
> -
> -- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
> - the phy side odt strength, default value is 240.
> -
> -- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
> - defines the ODT disable frequency in
> - MHz (Mega Hz). When the DDR frequency is less then
> - ddr3_odt_dis_freq, the ODT on the DRAM side and
> - controller side are both disabled.
> -
> -- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
> - the DRAM side driver strength in ohms. Default
> - value is 60.
> -
> -- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
> - the DRAM side ODT on DQS/DQ line strength in ohms.
> - Default value is 40.
> -
> -- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
> - the DRAM side ODT on CA line strength in ohms.
> - Default value is 40.
> -
> -- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
> - the PHY side CA line (including command address
> - line) driver strength. Default value is 40.
> -
> -- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
> - the PHY side clock line and CS line driver
> - strength. Default value is 80.
> -
> -- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
> - the PHY side DQ line (including DQS/DQ/DM line)
> - driver strength. Default value is 80.
> -
> -- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
> - the PHY side ODT strength. Default value is 60.
> -
> -Example:
> - dmc_opp_table: dmc_opp_table {
> - compatible = "operating-points-v2";
> -
> - opp00 {
> - opp-hz = /bits/ 64 <300000000>;
> - opp-microvolt = <900000>;
> - };
> - opp01 {
> - opp-hz = /bits/ 64 <666000000>;
> - opp-microvolt = <900000>;
> - };
> - };
> -
> - dmc: dmc {
> - compatible = "rockchip,rk3399-dmc";
> - devfreq-events = <&dfi>;
> - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cru SCLK_DDRC>;
> - clock-names = "dmc_clk";
> - operating-points-v2 = <&dmc_opp_table>;
> - center-supply = <&ppvar_centerlogic>;
> - upthreshold = <15>;
> - downdifferential = <10>;
> - rockchip,ddr3_speed_bin = <21>;
> - rockchip,pd_idle = <0x40>;
> - rockchip,sr_idle = <0x2>;
> - rockchip,sr_mc_gate_idle = <0x3>;
> - rockchip,srpd_lite_idle = <0x4>;
> - rockchip,standby_idle = <0x2000>;
> - rockchip,dram_dll_dis_freq = <300>;
> - rockchip,phy_dll_dis_freq = <125>;
> - rockchip,auto_pd_dis_freq = <666>;
> - rockchip,ddr3_odt_dis_freq = <333>;
> - rockchip,ddr3_drv = <40>;
> - rockchip,ddr3_odt = <120>;
> - rockchip,phy_ddr3_ca_drv = <40>;
> - rockchip,phy_ddr3_dq_drv = <40>;
> - rockchip,phy_ddr3_odt = <240>;
> - rockchip,lpddr3_odt_dis_freq = <333>;
> - rockchip,lpddr3_drv = <34>;
> - rockchip,lpddr3_odt = <240>;
> - rockchip,phy_lpddr3_ca_drv = <40>;
> - rockchip,phy_lpddr3_dq_drv = <40>;
> - rockchip,phy_lpddr3_odt = <240>;
> - rockchip,lpddr4_odt_dis_freq = <333>;
> - rockchip,lpddr4_drv = <60>;
> - rockchip,lpddr4_dq_odt = <40>;
> - rockchip,lpddr4_ca_odt = <40>;
> - rockchip,phy_lpddr4_ca_drv = <40>;
> - rockchip,phy_lpddr4_ck_cs_drv = <80>;
> - rockchip,phy_lpddr4_dq_drv = <80>;
> - rockchip,phy_lpddr4_odt = <60>;
> - };
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
> new file mode 100644
> index 000000000000..f12f34d93378
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
> @@ -0,0 +1,297 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# %YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/devfreq/rk3399_dmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
> +
> +maintainers:
> + - Brian Norris <briannorris@chromium.org>
> +
> +required:
'required' normally goes after properties.
> + - compatible
> + - devfreq-events
> + - clocks
> + - clock-names
> + - operating-points-v2
> + - center-supply
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3399-dmc
> +
> + devfreq-events:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + minItems: 1
> + description:
> + Node to get DDR loading. Refer to
> + Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: dmc_clk
> +
> + operating-points-v2:
> + description:
> + Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml for details.
Drop generic, free form references. Just 'true' is fine here.
> +
> + center-supply:
> + description:
> + DMC regulator supply.
> +
> + rockchip,pmu:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + maxItems: 1
'phandle' is already a single item. Drop.
> + description:
> + Phandle to the syscon managing the "PMU general register files".
> +
> + interrupts:
> + maxItems: 1
> + description:
> + The CPU interrupt number. The interrupt specifier format depends on the
> + interrupt controller. It should be a DCF interrupt. When DDR DVFS
> + finishes a DCF interrupt is triggered.
You can drop 'The interrupt specifier format depends on the interrupt
controller'.
> +
> + rockchip,ddr3_speed_bin:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
> + DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
> + datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
> + being used.
> +
> + rockchip,pd_idle:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Configure the PD_IDLE value. Defines the power-down idle period in which
> + memories are placed into power-down mode if bus is idle for PD_IDLE DFI
> + clock cycles.
> +
> + rockchip,sr_idle:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Configure the SR_IDLE value. Defines the self-refresh idle period in
> + which memories are placed into self-refresh mode if bus is idle for
> + SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock),
> + default value is "0".
> +
> + rockchip,sr_mc_gate_idle:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Defines the memory self-refresh and controller clock gating idle period.
> + Memories are placed into self-refresh mode and memory controller clock
> + arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
> + cycles.
> +
> + rockchip,srpd_lite_idle:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Defines the self-refresh power down idle period in which memories are
> + placed into self-refresh power down mode if bus is idle for
> + srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
> + only.
> +
> + rockchip,standby_idle:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Defines the standby idle period in which memories are placed into
> + self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
> + if bus is idle for standby_idle * DFI clock cycles.
> +
> + rockchip,dram_dll_dis_freq:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
> + than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
> + Note: if DLL was bypassed, the odt will also stop working.
> +
> + rockchip,phy_dll_dis_freq:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
> + is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
> + Note: PHY DLL and PHY ODT are independent.
> +
> + rockchip,auto_pd_dis_freq:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Defines the auto PD disable frequency in MHz.
> +
> + rockchip,ddr3_odt_dis_freq:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is DDR3, this parameter defines the ODT disable
> + frequency in MHz (Mega Hz). When the DDR frequency is less then
> + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
> + disabled.
> +
> + rockchip,ddr3_drv:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is DDR3, this parameter defines the DRAM side drive
> + strength in ohms. Default value is 40.
> +
> + rockchip,ddr3_odt:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is DDR3, this parameter defines the DRAM side ODT
> + strength in ohms. Default value is 120.
> +
> + rockchip,phy_ddr3_ca_drv:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is DDR3, this parameter defines the phy side CA line
> + (incluing command line, address line and clock line) drive strength.
> + Default value is 40.
> +
> + rockchip,phy_ddr3_dq_drv:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is DDR3, this parameter defines the PHY side DQ line
> + (including DQS/DQ/DM line) drive strength. Default value is 40.
> +
> + rockchip,phy_ddr3_odt:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is DDR3, this parameter defines the PHY side ODT
> + strength. Default value is 240.
> +
> + rockchip,lpddr3_odt_dis_freq:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR3, this parameter defines then ODT disable
> + frequency in MHz (Mega Hz). When DDR frequency is less then
> + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
> + disabled.
> +
> + rockchip,lpddr3_drv:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
> + strength in ohms. Default value is 34.
> +
> + rockchip,lpddr3_odt:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
> + strength in ohms. Default value is 240.
> +
> + rockchip,phy_lpddr3_ca_drv:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
> + (including command line, address line and clock line) drive strength.
> + Default value is 40.
> +
> + rockchip,phy_lpddr3_dq_drv:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
> + (including DQS/DQ/DM line) drive strength. Default value is 40.
> +
> + rockchip,phy_lpddr3_odt:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When dram type is LPDDR3, this parameter define the phy side odt
> + strength, default value is 240.
> +
> + rockchip,lpddr4_odt_dis_freq:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR4, this parameter defines the ODT disable
> + frequency in MHz (Mega Hz). When the DDR frequency is less then
> + ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
> + disabled.
> +
> + rockchip,lpddr4_drv:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
> + strength in ohms. Default value is 60.
> +
> + rockchip,lpddr4_dq_odt:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
> + DQS/DQ line strength in ohms. Default value is 40.
> +
> + rockchip,lpddr4_ca_odt:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
> + CA line strength in ohms. Default value is 40.
> +
> + rockchip,phy_lpddr4_ca_drv:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
> + (including command address line) drive strength. Default value is 40.
> +
> + rockchip,phy_lpddr4_ck_cs_drv:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR4, this parameter defines the PHY side clock
> + line and CS line drive strength. Default value is 80.
> +
> + rockchip,phy_lpddr4_dq_drv:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
> + (including DQS/DQ/DM line) drive strength. Default value is 80.
> +
> + rockchip,phy_lpddr4_odt:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
> + strength. Default value is 60.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/rk3399-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + dmc: dmc {
memory-controller {
> + compatible = "rockchip,rk3399-dmc";
> + devfreq-events = <&dfi>;
> + rockchip,pmu = <&pmu>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_DDRC>;
> + clock-names = "dmc_clk";
> + operating-points-v2 = <&dmc_opp_table>;
> + center-supply = <&ppvar_centerlogic>;
> + rockchip,ddr3_speed_bin = <21>;
> + rockchip,pd_idle = <0x40>;
> + rockchip,sr_idle = <0x2>;
> + rockchip,sr_mc_gate_idle = <0x3>;
> + rockchip,srpd_lite_idle = <0x4>;
> + rockchip,standby_idle = <0x2000>;
> + rockchip,dram_dll_dis_freq = <300>;
> + rockchip,phy_dll_dis_freq = <125>;
> + rockchip,auto_pd_dis_freq = <666>;
> + rockchip,ddr3_odt_dis_freq = <333>;
> + rockchip,ddr3_drv = <40>;
> + rockchip,ddr3_odt = <120>;
> + rockchip,phy_ddr3_ca_drv = <40>;
> + rockchip,phy_ddr3_dq_drv = <40>;
> + rockchip,phy_ddr3_odt = <240>;
> + rockchip,lpddr3_odt_dis_freq = <333>;
> + rockchip,lpddr3_drv = <34>;
> + rockchip,lpddr3_odt = <240>;
> + rockchip,phy_lpddr3_ca_drv = <40>;
> + rockchip,phy_lpddr3_dq_drv = <40>;
> + rockchip,phy_lpddr3_odt = <240>;
> + rockchip,lpddr4_odt_dis_freq = <333>;
> + rockchip,lpddr4_drv = <60>;
> + rockchip,lpddr4_dq_odt = <40>;
> + rockchip,lpddr4_ca_odt = <40>;
> + rockchip,phy_lpddr4_ca_drv = <40>;
> + rockchip,phy_lpddr4_ck_cs_drv = <80>;
> + rockchip,phy_lpddr4_dq_drv = <80>;
> + rockchip,phy_lpddr4_odt = <60>;
> + };
> --
> 2.34.1.575.g55b058a8bb-goog
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 02/10] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties
2022-01-07 23:53 [PATCH 00/10] rk3399: Clean up and enable DDR DVFS Brian Norris
2022-01-07 23:53 ` [PATCH 01/10] dt-bindings: devfreq: rk3399_dmc: Convert to YAML Brian Norris
@ 2022-01-07 23:53 ` Brian Norris
2022-01-12 1:59 ` Rob Herring
2022-01-07 23:53 ` [PATCH 03/10] dt-bindings: devfreq: rk3399_dmc: Fix Hz units Brian Norris
` (7 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Brian Norris @ 2022-01-07 23:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring
Cc: Heiko Stuebner, linux-arm-kernel, Lin Huang, devicetree,
linux-rockchip, linux-pm, Derek Basehore, linux-kernel,
Brian Norris
These DRAM configuration properties are all handled in ARM Trusted
Firmware (and have been since the early days of this SoC), and there are
no in-tree users of the DMC binding yet. It's better to just defer to
firmware instead of maintaining this large list of properties.
There's also some confusion about units: many of these are specified in
MHz, but the downstream users and driver code are treating them as Hz, I
believe. Rather than straighten all that out, I just drop them.
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
.../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++----------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
index f12f34d93378..6bb411dddb7b 100644
--- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
@@ -58,6 +58,7 @@ properties:
finishes a DCF interrupt is triggered.
rockchip,ddr3_speed_bin:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
@@ -104,6 +105,7 @@ properties:
if bus is idle for standby_idle * DFI clock cycles.
rockchip,dram_dll_dis_freq:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
@@ -111,6 +113,7 @@ properties:
Note: if DLL was bypassed, the odt will also stop working.
rockchip,phy_dll_dis_freq:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
@@ -118,6 +121,7 @@ properties:
Note: PHY DLL and PHY ODT are independent.
rockchip,auto_pd_dis_freq:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the auto PD disable frequency in MHz.
@@ -131,18 +135,21 @@ properties:
disabled.
rockchip,ddr3_drv:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the DRAM side drive
strength in ohms. Default value is 40.
rockchip,ddr3_odt:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the DRAM side ODT
strength in ohms. Default value is 120.
rockchip,phy_ddr3_ca_drv:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the phy side CA line
@@ -150,12 +157,14 @@ properties:
Default value is 40.
rockchip,phy_ddr3_dq_drv:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the PHY side DQ line
(including DQS/DQ/DM line) drive strength. Default value is 40.
rockchip,phy_ddr3_odt:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the PHY side ODT
@@ -170,18 +179,21 @@ properties:
disabled.
rockchip,lpddr3_drv:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
strength in ohms. Default value is 34.
rockchip,lpddr3_odt:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
strength in ohms. Default value is 240.
rockchip,phy_lpddr3_ca_drv:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
@@ -189,12 +201,14 @@ properties:
Default value is 40.
rockchip,phy_lpddr3_dq_drv:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
(including DQS/DQ/DM line) drive strength. Default value is 40.
rockchip,phy_lpddr3_odt:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When dram type is LPDDR3, this parameter define the phy side odt
@@ -209,42 +223,49 @@ properties:
disabled.
rockchip,lpddr4_drv:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
strength in ohms. Default value is 60.
rockchip,lpddr4_dq_odt:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
DQS/DQ line strength in ohms. Default value is 40.
rockchip,lpddr4_ca_odt:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
CA line strength in ohms. Default value is 40.
rockchip,phy_lpddr4_ca_drv:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
(including command address line) drive strength. Default value is 40.
rockchip,phy_lpddr4_ck_cs_drv:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side clock
line and CS line drive strength. Default value is 80.
rockchip,phy_lpddr4_dq_drv:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
(including DQS/DQ/DM line) drive strength. Default value is 80.
rockchip,phy_lpddr4_odt:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
@@ -265,33 +286,12 @@ examples:
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;
- rockchip,ddr3_speed_bin = <21>;
rockchip,pd_idle = <0x40>;
rockchip,sr_idle = <0x2>;
rockchip,sr_mc_gate_idle = <0x3>;
rockchip,srpd_lite_idle = <0x4>;
rockchip,standby_idle = <0x2000>;
- rockchip,dram_dll_dis_freq = <300>;
- rockchip,phy_dll_dis_freq = <125>;
- rockchip,auto_pd_dis_freq = <666>;
rockchip,ddr3_odt_dis_freq = <333>;
- rockchip,ddr3_drv = <40>;
- rockchip,ddr3_odt = <120>;
- rockchip,phy_ddr3_ca_drv = <40>;
- rockchip,phy_ddr3_dq_drv = <40>;
- rockchip,phy_ddr3_odt = <240>;
rockchip,lpddr3_odt_dis_freq = <333>;
- rockchip,lpddr3_drv = <34>;
- rockchip,lpddr3_odt = <240>;
- rockchip,phy_lpddr3_ca_drv = <40>;
- rockchip,phy_lpddr3_dq_drv = <40>;
- rockchip,phy_lpddr3_odt = <240>;
rockchip,lpddr4_odt_dis_freq = <333>;
- rockchip,lpddr4_drv = <60>;
- rockchip,lpddr4_dq_odt = <40>;
- rockchip,lpddr4_ca_odt = <40>;
- rockchip,phy_lpddr4_ca_drv = <40>;
- rockchip,phy_lpddr4_ck_cs_drv = <80>;
- rockchip,phy_lpddr4_dq_drv = <80>;
- rockchip,phy_lpddr4_odt = <60>;
};
--
2.34.1.575.g55b058a8bb-goog
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 02/10] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties
2022-01-07 23:53 ` [PATCH 02/10] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties Brian Norris
@ 2022-01-12 1:59 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-01-12 1:59 UTC (permalink / raw)
To: Brian Norris
Cc: Kyungmin Park, linux-pm, devicetree, Heiko Stuebner,
linux-arm-kernel, linux-kernel, Chanwoo Choi, Lin Huang,
Derek Basehore, linux-rockchip, Rob Herring, MyungJoo Ham
On Fri, 07 Jan 2022 15:53:12 -0800, Brian Norris wrote:
> These DRAM configuration properties are all handled in ARM Trusted
> Firmware (and have been since the early days of this SoC), and there are
> no in-tree users of the DMC binding yet. It's better to just defer to
> firmware instead of maintaining this large list of properties.
>
> There's also some confusion about units: many of these are specified in
> MHz, but the downstream users and driver code are treating them as Hz, I
> believe. Rather than straighten all that out, I just drop them.
>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
>
> .../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++----------
> 1 file changed, 21 insertions(+), 21 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 03/10] dt-bindings: devfreq: rk3399_dmc: Fix Hz units
2022-01-07 23:53 [PATCH 00/10] rk3399: Clean up and enable DDR DVFS Brian Norris
2022-01-07 23:53 ` [PATCH 01/10] dt-bindings: devfreq: rk3399_dmc: Convert to YAML Brian Norris
2022-01-07 23:53 ` [PATCH 02/10] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties Brian Norris
@ 2022-01-07 23:53 ` Brian Norris
2022-01-12 2:01 ` Rob Herring
2022-01-07 23:53 ` [PATCH 04/10] dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties Brian Norris
` (6 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Brian Norris @ 2022-01-07 23:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring
Cc: Heiko Stuebner, linux-arm-kernel, Lin Huang, devicetree,
linux-rockchip, linux-pm, Derek Basehore, linux-kernel,
Brian Norris
The driver and all downstream device trees [1] are using Hz units, but
the document claims MHz. DRAM frequency for these systems can't possibly
exceed 2^32-1 Hz, so the choice of unit doesn't really matter than much.
Rather than add unnecessary risk in getting the units wrong, let's just
go with the unofficial convention and make the docs match reality.
A sub-1MHz frequency is extremely unlikely, so include a minimum in the
schema, to help catch anybody who might have believed this was MHz.
[1] And notably, also those trying to upstream them:
https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@linaro.org/
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
.../bindings/devfreq/rk3399_dmc.yaml | 24 +++++++++----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
index 6bb411dddb7b..2c871c57fd97 100644
--- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
@@ -128,11 +128,11 @@ properties:
rockchip,ddr3_odt_dis_freq:
$ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1000000 # In case anyone thought this was MHz.
description:
When the DRAM type is DDR3, this parameter defines the ODT disable
- frequency in MHz (Mega Hz). When the DDR frequency is less then
- ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
- disabled.
+ frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
+ the ODT on the DRAM side and controller side are both disabled.
rockchip,ddr3_drv:
deprecated: true
@@ -172,11 +172,11 @@ properties:
rockchip,lpddr3_odt_dis_freq:
$ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1000000 # In case anyone thought this was MHz.
description:
When the DRAM type is LPDDR3, this parameter defines then ODT disable
- frequency in MHz (Mega Hz). When DDR frequency is less then
- ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
- disabled.
+ frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
+ ODT on the DRAM side and controller side are both disabled.
rockchip,lpddr3_drv:
deprecated: true
@@ -216,11 +216,11 @@ properties:
rockchip,lpddr4_odt_dis_freq:
$ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1000000 # In case anyone thought this was MHz.
description:
When the DRAM type is LPDDR4, this parameter defines the ODT disable
- frequency in MHz (Mega Hz). When the DDR frequency is less then
- ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
- disabled.
+ frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
+ the ODT on the DRAM side and controller side are both disabled.
rockchip,lpddr4_drv:
deprecated: true
@@ -291,7 +291,7 @@ examples:
rockchip,sr_mc_gate_idle = <0x3>;
rockchip,srpd_lite_idle = <0x4>;
rockchip,standby_idle = <0x2000>;
- rockchip,ddr3_odt_dis_freq = <333>;
- rockchip,lpddr3_odt_dis_freq = <333>;
- rockchip,lpddr4_odt_dis_freq = <333>;
+ rockchip,ddr3_odt_dis_freq = <333000000>;
+ rockchip,lpddr3_odt_dis_freq = <333000000>;
+ rockchip,lpddr4_odt_dis_freq = <333000000>;
};
--
2.34.1.575.g55b058a8bb-goog
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 03/10] dt-bindings: devfreq: rk3399_dmc: Fix Hz units
2022-01-07 23:53 ` [PATCH 03/10] dt-bindings: devfreq: rk3399_dmc: Fix Hz units Brian Norris
@ 2022-01-12 2:01 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-01-12 2:01 UTC (permalink / raw)
To: Brian Norris
Cc: Kyungmin Park, linux-arm-kernel, linux-pm, Lin Huang,
MyungJoo Ham, Chanwoo Choi, linux-kernel, Rob Herring,
Derek Basehore, devicetree, Heiko Stuebner, linux-rockchip
On Fri, 07 Jan 2022 15:53:13 -0800, Brian Norris wrote:
> The driver and all downstream device trees [1] are using Hz units, but
> the document claims MHz. DRAM frequency for these systems can't possibly
> exceed 2^32-1 Hz, so the choice of unit doesn't really matter than much.
>
> Rather than add unnecessary risk in getting the units wrong, let's just
> go with the unofficial convention and make the docs match reality.
>
> A sub-1MHz frequency is extremely unlikely, so include a minimum in the
> schema, to help catch anybody who might have believed this was MHz.
>
> [1] And notably, also those trying to upstream them:
> https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@linaro.org/
>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
>
> .../bindings/devfreq/rk3399_dmc.yaml | 24 +++++++++----------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 04/10] dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties
2022-01-07 23:53 [PATCH 00/10] rk3399: Clean up and enable DDR DVFS Brian Norris
` (2 preceding siblings ...)
2022-01-07 23:53 ` [PATCH 03/10] dt-bindings: devfreq: rk3399_dmc: Fix Hz units Brian Norris
@ 2022-01-07 23:53 ` Brian Norris
2022-01-12 2:04 ` Rob Herring
2022-01-07 23:53 ` [PATCH 05/10] PM / devfreq: rk3399_dmc: Drop undocumented ondemand DT props Brian Norris
` (5 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Brian Norris @ 2022-01-07 23:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring
Cc: Heiko Stuebner, linux-arm-kernel, Lin Huang, devicetree,
linux-rockchip, linux-pm, Derek Basehore, linux-kernel,
Brian Norris
DDR DVFS tuning has found that several power-saving features don't have
good tradeoffs at higher frequencies -- at higher frequencies, we'll see
glitches or other errors. Provide tuning controls so these can be
disabled at higher OPPs, and left active only at the lower ones.
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
.../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
index 2c871c57fd97..357d07c5a3df 100644
--- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
@@ -271,6 +271,43 @@ properties:
When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
strength. Default value is 60.
+ rockchip,pd_idle_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines the power-down idle disable frequency in Hz. When the DDR
+ frequency is greater than pd_idle_dis_freq, power-down idle is disabled.
+ See also rockchip,pd_idle.
+
+ rockchip,sr_idle_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines the self-refresh idle disable frequency in Hz. When the DDR
+ frequency is greater than sr_idle_dis_freq, self-refresh idle is
+ disabled. See also rockchip,sr_idle.
+
+ rockchip,sr_mc_gate_idle_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines the self-refresh and memory-controller clock gating disable
+ frequency in Hz. When the DDR frequency is greater than
+ sr_mc_gate_idle_dis_freq, the clock will not be gated when idle. See also
+ rockchip,sr_mc_gate_idle.
+
+ rockchip,srpd_lite_idle_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines the self-refresh power down idle disable frequency in Hz. When
+ the DDR frequency is greater than srpd_lite_idle_dis_freq, memory will
+ not be placed into self-refresh power down mode when idle. See also
+ rockchip,srpd_lite_idle.
+
+ rockchip,standby_idle_dis_freq:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Defines the standby idle disable frequency in Hz. When the DDR frequency
+ is greater than standby_idle_dis_freq, standby idle is disabled. See also
+ rockchip,standby_idle.
+
additionalProperties: false
examples:
@@ -294,4 +331,9 @@ examples:
rockchip,ddr3_odt_dis_freq = <333000000>;
rockchip,lpddr3_odt_dis_freq = <333000000>;
rockchip,lpddr4_odt_dis_freq = <333000000>;
+ rockchip,pd_idle_dis_freq = <1000000000>;
+ rockchip,sr_idle_dis_freq = <1000000000>;
+ rockchip,sr_mc_gate_idle_dis_freq = <1000000000>;
+ rockchip,srpd_lite_idle_dis_freq = <0>;
+ rockchip,standby_idle_dis_freq = <928000000>;
};
--
2.34.1.575.g55b058a8bb-goog
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 04/10] dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties
2022-01-07 23:53 ` [PATCH 04/10] dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties Brian Norris
@ 2022-01-12 2:04 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-01-12 2:04 UTC (permalink / raw)
To: Brian Norris
Cc: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Heiko Stuebner,
linux-arm-kernel, Lin Huang, devicetree, linux-rockchip,
linux-pm, Derek Basehore, linux-kernel
On Fri, Jan 07, 2022 at 03:53:14PM -0800, Brian Norris wrote:
> DDR DVFS tuning has found that several power-saving features don't have
> good tradeoffs at higher frequencies -- at higher frequencies, we'll see
> glitches or other errors. Provide tuning controls so these can be
> disabled at higher OPPs, and left active only at the lower ones.
>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
>
> .../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
> index 2c871c57fd97..357d07c5a3df 100644
> --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
> @@ -271,6 +271,43 @@ properties:
> When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
> strength. Default value is 60.
>
> + rockchip,pd_idle_dis_freq:
s/_/-/
on all the new properties.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Defines the power-down idle disable frequency in Hz. When the DDR
> + frequency is greater than pd_idle_dis_freq, power-down idle is disabled.
> + See also rockchip,pd_idle.
> +
> + rockchip,sr_idle_dis_freq:
'-hz' suffix. Let's not repeat the same problem.
> + $ref: /schemas/types.yaml#/definitions/uint32
And then the type can be dropped.
> + description:
> + Defines the self-refresh idle disable frequency in Hz. When the DDR
> + frequency is greater than sr_idle_dis_freq, self-refresh idle is
> + disabled. See also rockchip,sr_idle.
> +
> + rockchip,sr_mc_gate_idle_dis_freq:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Defines the self-refresh and memory-controller clock gating disable
> + frequency in Hz. When the DDR frequency is greater than
> + sr_mc_gate_idle_dis_freq, the clock will not be gated when idle. See also
> + rockchip,sr_mc_gate_idle.
> +
> + rockchip,srpd_lite_idle_dis_freq:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Defines the self-refresh power down idle disable frequency in Hz. When
> + the DDR frequency is greater than srpd_lite_idle_dis_freq, memory will
> + not be placed into self-refresh power down mode when idle. See also
> + rockchip,srpd_lite_idle.
> +
> + rockchip,standby_idle_dis_freq:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Defines the standby idle disable frequency in Hz. When the DDR frequency
> + is greater than standby_idle_dis_freq, standby idle is disabled. See also
> + rockchip,standby_idle.
> +
> additionalProperties: false
>
> examples:
> @@ -294,4 +331,9 @@ examples:
> rockchip,ddr3_odt_dis_freq = <333000000>;
> rockchip,lpddr3_odt_dis_freq = <333000000>;
> rockchip,lpddr4_odt_dis_freq = <333000000>;
> + rockchip,pd_idle_dis_freq = <1000000000>;
> + rockchip,sr_idle_dis_freq = <1000000000>;
> + rockchip,sr_mc_gate_idle_dis_freq = <1000000000>;
> + rockchip,srpd_lite_idle_dis_freq = <0>;
> + rockchip,standby_idle_dis_freq = <928000000>;
> };
> --
> 2.34.1.575.g55b058a8bb-goog
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 05/10] PM / devfreq: rk3399_dmc: Drop undocumented ondemand DT props
2022-01-07 23:53 [PATCH 00/10] rk3399: Clean up and enable DDR DVFS Brian Norris
` (3 preceding siblings ...)
2022-01-07 23:53 ` [PATCH 04/10] dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties Brian Norris
@ 2022-01-07 23:53 ` Brian Norris
2022-01-07 23:53 ` [PATCH 06/10] PM / devfreq: rk3399_dmc: Drop excess timing properties Brian Norris
` (4 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Brian Norris @ 2022-01-07 23:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring
Cc: Heiko Stuebner, linux-arm-kernel, Lin Huang, devicetree,
linux-rockchip, linux-pm, Derek Basehore, linux-kernel,
Brian Norris
These properties are:
* undocumented
* directly representing software properties, not hardware properties
* unused (no in-tree users, yet; this IP block has so far only been used
in downstream kernels)
Let's just stick the values that downstream users have been using
directly in the driver and call it a day.
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
drivers/devfreq/rk3399_dmc.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
index 293857ebfd75..e982862f6ac2 100644
--- a/drivers/devfreq/rk3399_dmc.c
+++ b/drivers/devfreq/rk3399_dmc.c
@@ -430,10 +430,8 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
goto err_edev;
}
- of_property_read_u32(np, "upthreshold",
- &data->ondemand_data.upthreshold);
- of_property_read_u32(np, "downdifferential",
- &data->ondemand_data.downdifferential);
+ data->ondemand_data.upthreshold = 25;
+ data->ondemand_data.downdifferential = 15;
data->rate = clk_get_rate(data->dmc_clk);
--
2.34.1.575.g55b058a8bb-goog
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 06/10] PM / devfreq: rk3399_dmc: Drop excess timing properties
2022-01-07 23:53 [PATCH 00/10] rk3399: Clean up and enable DDR DVFS Brian Norris
` (4 preceding siblings ...)
2022-01-07 23:53 ` [PATCH 05/10] PM / devfreq: rk3399_dmc: Drop undocumented ondemand DT props Brian Norris
@ 2022-01-07 23:53 ` Brian Norris
2022-01-07 23:53 ` [PATCH 07/10] PM / devfreq: rk3399_dmc: Use bitfield macro definitions for ODT_PD Brian Norris
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Brian Norris @ 2022-01-07 23:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring
Cc: Heiko Stuebner, linux-arm-kernel, Lin Huang, devicetree,
linux-rockchip, linux-pm, Derek Basehore, linux-kernel,
Brian Norris
All of these properties are initialized by ARM Trusted Firmware, and
have been since the early days of this chip. It's redundant (and
possibly wrong) to do this here now. What's more, there seems to be some
confusion about the units and some of the definitions of this timing
struct: the DT docs say MHz for many of these, but downstream users were
in Hz (and therefore, the ATF interface was Hz). Also, the in-driver
usage for some of these (e.g., for comparing to target frequency) were
in Hz too. So doubly wrong.
We can avoid thinking about who got the right units by dropping the
unnecessary code and properties. They are marked deprecated in the
binding schema.
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
drivers/devfreq/rk3399_dmc.c | 144 +++++++----------------------------
1 file changed, 29 insertions(+), 115 deletions(-)
diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
index e982862f6ac2..8f447217303f 100644
--- a/drivers/devfreq/rk3399_dmc.c
+++ b/drivers/devfreq/rk3399_dmc.c
@@ -23,38 +23,6 @@
#include <soc/rockchip/rk3399_grf.h>
#include <soc/rockchip/rockchip_sip.h>
-struct dram_timing {
- unsigned int ddr3_speed_bin;
- unsigned int pd_idle;
- unsigned int sr_idle;
- unsigned int sr_mc_gate_idle;
- unsigned int srpd_lite_idle;
- unsigned int standby_idle;
- unsigned int auto_pd_dis_freq;
- unsigned int dram_dll_dis_freq;
- unsigned int phy_dll_dis_freq;
- unsigned int ddr3_odt_dis_freq;
- unsigned int ddr3_drv;
- unsigned int ddr3_odt;
- unsigned int phy_ddr3_ca_drv;
- unsigned int phy_ddr3_dq_drv;
- unsigned int phy_ddr3_odt;
- unsigned int lpddr3_odt_dis_freq;
- unsigned int lpddr3_drv;
- unsigned int lpddr3_odt;
- unsigned int phy_lpddr3_ca_drv;
- unsigned int phy_lpddr3_dq_drv;
- unsigned int phy_lpddr3_odt;
- unsigned int lpddr4_odt_dis_freq;
- unsigned int lpddr4_drv;
- unsigned int lpddr4_dq_odt;
- unsigned int lpddr4_ca_odt;
- unsigned int phy_lpddr4_ca_drv;
- unsigned int phy_lpddr4_ck_cs_drv;
- unsigned int phy_lpddr4_dq_drv;
- unsigned int phy_lpddr4_odt;
-};
-
struct rk3399_dmcfreq {
struct device *dev;
struct devfreq *devfreq;
@@ -62,13 +30,21 @@ struct rk3399_dmcfreq {
struct clk *dmc_clk;
struct devfreq_event_dev *edev;
struct mutex lock;
- struct dram_timing timing;
struct regulator *vdd_center;
struct regmap *regmap_pmu;
unsigned long rate, target_rate;
unsigned long volt, target_volt;
unsigned int odt_dis_freq;
int odt_pd_arg0, odt_pd_arg1;
+
+ unsigned int pd_idle;
+ unsigned int sr_idle;
+ unsigned int sr_mc_gate_idle;
+ unsigned int srpd_lite_idle;
+ unsigned int standby_idle;
+ unsigned int ddr3_odt_dis_freq;
+ unsigned int lpddr3_odt_dis_freq;
+ unsigned int lpddr4_odt_dis_freq;
};
static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
@@ -238,69 +214,27 @@ static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
rk3399_dmcfreq_resume);
-static int of_get_ddr_timings(struct dram_timing *timing,
- struct device_node *np)
+static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data,
+ struct device_node *np)
{
int ret = 0;
- ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
- &timing->ddr3_speed_bin);
ret |= of_property_read_u32(np, "rockchip,pd_idle",
- &timing->pd_idle);
+ &data->pd_idle);
ret |= of_property_read_u32(np, "rockchip,sr_idle",
- &timing->sr_idle);
+ &data->sr_idle);
ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
- &timing->sr_mc_gate_idle);
+ &data->sr_mc_gate_idle);
ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
- &timing->srpd_lite_idle);
+ &data->srpd_lite_idle);
ret |= of_property_read_u32(np, "rockchip,standby_idle",
- &timing->standby_idle);
- ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
- &timing->auto_pd_dis_freq);
- ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
- &timing->dram_dll_dis_freq);
- ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
- &timing->phy_dll_dis_freq);
+ &data->standby_idle);
ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
- &timing->ddr3_odt_dis_freq);
- ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
- &timing->ddr3_drv);
- ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
- &timing->ddr3_odt);
- ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
- &timing->phy_ddr3_ca_drv);
- ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
- &timing->phy_ddr3_dq_drv);
- ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
- &timing->phy_ddr3_odt);
+ &data->ddr3_odt_dis_freq);
ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
- &timing->lpddr3_odt_dis_freq);
- ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
- &timing->lpddr3_drv);
- ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
- &timing->lpddr3_odt);
- ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
- &timing->phy_lpddr3_ca_drv);
- ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
- &timing->phy_lpddr3_dq_drv);
- ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
- &timing->phy_lpddr3_odt);
+ &data->lpddr3_odt_dis_freq);
ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
- &timing->lpddr4_odt_dis_freq);
- ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
- &timing->lpddr4_drv);
- ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
- &timing->lpddr4_dq_odt);
- ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
- &timing->lpddr4_ca_odt);
- ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
- &timing->phy_lpddr4_ca_drv);
- ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
- &timing->phy_lpddr4_ck_cs_drv);
- ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
- &timing->phy_lpddr4_dq_drv);
- ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
- &timing->phy_lpddr4_odt);
+ &data->lpddr4_odt_dis_freq);
return ret;
}
@@ -311,8 +245,7 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = pdev->dev.of_node, *node;
struct rk3399_dmcfreq *data;
- int ret, index, size;
- uint32_t *timing;
+ int ret;
struct dev_pm_opp *opp;
u32 ddr_type;
u32 val;
@@ -343,26 +276,7 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
return ret;
}
- /*
- * Get dram timing and pass it to arm trust firmware,
- * the dram driver in arm trust firmware will get these
- * timing and to do dram initial.
- */
- if (!of_get_ddr_timings(&data->timing, np)) {
- timing = &data->timing.ddr3_speed_bin;
- size = sizeof(struct dram_timing) / 4;
- for (index = 0; index < size; index++) {
- arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
- ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
- 0, 0, 0, 0, &res);
- if (res.a0) {
- dev_err(dev, "Failed to set dram param: %ld\n",
- res.a0);
- ret = -EINVAL;
- goto err_edev;
- }
- }
- }
+ rk3399_dmcfreq_of_props(data, np);
node = of_parse_phandle(np, "rockchip,pmu", 0);
if (!node)
@@ -381,13 +295,13 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
switch (ddr_type) {
case RK3399_PMUGRF_DDRTYPE_DDR3:
- data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
+ data->odt_dis_freq = data->ddr3_odt_dis_freq;
break;
case RK3399_PMUGRF_DDRTYPE_LPDDR3:
- data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
+ data->odt_dis_freq = data->lpddr3_odt_dis_freq;
break;
case RK3399_PMUGRF_DDRTYPE_LPDDR4:
- data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
+ data->odt_dis_freq = data->lpddr4_odt_dis_freq;
break;
default:
ret = -EINVAL;
@@ -414,11 +328,11 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
* arg2:
* bit[0] : odt enable
*/
- data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) |
- ((data->timing.sr_mc_gate_idle & 0xff) << 8) |
- ((data->timing.standby_idle & 0xffff) << 16);
- data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) |
- ((data->timing.srpd_lite_idle & 0xfff) << 16);
+ data->odt_pd_arg0 = (data->sr_idle & 0xff) |
+ ((data->sr_mc_gate_idle & 0xff) << 8) |
+ ((data->standby_idle & 0xffff) << 16);
+ data->odt_pd_arg1 = (data->pd_idle & 0xfff) |
+ ((data->srpd_lite_idle & 0xfff) << 16);
/*
* We add a devfreq driver to our parent since it has a device tree node
--
2.34.1.575.g55b058a8bb-goog
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 07/10] PM / devfreq: rk3399_dmc: Use bitfield macro definitions for ODT_PD
2022-01-07 23:53 [PATCH 00/10] rk3399: Clean up and enable DDR DVFS Brian Norris
` (5 preceding siblings ...)
2022-01-07 23:53 ` [PATCH 06/10] PM / devfreq: rk3399_dmc: Drop excess timing properties Brian Norris
@ 2022-01-07 23:53 ` Brian Norris
2022-01-07 23:53 ` [PATCH 08/10] PM / devfreq: rk3399_dmc: Support new disable-freq properties Brian Norris
` (2 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Brian Norris @ 2022-01-07 23:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring
Cc: Heiko Stuebner, linux-arm-kernel, Lin Huang, devicetree,
linux-rockchip, linux-pm, Derek Basehore, linux-kernel,
Brian Norris
We're going to add new usages, and it's cleaner to work with macros
instead of comments and magic numbers.
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
drivers/devfreq/rk3399_dmc.c | 43 ++++++++++++++++++++----------------
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
index 8f447217303f..c4efbc15cbb1 100644
--- a/drivers/devfreq/rk3399_dmc.c
+++ b/drivers/devfreq/rk3399_dmc.c
@@ -5,6 +5,7 @@
*/
#include <linux/arm-smccc.h>
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/devfreq.h>
@@ -23,6 +24,15 @@
#include <soc/rockchip/rk3399_grf.h>
#include <soc/rockchip/rockchip_sip.h>
+#define RK3399_SET_ODT_PD_0_SR_IDLE GENMASK(7, 0)
+#define RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE GENMASK(15, 8)
+#define RK3399_SET_ODT_PD_0_STANDBY_IDLE GENMASK(31, 16)
+
+#define RK3399_SET_ODT_PD_1_PD_IDLE GENMASK(11, 0)
+#define RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE GENMASK(27, 16)
+
+#define RK3399_SET_ODT_PD_2_ODT_ENABLE BIT(0)
+
struct rk3399_dmcfreq {
struct device *dev;
struct devfreq *devfreq;
@@ -55,7 +65,6 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
unsigned long old_clk_rate = dmcfreq->rate;
unsigned long target_volt, target_rate;
struct arm_smccc_res res;
- bool odt_enable = false;
int err;
opp = devfreq_recommended_opp(dev, freq, flags);
@@ -72,8 +81,10 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
mutex_lock(&dmcfreq->lock);
if (dmcfreq->regmap_pmu) {
+ unsigned int odt_pd_arg2 = 0;
+
if (target_rate >= dmcfreq->odt_dis_freq)
- odt_enable = true;
+ odt_pd_arg2 |= RK3399_SET_ODT_PD_2_ODT_ENABLE;
/*
* This makes a SMC call to the TF-A to set the DDR PD
@@ -83,7 +94,7 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
dmcfreq->odt_pd_arg1,
ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
- odt_enable, 0, 0, 0, &res);
+ odt_pd_arg2, 0, 0, 0, &res);
}
/*
@@ -316,23 +327,17 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
/*
* In TF-A there is a platform SIP call to set the PD (power-down)
* timings and to enable or disable the ODT (on-die termination).
- * This call needs three arguments as follows:
- *
- * arg0:
- * bit[0-7] : sr_idle
- * bit[8-15] : sr_mc_gate_idle
- * bit[16-31] : standby idle
- * arg1:
- * bit[0-11] : pd_idle
- * bit[16-27] : srpd_lite_idle
- * arg2:
- * bit[0] : odt enable
*/
- data->odt_pd_arg0 = (data->sr_idle & 0xff) |
- ((data->sr_mc_gate_idle & 0xff) << 8) |
- ((data->standby_idle & 0xffff) << 16);
- data->odt_pd_arg1 = (data->pd_idle & 0xfff) |
- ((data->srpd_lite_idle & 0xfff) << 16);
+ data->odt_pd_arg0 =
+ FIELD_PREP(RK3399_SET_ODT_PD_0_SR_IDLE, data->sr_idle) |
+ FIELD_PREP(RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE,
+ data->sr_mc_gate_idle) |
+ FIELD_PREP(RK3399_SET_ODT_PD_0_STANDBY_IDLE,
+ data->standby_idle);
+ data->odt_pd_arg1 =
+ FIELD_PREP(RK3399_SET_ODT_PD_1_PD_IDLE, data->pd_idle) |
+ FIELD_PREP(RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE,
+ data->srpd_lite_idle);
/*
* We add a devfreq driver to our parent since it has a device tree node
--
2.34.1.575.g55b058a8bb-goog
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 08/10] PM / devfreq: rk3399_dmc: Support new disable-freq properties
2022-01-07 23:53 [PATCH 00/10] rk3399: Clean up and enable DDR DVFS Brian Norris
` (6 preceding siblings ...)
2022-01-07 23:53 ` [PATCH 07/10] PM / devfreq: rk3399_dmc: Use bitfield macro definitions for ODT_PD Brian Norris
@ 2022-01-07 23:53 ` Brian Norris
2022-01-07 23:53 ` [PATCH 09/10] arm64: dts: rk3399: Add dfi and dmc nodes Brian Norris
2022-01-07 23:53 ` [PATCH 10/10] arm64: dts: rockchip: Enable dmc and dfi nodes on gru Brian Norris
9 siblings, 0 replies; 16+ messages in thread
From: Brian Norris @ 2022-01-07 23:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring
Cc: Heiko Stuebner, linux-arm-kernel, Lin Huang, devicetree,
linux-rockchip, linux-pm, Derek Basehore, linux-kernel,
Brian Norris
Implement the newly-defined properties to allow disabling certain
power-saving-at-idle features at higher frequencies.
This is a rewritten version of work by Lin Huang <hl@rock-chips.com>.
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
drivers/devfreq/rk3399_dmc.c | 51 +++++++++++++++++++++++++++++++++---
1 file changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
index c4efbc15cbb1..58a4970918be 100644
--- a/drivers/devfreq/rk3399_dmc.c
+++ b/drivers/devfreq/rk3399_dmc.c
@@ -55,6 +55,12 @@ struct rk3399_dmcfreq {
unsigned int ddr3_odt_dis_freq;
unsigned int lpddr3_odt_dis_freq;
unsigned int lpddr4_odt_dis_freq;
+
+ unsigned int pd_idle_dis_freq;
+ unsigned int sr_idle_dis_freq;
+ unsigned int sr_mc_gate_idle_dis_freq;
+ unsigned int srpd_lite_idle_dis_freq;
+ unsigned int standby_idle_dis_freq;
};
static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
@@ -81,8 +87,25 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
mutex_lock(&dmcfreq->lock);
if (dmcfreq->regmap_pmu) {
+ unsigned int odt_pd_arg0 = dmcfreq->odt_pd_arg0;
+ unsigned int odt_pd_arg1 = dmcfreq->odt_pd_arg1;
unsigned int odt_pd_arg2 = 0;
+ if (target_rate >= dmcfreq->sr_idle_dis_freq)
+ odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_SR_IDLE;
+
+ if (target_rate >= dmcfreq->sr_mc_gate_idle_dis_freq)
+ odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE;
+
+ if (target_rate >= dmcfreq->standby_idle_dis_freq)
+ odt_pd_arg0 &= ~RK3399_SET_ODT_PD_0_STANDBY_IDLE;
+
+ if (target_rate >= dmcfreq->pd_idle_dis_freq)
+ odt_pd_arg1 &= ~RK3399_SET_ODT_PD_1_PD_IDLE;
+
+ if (target_rate >= dmcfreq->srpd_lite_idle_dis_freq)
+ odt_pd_arg1 &= ~RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE;
+
if (target_rate >= dmcfreq->odt_dis_freq)
odt_pd_arg2 |= RK3399_SET_ODT_PD_2_ODT_ENABLE;
@@ -91,10 +114,9 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
* (power-down) timings and to enable or disable the
* ODT (on-die termination) resistors.
*/
- arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
- dmcfreq->odt_pd_arg1,
- ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
- odt_pd_arg2, 0, 0, 0, &res);
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, odt_pd_arg0, odt_pd_arg1,
+ ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, odt_pd_arg2,
+ 0, 0, 0, &res);
}
/*
@@ -230,6 +252,16 @@ static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data,
{
int ret = 0;
+ /*
+ * These are all optional, and serve as minimum bounds. Give them large
+ * (i.e., never "disabled") values if the DT doesn't specify one.
+ */
+ data->pd_idle_dis_freq =
+ data->sr_idle_dis_freq =
+ data->sr_mc_gate_idle_dis_freq =
+ data->srpd_lite_idle_dis_freq =
+ data->standby_idle_dis_freq = UINT_MAX;
+
ret |= of_property_read_u32(np, "rockchip,pd_idle",
&data->pd_idle);
ret |= of_property_read_u32(np, "rockchip,sr_idle",
@@ -247,6 +279,17 @@ static int rk3399_dmcfreq_of_props(struct rk3399_dmcfreq *data,
ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
&data->lpddr4_odt_dis_freq);
+ ret |= of_property_read_u32(np, "rockchip,pd_idle_dis_freq",
+ &data->pd_idle_dis_freq);
+ ret |= of_property_read_u32(np, "rockchip,sr_idle_dis_freq",
+ &data->sr_idle_dis_freq);
+ ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle_dis_freq",
+ &data->sr_mc_gate_idle_dis_freq);
+ ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle_dis_freq",
+ &data->srpd_lite_idle_dis_freq);
+ ret |= of_property_read_u32(np, "rockchip,standby_idle_dis_freq",
+ &data->standby_idle_dis_freq);
+
return ret;
}
--
2.34.1.575.g55b058a8bb-goog
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 09/10] arm64: dts: rk3399: Add dfi and dmc nodes
2022-01-07 23:53 [PATCH 00/10] rk3399: Clean up and enable DDR DVFS Brian Norris
` (7 preceding siblings ...)
2022-01-07 23:53 ` [PATCH 08/10] PM / devfreq: rk3399_dmc: Support new disable-freq properties Brian Norris
@ 2022-01-07 23:53 ` Brian Norris
2022-01-07 23:53 ` [PATCH 10/10] arm64: dts: rockchip: Enable dmc and dfi nodes on gru Brian Norris
9 siblings, 0 replies; 16+ messages in thread
From: Brian Norris @ 2022-01-07 23:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring
Cc: Heiko Stuebner, linux-arm-kernel, Lin Huang, devicetree,
linux-rockchip, linux-pm, Derek Basehore, linux-kernel,
Enric Balletbo i Serra, Gaël PORTAY, Daniel Lezcano,
Brian Norris
From: Lin Huang <hl@rock-chips.com>
These are required to support DDR DVFS on RK3399 platforms.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Gaël PORTAY <gael.portay@collabora.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
This is based on a v5 posting from various authors:
https://lore.kernel.org/lkml/20210308233858.24741-3-daniel.lezcano@linaro.org/
Much of that series was already merged, so I start over with the
numbering.
Change since Daniel's posting: reordered by unit address, per existing
style
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d3cdf6f42a30..86e2d87e008a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1295,6 +1295,25 @@ pwm3: pwm@ff420030 {
status = "disabled";
};
+ dfi: dfi@ff630000 {
+ reg = <0x00 0xff630000 0x00 0x4000>;
+ compatible = "rockchip,rk3399-dfi";
+ rockchip,pmu = <&pmugrf>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_DDR_MON>;
+ clock-names = "pclk_ddr_mon";
+ status = "disabled";
+ };
+
+ dmc: dmc {
+ compatible = "rockchip,rk3399-dmc";
+ rockchip,pmu = <&pmugrf>;
+ devfreq-events = <&dfi>;
+ clocks = <&cru SCLK_DDRC>;
+ clock-names = "dmc_clk";
+ status = "disabled";
+ };
+
vpu: video-codec@ff650000 {
compatible = "rockchip,rk3399-vpu";
reg = <0x0 0xff650000 0x0 0x800>;
--
2.34.1.575.g55b058a8bb-goog
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 10/10] arm64: dts: rockchip: Enable dmc and dfi nodes on gru
2022-01-07 23:53 [PATCH 00/10] rk3399: Clean up and enable DDR DVFS Brian Norris
` (8 preceding siblings ...)
2022-01-07 23:53 ` [PATCH 09/10] arm64: dts: rk3399: Add dfi and dmc nodes Brian Norris
@ 2022-01-07 23:53 ` Brian Norris
9 siblings, 0 replies; 16+ messages in thread
From: Brian Norris @ 2022-01-07 23:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring
Cc: Heiko Stuebner, linux-arm-kernel, Lin Huang, devicetree,
linux-rockchip, linux-pm, Derek Basehore, linux-kernel,
Enric Balletbo i Serra, Gaël PORTAY, Daniel Lezcano,
Brian Norris
From: Lin Huang <hl@rock-chips.com>
Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY
Interface) nodes on gru boards so we can support DDR DVFS.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Gaël PORTAY <gael.portay@collabora.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
This was part of a previous series, at:
https://lore.kernel.org/r/20210308233858.24741-3-daniel.lezcano@linaro.org
I've picked up a bunch of changes and fixes, so I've restarted the patch
series numbering.
Updates since the old series:
* reordered alphabetically by phandle name, per style
* drop a ton of deprecated/unused properties
* add required center-supply for scarlet
* add new *_idle_dis_freq properties
* drop the lowest (200 MHz) OPP; this was never stabilized for
production
* bump the voltage (0.9V -> 0.925V) for the highest OPP on Chromebook
models; later (tablet) models were more stable, with a fixed DDR
regulator
* bump odt_dis_freq to 666 MHz; early versions used 333 MHz, but
stabilization efforts landed on 666 MHz for production
.../dts/rockchip/rk3399-gru-chromebook.dtsi | 7 +++++
.../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 12 ++++++++
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 28 +++++++++++++++++++
.../boot/dts/rockchip/rk3399-op1-opp.dtsi | 25 +++++++++++++++++
4 files changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
index 9b2c679f5eca..46292fdceecb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
@@ -234,6 +234,13 @@ &cdn_dp {
extcon = <&usbc_extcon0>, <&usbc_extcon1>;
};
+&dmc {
+ center-supply = <&ppvar_centerlogic>;
+ rockchip,pd_idle_dis_freq = <800000000>;
+ rockchip,sr_idle_dis_freq = <800000000>;
+ rockchip,sr_mc_gate_idle_dis_freq = <800000000>;
+};
+
&edp {
status = "okay";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
index a9817b3d7edc..913d845eb51a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
@@ -391,6 +391,18 @@ &cru {
<400000000>;
};
+/* The center supply is fixed to .9V on scarlet */
+&dmc {
+ center-supply = <&pp900_s0>;
+};
+
+/* We don't need .925 V for 928 MHz on scarlet */
+&dmc_opp_table {
+ opp03 {
+ opp-microvolt = <900000>;
+ };
+};
+
&gpio0 {
gpio-line-names = /* GPIO0 A 0-7 */
"CLK_32K_AP",
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 45a5ae5d2027..58b8d332f924 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -373,6 +373,34 @@ &cru {
<200000000>;
};
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ status = "okay";
+ rockchip,pd_idle = <0x40>;
+ rockchip,sr_idle = <0x2>;
+ rockchip,sr_mc_gate_idle = <0x3>;
+ rockchip,srpd_lite_idle = <0x4>;
+ rockchip,standby_idle = <0x2000>;
+ rockchip,ddr3_odt_dis_freq = <666000000>;
+ rockchip,lpddr3_odt_dis_freq = <666000000>;
+ rockchip,lpddr4_odt_dis_freq = <666000000>;
+
+ rockchip,pd_idle_dis_freq = <1000000000>;
+ rockchip,sr_idle_dis_freq = <1000000000>;
+ rockchip,sr_mc_gate_idle_dis_freq = <1000000000>;
+ rockchip,srpd_lite_idle_dis_freq = <0>;
+ rockchip,standby_idle_dis_freq = <928000000>;
+};
+
+&dmc_opp_table {
+ opp03 {
+ opp-suspend;
+ };
+};
+
&emmc_phy {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
index 2180e0f75003..6e29e74f6fc6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
@@ -110,6 +110,27 @@ opp05 {
opp-microvolt = <1075000>;
};
};
+
+ dmc_opp_table: dmc_opp_table {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <900000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <666000000>;
+ opp-microvolt = <900000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <900000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <928000000>;
+ opp-microvolt = <925000>;
+ };
+ };
};
&cpu_l0 {
@@ -136,6 +157,10 @@ &cpu_b1 {
operating-points-v2 = <&cluster1_opp>;
};
+&dmc {
+ operating-points-v2 = <&dmc_opp_table>;
+};
+
&gpu {
operating-points-v2 = <&gpu_opp_table>;
};
--
2.34.1.575.g55b058a8bb-goog
^ permalink raw reply related [flat|nested] 16+ messages in thread