From: Stephen Boyd <sboyd@kernel.org>
To: Nikita Travkin <nikita@trvn.ru>,
linus.walleij@linaro.org, mturquette@baylibre.com
Cc: bjorn.andersson@linaro.org, agross@kernel.org,
tdas@codeaurora.org, joonwoop@codeaurora.org,
svarbanov@mm-sol.com, linux-arm-msm@vger.kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org,
~postmarketos/upstreaming@lists.sr.ht,
Nikita Travkin <nikita@trvn.ru>
Subject: Re: [PATCH 1/4] clk: qcom: clk-rcg2: Fail Duty-Cycle configuration if MND divider is not enabled.
Date: Fri, 07 Jan 2022 16:52:08 -0800 [thread overview]
Message-ID: <20220108005209.5140EC36AEB@smtp.kernel.org> (raw)
In-Reply-To: <20211209163720.106185-2-nikita@trvn.ru>
Quoting Nikita Travkin (2021-12-09 08:37:17)
> In cases when MND is not enabled (e.g. when only Half Integer Divider is
> used), setting D registers makes no effect. Fail instead of making
> ineffective write.
>
> Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG")
> Signed-off-by: Nikita Travkin <nikita@trvn.ru>
> ---
> drivers/clk/qcom/clk-rcg2.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index e1b1b426fae4..6964cf914b60 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -396,7 +396,7 @@ static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
> static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
> {
> struct clk_rcg2 *rcg = to_clk_rcg2(hw);
> - u32 notn_m, n, m, d, not2d, mask, duty_per;
> + u32 notn_m, n, m, d, not2d, mask, duty_per, cfg;
> int ret;
>
> /* Duty-cycle cannot be modified for non-MND RCGs */
> @@ -407,6 +407,11 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
>
> regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
> regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
> + regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
> +
> + /* Duty-cycle cannot be modified if MND divider is in bypass mode. */
> + if (!(cfg & CFG_MODE_MASK))
> + return -EINVAL;
Should we still allow 50% duty cycle to succeed?
next prev parent reply other threads:[~2022-01-08 0:52 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-09 16:37 [PATCH 0/4] Prepare general purpose clocks on msm8916 Nikita Travkin
2021-12-09 16:37 ` [PATCH 1/4] clk: qcom: clk-rcg2: Fail Duty-Cycle configuration if MND divider is not enabled Nikita Travkin
2022-01-08 0:52 ` Stephen Boyd [this message]
2022-01-08 7:25 ` Nikita Travkin
2022-01-10 20:14 ` Stephen Boyd
2022-01-26 15:14 ` Nikita Travkin
2022-02-17 22:37 ` Stephen Boyd
2022-02-19 6:32 ` Nikita Travkin
2021-12-09 16:37 ` [PATCH 2/4] clk: qcom: clk-rcg2: Make sure to not write d=0 to the NMD register Nikita Travkin
2022-01-08 0:56 ` Stephen Boyd
2022-01-08 7:29 ` Nikita Travkin
2021-12-09 16:37 ` [PATCH 3/4] pinctrl: qcom: msm8916: Allow CAMSS GP clocks to be muxed Nikita Travkin
2021-12-09 16:37 ` [PATCH 4/4] clk: qcom: gcc-msm8916: Add rates to the GP clocks Nikita Travkin
2022-01-08 0:53 ` Stephen Boyd
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