From: James Clark <james.clark@arm.com>
To: mathieu.poirier@linaro.org, coresight@lists.linaro.org
Cc: suzuki.poulose@arm.com, leo.yan@linaro.com,
mike.leach@linaro.org, James Clark <james.clark@arm.com>,
Leo Yan <leo.yan@linaro.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 15/15] coresight: Make ETM4x TRCRSCTLRn register accesses consistent with sysreg.h
Date: Wed, 2 Feb 2022 16:02:25 +0000 [thread overview]
Message-ID: <20220202160226.37858-16-james.clark@arm.com> (raw)
In-Reply-To: <20220202160226.37858-1-james.clark@arm.com>
This is a no-op change for style and consistency and has no effect on the
binary produced by gcc-11.
Signed-off-by: James Clark <james.clark@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 7 +++++--
drivers/hwtracing/coresight/coresight-etm4x.h | 9 +++++++++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index a0cdd2cd978a..c876a63fa84d 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -1728,8 +1728,11 @@ static ssize_t res_ctrl_store(struct device *dev,
/* For odd idx pair inversal bit is RES0 */
if (idx % 2 != 0)
/* PAIRINV, bit[21] */
- val &= ~BIT(21);
- config->res_ctrl[idx] = val & GENMASK(21, 0);
+ val &= ~TRCRSCTLRn_PAIRINV;
+ config->res_ctrl[idx] = val & (TRCRSCTLRn_PAIRINV |
+ TRCRSCTLRn_INV |
+ (TRCRSCTLRn_GROUP_MASK << TRCRSCTLRn_GROUP_SHIFT) |
+ (TRCRSCTLRn_SELECT_MASK << TRCRSCTLRn_SELECT_SHIFT));
spin_unlock(&drvdata->spinlock);
return size;
}
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 4d943faade33..dd2156a5e70b 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -258,6 +258,15 @@
#define TRCBBCTLR_RANGE_SHIFT 0
#define TRCBBCTLR_RANGE_MASK GENMASK(7, 0)
+#define TRCRSCTLRn_PAIRINV BIT(21)
+#define TRCRSCTLRn_INV BIT(20)
+#define TRCRSCTLRn_GROUP_SHIFT 16
+#define TRCRSCTLRn_GROUP_MASK GENMASK(3, 0)
+#define TRCRSCTLRn_SELECT_SHIFT 0
+#define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0)
+
+
+
/*
* System instructions to access ETM registers.
* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
--
2.28.0
prev parent reply other threads:[~2022-02-02 16:03 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-02 16:02 [PATCH 00/15] Make ETM register accesses consistent with sysreg.h James Clark
2022-02-02 16:02 ` [PATCH 01/15] coresight: Make ETM4x TRCIDR0 " James Clark
2022-02-02 17:05 ` Suzuki K Poulose
2022-02-03 10:40 ` James Clark
2022-02-03 10:54 ` Suzuki K Poulose
2022-02-03 12:08 ` James Clark
2022-02-02 16:02 ` [PATCH 02/15] coresight: Make ETM4x TRCIDR2 " James Clark
2022-02-03 13:58 ` Suzuki K Poulose
2022-02-03 14:27 ` Suzuki K Poulose
2022-02-02 16:02 ` [PATCH 03/15] coresight: Make ETM4x TRCIDR3 " James Clark
2022-02-02 16:02 ` [PATCH 04/15] coresight: Make ETM4x TRCIDR4 " James Clark
2022-02-02 16:02 ` [PATCH 05/15] coresight: Make ETM4x TRCIDR5 " James Clark
2022-02-02 16:02 ` [PATCH 06/15] coresight: Make ETM4x TRCCONFIGR " James Clark
2022-02-02 16:02 ` [PATCH 07/15] coresight: Make ETM4x TRCEVENTCTL1R " James Clark
2022-02-02 16:02 ` [PATCH 08/15] coresight: Make ETM4x TRCSTALLCTLR " James Clark
2022-02-02 16:02 ` [PATCH 09/15] coresight: Make ETM4x TRCVICTLR " James Clark
2022-02-02 16:02 ` [PATCH 10/15] coresight: Make ETM3x ETMTECR1 " James Clark
2022-02-02 16:02 ` [PATCH 11/15] coresight: Make ETM4x TRCACATRn " James Clark
2022-02-02 16:02 ` [PATCH 12/15] coresight: Make ETM4x TRCSSCCRn and TRCSSCSRn " James Clark
2022-02-02 16:02 ` [PATCH 13/15] coresight: Make ETM4x TRCSSPCICRn " James Clark
2022-02-02 16:02 ` [PATCH 14/15] coresight: Make ETM4x TRCBBCTLR " James Clark
2022-02-02 16:02 ` James Clark [this message]
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