* [PATCH v3 0/2] pinctrl: mediatek: Support pinctrl driver on mt8186
@ 2022-02-10 6:21 Guodong Liu
2022-02-10 6:21 ` [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document Guodong Liu
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Guodong Liu @ 2022-02-10 6:21 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Guodong Liu
changes since v2:
- update reg property
- update reg-names property
- sync rsel resistance selection property same as patch 3
- repair constraints is not indented correctly for bias-pull-{up,down}
- add "type: boolean" to the list of valid values. This corresponds to having bias-pull-{up,down} without any arguments.
- add dual file license for file "mt8186-pinfunc.h"
- add patch 3 to change "mediatek,rsel_resistance_in_si_unit" to "mediatek,rsel-resistance-in-si-unit"
changes since v1:
- add default pinctrl config to consistent with other MTK pinctrl drivers
Patch 1 add pinctrl file and binding document.
Patch 2 add pinctrl chip driver on mt8186.
Patch 3 canonical rsel resistance selection property.
Guodong Liu (3):
dt-bindings: pinctrl: mt8186: add pinctrl file and binding document
pinctrl: add pinctrl driver on mt8186
pinctrl: canonical rsel resistance selection property
.../bindings/pinctrl/pinctrl-mt8186.yaml | 313 +++
drivers/pinctrl/mediatek/Kconfig | 7 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8186.c | 1313 ++++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h | 2186 +++++++++++++++++
drivers/pinctrl/mediatek/pinctrl-paris.c | 2 +-
include/dt-bindings/pinctrl/mt8186-pinfunc.h | 1174 +++++++++
7 files changed, 4995 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8186.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
create mode 100644 include/dt-bindings/pinctrl/mt8186-pinfunc.h
--
2.25.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document
2022-02-10 6:21 [PATCH v3 0/2] pinctrl: mediatek: Support pinctrl driver on mt8186 Guodong Liu
@ 2022-02-10 6:21 ` Guodong Liu
2022-02-10 14:47 ` Rob Herring
` (2 more replies)
2022-02-10 6:21 ` [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186 Guodong Liu
2022-02-10 6:21 ` [PATCH v3 3/3] pinctrl: canonical rsel resistance selection property Guodong Liu
2 siblings, 3 replies; 13+ messages in thread
From: Guodong Liu @ 2022-02-10 6:21 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Guodong Liu
1. This patch adds pinctrl file for mt8186.
2. This patch adds mt8186 compatible node in binding document.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
---
.../bindings/pinctrl/pinctrl-mt8186.yaml | 313 +++++
include/dt-bindings/pinctrl/mt8186-pinfunc.h | 1174 +++++++++++++++++
2 files changed, 1487 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
create mode 100644 include/dt-bindings/pinctrl/mt8186-pinfunc.h
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
new file mode 100644
index 000000000000..54c9508af922
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
@@ -0,0 +1,313 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT8186 Pin Controller
+
+maintainers:
+ - Sean Wang <sean.wang@mediatek.com>
+
+description: |
+ The Mediatek's Pin controller is used to control SoC pins.
+
+properties:
+ compatible:
+ const: mediatek,mt8186-pinctrl
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: |
+ Number of cells in GPIO specifier. Since the generic GPIO binding is used,
+ the amount of cells must be specified as 2. See the below
+ mentioned gpio binding representation for description of particular cells.
+ const: 2
+
+ gpio-ranges:
+ description: gpio valid number range.
+ maxItems: 1
+
+ reg:
+ description: |
+ Physical address base for gpio base registers. There are 8 different GPIO
+ physical address base in mt8186.
+ maxItems: 8
+
+ reg-names:
+ description: |
+ Gpio base register names.
+ items:
+ - const: "iocfg0"
+ - const: "iocfg_bm"
+ - const: "iocfg_bl"
+ - const: "iocfg_br"
+ - const: "iocfg_lm"
+ - const: "iocfg_rb"
+ - const: "iocfg_tl"
+ - const: "eint"
+ maxItems: 8
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupts:
+ description: The interrupt outputs to sysirq.
+ maxItems: 1
+
+ mediatek,rsel-resistance-in-si-unit:
+ type: boolean
+ description: |
+ Identifying i2c pins pull up/down type which is RSEL. It can support
+ RSEL define or si unit value(ohm) to set different resistance.
+
+# PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '^pins':
+ type: object
+ additionalProperties: false
+ description: |
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to muxer
+ configuration, pullups, drive strength, input enable/disable and
+ input schmitt.
+ An example of using macro:
+ pincontroller {
+ /* GPIO0 set as multifunction GPIO0 */
+ gpio-pins {
+ pins {
+ pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
+ }
+ };
+ /* GPIO128 set as multifunction SDA0 */
+ i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
+ }
+ };
+ };
+ $ref: "pinmux-node.yaml"
+
+ properties:
+ pinmux:
+ description: |
+ Integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are
+ defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
+ directly.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+ mediatek,drive-strength-adv:
+ description: |
+ Describe the specific driving setup property.
+ For I2C pins, the existing generic driving setup can only support
+ 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
+ can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
+ driving setup, the existing generic setup will be disabled.
+ The specific driving setup is controlled by E1E0EN.
+ When E1=0/E0=0, the strength is 0.125mA.
+ When E1=0/E0=1, the strength is 0.25mA.
+ When E1=1/E0=0, the strength is 0.5mA.
+ When E1=1/E0=1, the strength is 1mA.
+ EN is used to enable or disable the specific driving setup.
+ Valid arguments are described as below:
+ 0: (E1, E0, EN) = (0, 0, 0)
+ 1: (E1, E0, EN) = (0, 0, 1)
+ 2: (E1, E0, EN) = (0, 1, 0)
+ 3: (E1, E0, EN) = (0, 1, 1)
+ 4: (E1, E0, EN) = (1, 0, 0)
+ 5: (E1, E0, EN) = (1, 0, 1)
+ 6: (E1, E0, EN) = (1, 1, 0)
+ 7: (E1, E0, EN) = (1, 1, 1)
+ So the valid arguments are from 0 to 7.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+
+ bias-pull-down:
+ oneOf:
+ - enum: [100, 101, 102, 103]
+ - description: mt8186 pull down PUPD/R0/R1 type define value.
+ - enum: [200, 201, 202, 203, 204, 205, 206, 207]
+ - description: mt8186 pull down RSEL type define value.
+ - enum: [75000, 5000]
+ - description: mt8186 pull down RSEL type si unit value(ohm).
+
+ description: |
+ For pull down type is normal, it don't need add RSEL & R1R0 define
+ and resistance value.
+ For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
+ set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
+ "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
+ "MTK_PUPD_SET_R1R0_11" define in mt8186.
+ For pull down type is RSEL, it can add RSEL define & resistance
+ value(ohm) to set different resistance by identifying property
+ "mediatek,rsel-resistance-in-si-unit".
+ It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
+ & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
+ & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
+ & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
+ define in mt8186. It can also support resistance value(ohm)
+ "75000" & "5000" in mt8186.
+ An example of using RSEL define:
+ pincontroller {
+ i2c0_pin {
+ pins {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
+ bias-pull-down = <MTK_PULL_SET_RSEL_001>;
+ }
+ };
+ };
+ An example of using si unit resistance value(ohm):
+ &pio {
+ mediatek,rsel-resistance-in-si-unit;
+ }
+ pincontroller {
+ i2c0_pin {
+ pins {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
+ bias-pull-down = <75000>;
+ }
+ };
+ };
+
+ bias-pull-up:
+ oneOf:
+ - enum: [100, 101, 102, 103]
+ - description: mt8186 pull up PUPD/R0/R1 type define value.
+ - enum: [200, 201, 202, 203, 204, 205, 206, 207]
+ - description: mt8186 pull up RSEL type define value.
+ - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
+ - description: mt8186 pull up RSEL type si unit value(ohm).
+
+ description: |
+ For pull up type is normal, it don't need add RSEL & R1R0 define
+ and resistance value.
+ For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
+ set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
+ "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
+ "MTK_PUPD_SET_R1R0_11" define in mt8186.
+ For pull up type is RSEL, it can add RSEL define & resistance
+ value(ohm) to set different resistance by identifying property
+ "mediatek,rsel-resistance-in-si-unit".
+ It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
+ & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
+ & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
+ & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
+ define in mt8186. It can also support resistance value(ohm)
+ "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" &
+ "75000" in mt8186.
+ An example of using RSEL define:
+ pincontroller {
+ i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_001>;
+ }
+ };
+ };
+ An example of using si unit resistance value(ohm):
+ &pio {
+ mediatek,rsel-resistance-in-si-unit;
+ }
+ pincontroller {
+ i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
+ bias-pull-up = <1000>;
+ }
+ };
+ };
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ input-enable: true
+
+ input-disable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ required:
+ - pinmux
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8186-pinctrl";
+ reg = <0x10005000 0x1000>,
+ <0x10002000 0x0200>,
+ <0x10002200 0x0200>,
+ <0x10002400 0x0200>,
+ <0x10002600 0x0200>,
+ <0x10002A00 0x0200>,
+ <0x10002c00 0x0200>,
+ <0x1000b000 0x1000>;
+ reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
+ "iocfg_br", "iocfg_lm", "iocfg_rb",
+ "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 185>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
+ #interrupt-cells = <2>;
+
+ pio-pins {
+ pins {
+ pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
+ output-low;
+ };
+ };
+
+ spi0-pins {
+ pins-spi {
+ pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>,
+ <PINMUX_GPIO1__FUNC_SPI0_CSB_B>,
+ <PINMUX_GPIO2__FUNC_SPI0_MO_B>;
+ bias-disable;
+ };
+ pins-spi-mi {
+ pinmux = <PINMUX_GPIO3__FUNC_SPI0_MI_B>;
+ bias-pull-down;
+ };
+ };
+
+ i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO127__FUNC_SCL0>,
+ <PINMUX_GPIO128__FUNC_SDA0>;
+ bias-disable;
+ mediatek,drive-strength-adv = <7>;
+ };
+ };
+ };
diff --git a/include/dt-bindings/pinctrl/mt8186-pinfunc.h b/include/dt-bindings/pinctrl/mt8186-pinfunc.h
new file mode 100644
index 000000000000..dcff86201a61
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mt8186-pinfunc.h
@@ -0,0 +1,1174 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Guodong Liu <Guodong.Liu@mediatek.com>
+ *
+ */
+
+#ifndef __MT8168_PINFUNC_H
+#define __MT8168_PINFUNC_H
+
+#include "mt65xx.h"
+
+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define PINMUX_GPIO0__FUNC_I2S0_MCK (MTK_PIN_NO(0) | 1)
+#define PINMUX_GPIO0__FUNC_SPI0_CLK_B (MTK_PIN_NO(0) | 2)
+#define PINMUX_GPIO0__FUNC_I2S2_MCK (MTK_PIN_NO(0) | 3)
+#define PINMUX_GPIO0__FUNC_CMFLASH0 (MTK_PIN_NO(0) | 4)
+#define PINMUX_GPIO0__FUNC_SCP_SPI0_CK (MTK_PIN_NO(0) | 5)
+#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6)
+#define PINMUX_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7)
+
+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define PINMUX_GPIO1__FUNC_I2S0_BCK (MTK_PIN_NO(1) | 1)
+#define PINMUX_GPIO1__FUNC_SPI0_CSB_B (MTK_PIN_NO(1) | 2)
+#define PINMUX_GPIO1__FUNC_I2S2_BCK (MTK_PIN_NO(1) | 3)
+#define PINMUX_GPIO1__FUNC_CMFLASH1 (MTK_PIN_NO(1) | 4)
+#define PINMUX_GPIO1__FUNC_SCP_SPI0_CS (MTK_PIN_NO(1) | 5)
+#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6)
+
+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define PINMUX_GPIO2__FUNC_I2S0_LRCK (MTK_PIN_NO(2) | 1)
+#define PINMUX_GPIO2__FUNC_SPI0_MO_B (MTK_PIN_NO(2) | 2)
+#define PINMUX_GPIO2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3)
+#define PINMUX_GPIO2__FUNC_CMFLASH2 (MTK_PIN_NO(2) | 4)
+#define PINMUX_GPIO2__FUNC_SCP_SPI0_MO (MTK_PIN_NO(2) | 5)
+#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6)
+
+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define PINMUX_GPIO3__FUNC_I2S0_DI (MTK_PIN_NO(3) | 1)
+#define PINMUX_GPIO3__FUNC_SPI0_MI_B (MTK_PIN_NO(3) | 2)
+#define PINMUX_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3)
+#define PINMUX_GPIO3__FUNC_SRCLKENAI1 (MTK_PIN_NO(3) | 4)
+#define PINMUX_GPIO3__FUNC_SCP_SPI0_MI (MTK_PIN_NO(3) | 5)
+#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6)
+
+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define PINMUX_GPIO4__FUNC_I2S3_DO (MTK_PIN_NO(4) | 1)
+#define PINMUX_GPIO4__FUNC_I2S1_DO (MTK_PIN_NO(4) | 3)
+#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)
+
+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define PINMUX_GPIO5__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(5) | 1)
+#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)
+
+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define PINMUX_GPIO6__FUNC_I2S3_MCK (MTK_PIN_NO(6) | 1)
+#define PINMUX_GPIO6__FUNC_SPI1_CLK_B (MTK_PIN_NO(6) | 2)
+#define PINMUX_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3)
+#define PINMUX_GPIO6__FUNC_DPI_DATA22 (MTK_PIN_NO(6) | 4)
+#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)
+
+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define PINMUX_GPIO7__FUNC_I2S3_BCK (MTK_PIN_NO(7) | 1)
+#define PINMUX_GPIO7__FUNC_SPI1_CSB_B (MTK_PIN_NO(7) | 2)
+#define PINMUX_GPIO7__FUNC_I2S1_BCK (MTK_PIN_NO(7) | 3)
+#define PINMUX_GPIO7__FUNC_DPI_DATA23 (MTK_PIN_NO(7) | 4)
+#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)
+
+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define PINMUX_GPIO8__FUNC_I2S3_LRCK (MTK_PIN_NO(8) | 1)
+#define PINMUX_GPIO8__FUNC_SPI1_MO_B (MTK_PIN_NO(8) | 2)
+#define PINMUX_GPIO8__FUNC_I2S1_LRCK (MTK_PIN_NO(8) | 3)
+#define PINMUX_GPIO8__FUNC_CONN_UART0_RXD (MTK_PIN_NO(8) | 4)
+#define PINMUX_GPIO8__FUNC_SSPM_URXD_AO (MTK_PIN_NO(8) | 5)
+#define PINMUX_GPIO8__FUNC_ADSP_UART_RX (MTK_PIN_NO(8) | 6)
+#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 7)
+
+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define PINMUX_GPIO9__FUNC_I2S3_DO (MTK_PIN_NO(9) | 1)
+#define PINMUX_GPIO9__FUNC_SPI1_MI_B (MTK_PIN_NO(9) | 2)
+#define PINMUX_GPIO9__FUNC_I2S1_DO (MTK_PIN_NO(9) | 3)
+#define PINMUX_GPIO9__FUNC_CONN_UART0_TXD (MTK_PIN_NO(9) | 4)
+#define PINMUX_GPIO9__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(9) | 5)
+#define PINMUX_GPIO9__FUNC_ADSP_UART_TX (MTK_PIN_NO(9) | 6)
+#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(9) | 7)
+
+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define PINMUX_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 1)
+#define PINMUX_GPIO10__FUNC_SPI4_CLK_A (MTK_PIN_NO(10) | 2)
+#define PINMUX_GPIO10__FUNC_I2S2_MCK (MTK_PIN_NO(10) | 3)
+#define PINMUX_GPIO10__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(10) | 4)
+#define PINMUX_GPIO10__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(10) | 5)
+#define PINMUX_GPIO10__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(10) | 6)
+#define PINMUX_GPIO10__FUNC_CONN_MCU_TDI (MTK_PIN_NO(10) | 7)
+
+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define PINMUX_GPIO11__FUNC_I2S0_BCK (MTK_PIN_NO(11) | 1)
+#define PINMUX_GPIO11__FUNC_SPI4_CSB_A (MTK_PIN_NO(11) | 2)
+#define PINMUX_GPIO11__FUNC_I2S2_BCK (MTK_PIN_NO(11) | 3)
+#define PINMUX_GPIO11__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(11) | 4)
+#define PINMUX_GPIO11__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(11) | 5)
+#define PINMUX_GPIO11__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(11) | 6)
+#define PINMUX_GPIO11__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(11) | 7)
+
+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define PINMUX_GPIO12__FUNC_I2S0_LRCK (MTK_PIN_NO(12) | 1)
+#define PINMUX_GPIO12__FUNC_SPI4_MO_A (MTK_PIN_NO(12) | 2)
+#define PINMUX_GPIO12__FUNC_I2S2_LRCK (MTK_PIN_NO(12) | 3)
+#define PINMUX_GPIO12__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(12) | 4)
+#define PINMUX_GPIO12__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(12) | 5)
+#define PINMUX_GPIO12__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(12) | 6)
+#define PINMUX_GPIO12__FUNC_CONN_MCU_TCK (MTK_PIN_NO(12) | 7)
+
+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define PINMUX_GPIO13__FUNC_I2S0_DI (MTK_PIN_NO(13) | 1)
+#define PINMUX_GPIO13__FUNC_SPI4_MI_A (MTK_PIN_NO(13) | 2)
+#define PINMUX_GPIO13__FUNC_I2S2_DI (MTK_PIN_NO(13) | 3)
+#define PINMUX_GPIO13__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(13) | 4)
+#define PINMUX_GPIO13__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(13) | 5)
+#define PINMUX_GPIO13__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(13) | 6)
+#define PINMUX_GPIO13__FUNC_CONN_MCU_TDO (MTK_PIN_NO(13) | 7)
+
+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define PINMUX_GPIO14__FUNC_CLKM0 (MTK_PIN_NO(14) | 3)
+#define PINMUX_GPIO14__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(14) | 4)
+#define PINMUX_GPIO14__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(14) | 5)
+#define PINMUX_GPIO14__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(14) | 6)
+#define PINMUX_GPIO14__FUNC_CONN_MCU_TMS (MTK_PIN_NO(14) | 7)
+
+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define PINMUX_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 1)
+#define PINMUX_GPIO15__FUNC_SRCLKENAI1 (MTK_PIN_NO(15) | 2)
+#define PINMUX_GPIO15__FUNC_CLKM1 (MTK_PIN_NO(15) | 3)
+#define PINMUX_GPIO15__FUNC_PWM0 (MTK_PIN_NO(15) | 4)
+
+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define PINMUX_GPIO16__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(16) | 1)
+#define PINMUX_GPIO16__FUNC_SRCLKENAI0 (MTK_PIN_NO(16) | 2)
+#define PINMUX_GPIO16__FUNC_CLKM2 (MTK_PIN_NO(16) | 3)
+#define PINMUX_GPIO16__FUNC_PWM1 (MTK_PIN_NO(16) | 4)
+
+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define PINMUX_GPIO17__FUNC_CLKM3 (MTK_PIN_NO(17) | 3)
+#define PINMUX_GPIO17__FUNC_PWM2 (MTK_PIN_NO(17) | 4)
+#define PINMUX_GPIO17__FUNC_DBG_MON_A32 (MTK_PIN_NO(17) | 7)
+
+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define PINMUX_GPIO18__FUNC_CMVREF0 (MTK_PIN_NO(18) | 2)
+#define PINMUX_GPIO18__FUNC_SPI2_CLK_B (MTK_PIN_NO(18) | 6)
+#define PINMUX_GPIO18__FUNC_DBG_MON_A26 (MTK_PIN_NO(18) | 7)
+
+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define PINMUX_GPIO19__FUNC_CMVREF1 (MTK_PIN_NO(19) | 2)
+#define PINMUX_GPIO19__FUNC_ANT_SEL3 (MTK_PIN_NO(19) | 5)
+#define PINMUX_GPIO19__FUNC_SPI2_CSB_B (MTK_PIN_NO(19) | 6)
+#define PINMUX_GPIO19__FUNC_DBG_MON_A2 (MTK_PIN_NO(19) | 7)
+
+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define PINMUX_GPIO20__FUNC_CMVREF2 (MTK_PIN_NO(20) | 2)
+#define PINMUX_GPIO20__FUNC_ANT_SEL4 (MTK_PIN_NO(20) | 5)
+#define PINMUX_GPIO20__FUNC_SPI2_MO_B (MTK_PIN_NO(20) | 6)
+#define PINMUX_GPIO20__FUNC_DBG_MON_A3 (MTK_PIN_NO(20) | 7)
+
+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define PINMUX_GPIO21__FUNC_I2S0_MCK (MTK_PIN_NO(21) | 1)
+#define PINMUX_GPIO21__FUNC_I2S1_MCK (MTK_PIN_NO(21) | 2)
+#define PINMUX_GPIO21__FUNC_I2S3_MCK (MTK_PIN_NO(21) | 3)
+#define PINMUX_GPIO21__FUNC_ANT_SEL5 (MTK_PIN_NO(21) | 5)
+#define PINMUX_GPIO21__FUNC_SPI2_MI_B (MTK_PIN_NO(21) | 6)
+#define PINMUX_GPIO21__FUNC_DBG_MON_A4 (MTK_PIN_NO(21) | 7)
+
+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define PINMUX_GPIO22__FUNC_I2S0_BCK (MTK_PIN_NO(22) | 1)
+#define PINMUX_GPIO22__FUNC_I2S1_BCK (MTK_PIN_NO(22) | 2)
+#define PINMUX_GPIO22__FUNC_I2S3_BCK (MTK_PIN_NO(22) | 3)
+#define PINMUX_GPIO22__FUNC_TDM_RX_LRCK (MTK_PIN_NO(22) | 4)
+#define PINMUX_GPIO22__FUNC_ANT_SEL6 (MTK_PIN_NO(22) | 5)
+#define PINMUX_GPIO22__FUNC_DBG_MON_A5 (MTK_PIN_NO(22) | 7)
+
+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define PINMUX_GPIO23__FUNC_I2S0_LRCK (MTK_PIN_NO(23) | 1)
+#define PINMUX_GPIO23__FUNC_I2S1_LRCK (MTK_PIN_NO(23) | 2)
+#define PINMUX_GPIO23__FUNC_I2S3_LRCK (MTK_PIN_NO(23) | 3)
+#define PINMUX_GPIO23__FUNC_TDM_RX_BCK (MTK_PIN_NO(23) | 4)
+#define PINMUX_GPIO23__FUNC_ANT_SEL7 (MTK_PIN_NO(23) | 5)
+#define PINMUX_GPIO23__FUNC_DBG_MON_A6 (MTK_PIN_NO(23) | 7)
+
+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define PINMUX_GPIO24__FUNC_I2S0_DI (MTK_PIN_NO(24) | 1)
+#define PINMUX_GPIO24__FUNC_I2S1_DO (MTK_PIN_NO(24) | 2)
+#define PINMUX_GPIO24__FUNC_I2S3_DO (MTK_PIN_NO(24) | 3)
+#define PINMUX_GPIO24__FUNC_TDM_RX_MCK (MTK_PIN_NO(24) | 4)
+#define PINMUX_GPIO24__FUNC_DBG_MON_A7 (MTK_PIN_NO(24) | 7)
+
+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define PINMUX_GPIO25__FUNC_I2S2_MCK (MTK_PIN_NO(25) | 1)
+#define PINMUX_GPIO25__FUNC_PCM_CLK (MTK_PIN_NO(25) | 2)
+#define PINMUX_GPIO25__FUNC_SPI4_CLK_B (MTK_PIN_NO(25) | 3)
+#define PINMUX_GPIO25__FUNC_TDM_RX_DATA0 (MTK_PIN_NO(25) | 4)
+#define PINMUX_GPIO25__FUNC_DBG_MON_A8 (MTK_PIN_NO(25) | 7)
+
+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define PINMUX_GPIO26__FUNC_I2S2_BCK (MTK_PIN_NO(26) | 1)
+#define PINMUX_GPIO26__FUNC_PCM_SYNC (MTK_PIN_NO(26) | 2)
+#define PINMUX_GPIO26__FUNC_SPI4_CSB_B (MTK_PIN_NO(26) | 3)
+#define PINMUX_GPIO26__FUNC_TDM_RX_DATA1 (MTK_PIN_NO(26) | 4)
+#define PINMUX_GPIO26__FUNC_DBG_MON_A9 (MTK_PIN_NO(26) | 7)
+
+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define PINMUX_GPIO27__FUNC_I2S2_LRCK (MTK_PIN_NO(27) | 1)
+#define PINMUX_GPIO27__FUNC_PCM_DI (MTK_PIN_NO(27) | 2)
+#define PINMUX_GPIO27__FUNC_SPI4_MO_B (MTK_PIN_NO(27) | 3)
+#define PINMUX_GPIO27__FUNC_TDM_RX_DATA2 (MTK_PIN_NO(27) | 4)
+#define PINMUX_GPIO27__FUNC_DBG_MON_A10 (MTK_PIN_NO(27) | 7)
+
+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define PINMUX_GPIO28__FUNC_I2S2_DI (MTK_PIN_NO(28) | 1)
+#define PINMUX_GPIO28__FUNC_PCM_DO (MTK_PIN_NO(28) | 2)
+#define PINMUX_GPIO28__FUNC_SPI4_MI_B (MTK_PIN_NO(28) | 3)
+#define PINMUX_GPIO28__FUNC_TDM_RX_DATA3 (MTK_PIN_NO(28) | 4)
+
+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define PINMUX_GPIO29__FUNC_ANT_SEL0 (MTK_PIN_NO(29) | 1)
+#define PINMUX_GPIO29__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(29) | 2)
+
+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define PINMUX_GPIO30__FUNC_ANT_SEL1 (MTK_PIN_NO(30) | 1)
+
+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define PINMUX_GPIO31__FUNC_ANT_SEL2 (MTK_PIN_NO(31) | 1)
+#define PINMUX_GPIO31__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(31) | 2)
+#define PINMUX_GPIO31__FUNC_SRCLKENAI1 (MTK_PIN_NO(31) | 3)
+
+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define PINMUX_GPIO32__FUNC_URXD0 (MTK_PIN_NO(32) | 1)
+#define PINMUX_GPIO32__FUNC_UTXD0 (MTK_PIN_NO(32) | 2)
+#define PINMUX_GPIO32__FUNC_ADSP_UART_RX (MTK_PIN_NO(32) | 3)
+#define PINMUX_GPIO32__FUNC_TP_URXD1_AO (MTK_PIN_NO(32) | 4)
+
+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define PINMUX_GPIO33__FUNC_UTXD0 (MTK_PIN_NO(33) | 1)
+#define PINMUX_GPIO33__FUNC_URXD0 (MTK_PIN_NO(33) | 2)
+#define PINMUX_GPIO33__FUNC_ADSP_UART_TX (MTK_PIN_NO(33) | 3)
+#define PINMUX_GPIO33__FUNC_TP_UTXD1_AO (MTK_PIN_NO(33) | 4)
+
+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define PINMUX_GPIO34__FUNC_URXD1 (MTK_PIN_NO(34) | 1)
+#define PINMUX_GPIO34__FUNC_TP_URXD2_AO (MTK_PIN_NO(34) | 2)
+#define PINMUX_GPIO34__FUNC_SSPM_URXD_AO (MTK_PIN_NO(34) | 3)
+#define PINMUX_GPIO34__FUNC_ADSP_UART_RX (MTK_PIN_NO(34) | 4)
+#define PINMUX_GPIO34__FUNC_CONN_UART0_RXD (MTK_PIN_NO(34) | 5)
+
+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define PINMUX_GPIO35__FUNC_UTXD1 (MTK_PIN_NO(35) | 1)
+#define PINMUX_GPIO35__FUNC_TP_UTXD2_AO (MTK_PIN_NO(35) | 2)
+#define PINMUX_GPIO35__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(35) | 3)
+#define PINMUX_GPIO35__FUNC_ADSP_UART_TX (MTK_PIN_NO(35) | 4)
+#define PINMUX_GPIO35__FUNC_CONN_UART0_TXD (MTK_PIN_NO(35) | 5)
+#define PINMUX_GPIO35__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(35) | 6)
+
+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define PINMUX_GPIO36__FUNC_SPI0_CLK_A (MTK_PIN_NO(36) | 1)
+#define PINMUX_GPIO36__FUNC_CLKM0 (MTK_PIN_NO(36) | 2)
+#define PINMUX_GPIO36__FUNC_SCP_SPI0_CK (MTK_PIN_NO(36) | 4)
+#define PINMUX_GPIO36__FUNC_SPINOR_CK (MTK_PIN_NO(36) | 5)
+#define PINMUX_GPIO36__FUNC_DBG_MON_A11 (MTK_PIN_NO(36) | 7)
+
+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define PINMUX_GPIO37__FUNC_SPI0_CSB_A (MTK_PIN_NO(37) | 1)
+#define PINMUX_GPIO37__FUNC_CLKM1 (MTK_PIN_NO(37) | 2)
+#define PINMUX_GPIO37__FUNC_PWM0 (MTK_PIN_NO(37) | 3)
+#define PINMUX_GPIO37__FUNC_SCP_SPI0_CS (MTK_PIN_NO(37) | 4)
+#define PINMUX_GPIO37__FUNC_SPINOR_CS (MTK_PIN_NO(37) | 5)
+#define PINMUX_GPIO37__FUNC_DBG_MON_A12 (MTK_PIN_NO(37) | 7)
+
+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define PINMUX_GPIO38__FUNC_SPI0_MO_A (MTK_PIN_NO(38) | 1)
+#define PINMUX_GPIO38__FUNC_CLKM2 (MTK_PIN_NO(38) | 2)
+#define PINMUX_GPIO38__FUNC_PWM1 (MTK_PIN_NO(38) | 3)
+#define PINMUX_GPIO38__FUNC_SCP_SPI0_MO (MTK_PIN_NO(38) | 4)
+#define PINMUX_GPIO38__FUNC_SPINOR_IO0 (MTK_PIN_NO(38) | 5)
+#define PINMUX_GPIO38__FUNC_DBG_MON_A13 (MTK_PIN_NO(38) | 7)
+
+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define PINMUX_GPIO39__FUNC_SPI0_MI_A (MTK_PIN_NO(39) | 1)
+#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 2)
+#define PINMUX_GPIO39__FUNC_PWM2 (MTK_PIN_NO(39) | 3)
+#define PINMUX_GPIO39__FUNC_SCP_SPI0_MI (MTK_PIN_NO(39) | 4)
+#define PINMUX_GPIO39__FUNC_SPINOR_IO1 (MTK_PIN_NO(39) | 5)
+#define PINMUX_GPIO39__FUNC_DBG_MON_A14 (MTK_PIN_NO(39) | 7)
+
+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define PINMUX_GPIO40__FUNC_SPI1_CLK_A (MTK_PIN_NO(40) | 1)
+#define PINMUX_GPIO40__FUNC_SCP_SPI1_CK (MTK_PIN_NO(40) | 2)
+#define PINMUX_GPIO40__FUNC_UCTS0 (MTK_PIN_NO(40) | 4)
+#define PINMUX_GPIO40__FUNC_SPINOR_IO2 (MTK_PIN_NO(40) | 5)
+#define PINMUX_GPIO40__FUNC_TP_UCTS1_AO (MTK_PIN_NO(40) | 6)
+#define PINMUX_GPIO40__FUNC_DBG_MON_A15 (MTK_PIN_NO(40) | 7)
+
+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define PINMUX_GPIO41__FUNC_SPI1_CSB_A (MTK_PIN_NO(41) | 1)
+#define PINMUX_GPIO41__FUNC_SCP_SPI1_CS (MTK_PIN_NO(41) | 2)
+#define PINMUX_GPIO41__FUNC_PWM0 (MTK_PIN_NO(41) | 3)
+#define PINMUX_GPIO41__FUNC_URTS0 (MTK_PIN_NO(41) | 4)
+#define PINMUX_GPIO41__FUNC_SPINOR_IO3 (MTK_PIN_NO(41) | 5)
+#define PINMUX_GPIO41__FUNC_TP_URTS1_AO (MTK_PIN_NO(41) | 6)
+#define PINMUX_GPIO41__FUNC_DBG_MON_A16 (MTK_PIN_NO(41) | 7)
+
+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define PINMUX_GPIO42__FUNC_SPI1_MO_A (MTK_PIN_NO(42) | 1)
+#define PINMUX_GPIO42__FUNC_SCP_SPI1_MO (MTK_PIN_NO(42) | 2)
+#define PINMUX_GPIO42__FUNC_PWM1 (MTK_PIN_NO(42) | 3)
+#define PINMUX_GPIO42__FUNC_UCTS1 (MTK_PIN_NO(42) | 4)
+#define PINMUX_GPIO42__FUNC_TP_UCTS2_AO (MTK_PIN_NO(42) | 6)
+#define PINMUX_GPIO42__FUNC_DBG_MON_A17 (MTK_PIN_NO(42) | 7)
+
+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define PINMUX_GPIO43__FUNC_SPI1_MI_A (MTK_PIN_NO(43) | 1)
+#define PINMUX_GPIO43__FUNC_SCP_SPI1_MI (MTK_PIN_NO(43) | 2)
+#define PINMUX_GPIO43__FUNC_PWM2 (MTK_PIN_NO(43) | 3)
+#define PINMUX_GPIO43__FUNC_URTS1 (MTK_PIN_NO(43) | 4)
+#define PINMUX_GPIO43__FUNC_TP_URTS2_AO (MTK_PIN_NO(43) | 6)
+#define PINMUX_GPIO43__FUNC_DBG_MON_A18 (MTK_PIN_NO(43) | 7)
+
+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define PINMUX_GPIO44__FUNC_SPI2_CLK_A (MTK_PIN_NO(44) | 1)
+#define PINMUX_GPIO44__FUNC_SCP_SPI0_CK (MTK_PIN_NO(44) | 2)
+#define PINMUX_GPIO44__FUNC_DBG_MON_A19 (MTK_PIN_NO(44) | 7)
+
+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define PINMUX_GPIO45__FUNC_SPI2_CSB_A (MTK_PIN_NO(45) | 1)
+#define PINMUX_GPIO45__FUNC_SCP_SPI0_CS (MTK_PIN_NO(45) | 2)
+#define PINMUX_GPIO45__FUNC_DBG_MON_A20 (MTK_PIN_NO(45) | 7)
+
+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define PINMUX_GPIO46__FUNC_SPI2_MO_A (MTK_PIN_NO(46) | 1)
+#define PINMUX_GPIO46__FUNC_SCP_SPI0_MO (MTK_PIN_NO(46) | 2)
+#define PINMUX_GPIO46__FUNC_DBG_MON_A21 (MTK_PIN_NO(46) | 7)
+
+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define PINMUX_GPIO47__FUNC_SPI2_MI_A (MTK_PIN_NO(47) | 1)
+#define PINMUX_GPIO47__FUNC_SCP_SPI0_MI (MTK_PIN_NO(47) | 2)
+#define PINMUX_GPIO47__FUNC_DBG_MON_A22 (MTK_PIN_NO(47) | 7)
+
+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define PINMUX_GPIO48__FUNC_SPI3_CLK (MTK_PIN_NO(48) | 1)
+#define PINMUX_GPIO48__FUNC_TP_URXD1_AO (MTK_PIN_NO(48) | 2)
+#define PINMUX_GPIO48__FUNC_TP_URXD2_AO (MTK_PIN_NO(48) | 3)
+#define PINMUX_GPIO48__FUNC_URXD1 (MTK_PIN_NO(48) | 4)
+#define PINMUX_GPIO48__FUNC_I2S2_MCK (MTK_PIN_NO(48) | 5)
+#define PINMUX_GPIO48__FUNC_SCP_SPI0_CK (MTK_PIN_NO(48) | 6)
+
+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define PINMUX_GPIO49__FUNC_SPI3_CSB (MTK_PIN_NO(49) | 1)
+#define PINMUX_GPIO49__FUNC_TP_UTXD1_AO (MTK_PIN_NO(49) | 2)
+#define PINMUX_GPIO49__FUNC_TP_UTXD2_AO (MTK_PIN_NO(49) | 3)
+#define PINMUX_GPIO49__FUNC_UTXD1 (MTK_PIN_NO(49) | 4)
+#define PINMUX_GPIO49__FUNC_I2S2_BCK (MTK_PIN_NO(49) | 5)
+#define PINMUX_GPIO49__FUNC_SCP_SPI0_CS (MTK_PIN_NO(49) | 6)
+
+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define PINMUX_GPIO50__FUNC_SPI3_MO (MTK_PIN_NO(50) | 1)
+#define PINMUX_GPIO50__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 5)
+#define PINMUX_GPIO50__FUNC_SCP_SPI0_MO (MTK_PIN_NO(50) | 6)
+
+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define PINMUX_GPIO51__FUNC_SPI3_MI (MTK_PIN_NO(51) | 1)
+#define PINMUX_GPIO51__FUNC_I2S2_DI (MTK_PIN_NO(51) | 5)
+#define PINMUX_GPIO51__FUNC_SCP_SPI0_MI (MTK_PIN_NO(51) | 6)
+
+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define PINMUX_GPIO52__FUNC_SPI5_CLK (MTK_PIN_NO(52) | 1)
+#define PINMUX_GPIO52__FUNC_I2S2_MCK (MTK_PIN_NO(52) | 2)
+#define PINMUX_GPIO52__FUNC_I2S1_MCK (MTK_PIN_NO(52) | 3)
+#define PINMUX_GPIO52__FUNC_SCP_SPI1_CK (MTK_PIN_NO(52) | 4)
+#define PINMUX_GPIO52__FUNC_LVTS_26M (MTK_PIN_NO(52) | 5)
+#define PINMUX_GPIO52__FUNC_DFD_TCK_XI (MTK_PIN_NO(52) | 6)
+#define PINMUX_GPIO52__FUNC_DBG_MON_B30 (MTK_PIN_NO(52) | 7)
+
+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define PINMUX_GPIO53__FUNC_SPI5_CSB (MTK_PIN_NO(53) | 1)
+#define PINMUX_GPIO53__FUNC_I2S2_BCK (MTK_PIN_NO(53) | 2)
+#define PINMUX_GPIO53__FUNC_I2S1_BCK (MTK_PIN_NO(53) | 3)
+#define PINMUX_GPIO53__FUNC_SCP_SPI1_CS (MTK_PIN_NO(53) | 4)
+#define PINMUX_GPIO53__FUNC_LVTS_FOUT (MTK_PIN_NO(53) | 5)
+#define PINMUX_GPIO53__FUNC_DFD_TDI (MTK_PIN_NO(53) | 6)
+#define PINMUX_GPIO53__FUNC_DBG_MON_B31 (MTK_PIN_NO(53) | 7)
+
+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define PINMUX_GPIO54__FUNC_SPI5_MO (MTK_PIN_NO(54) | 1)
+#define PINMUX_GPIO54__FUNC_I2S2_LRCK (MTK_PIN_NO(54) | 2)
+#define PINMUX_GPIO54__FUNC_I2S1_LRCK (MTK_PIN_NO(54) | 3)
+#define PINMUX_GPIO54__FUNC_SCP_SPI1_MO (MTK_PIN_NO(54) | 4)
+#define PINMUX_GPIO54__FUNC_LVTS_SCK (MTK_PIN_NO(54) | 5)
+#define PINMUX_GPIO54__FUNC_DFD_TDO (MTK_PIN_NO(54) | 6)
+#define PINMUX_GPIO54__FUNC_DBG_MON_A1 (MTK_PIN_NO(54) | 7)
+
+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define PINMUX_GPIO55__FUNC_SPI5_MI (MTK_PIN_NO(55) | 1)
+#define PINMUX_GPIO55__FUNC_I2S2_DI (MTK_PIN_NO(55) | 2)
+#define PINMUX_GPIO55__FUNC_I2S1_DO (MTK_PIN_NO(55) | 3)
+#define PINMUX_GPIO55__FUNC_SCP_SPI1_MI (MTK_PIN_NO(55) | 4)
+#define PINMUX_GPIO55__FUNC_LVTS_SDO (MTK_PIN_NO(55) | 5)
+#define PINMUX_GPIO55__FUNC_DFD_TMS (MTK_PIN_NO(55) | 6)
+#define PINMUX_GPIO55__FUNC_DBG_MON_B32 (MTK_PIN_NO(55) | 7)
+
+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define PINMUX_GPIO56__FUNC_I2S1_DO (MTK_PIN_NO(56) | 1)
+#define PINMUX_GPIO56__FUNC_I2S3_DO (MTK_PIN_NO(56) | 2)
+#define PINMUX_GPIO56__FUNC_DBG_MON_A23 (MTK_PIN_NO(56) | 7)
+
+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define PINMUX_GPIO57__FUNC_I2S1_BCK (MTK_PIN_NO(57) | 1)
+#define PINMUX_GPIO57__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 2)
+#define PINMUX_GPIO57__FUNC_DBG_MON_A24 (MTK_PIN_NO(57) | 7)
+
+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define PINMUX_GPIO58__FUNC_I2S1_LRCK (MTK_PIN_NO(58) | 1)
+#define PINMUX_GPIO58__FUNC_I2S3_LRCK (MTK_PIN_NO(58) | 2)
+#define PINMUX_GPIO58__FUNC_DBG_MON_A25 (MTK_PIN_NO(58) | 7)
+
+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define PINMUX_GPIO59__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 1)
+#define PINMUX_GPIO59__FUNC_I2S3_MCK (MTK_PIN_NO(59) | 2)
+#define PINMUX_GPIO59__FUNC_DBG_MON_A27 (MTK_PIN_NO(59) | 7)
+
+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define PINMUX_GPIO60__FUNC_TDM_RX_LRCK (MTK_PIN_NO(60) | 1)
+#define PINMUX_GPIO60__FUNC_ANT_SEL3 (MTK_PIN_NO(60) | 2)
+#define PINMUX_GPIO60__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(60) | 5)
+
+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define PINMUX_GPIO61__FUNC_TDM_RX_BCK (MTK_PIN_NO(61) | 1)
+#define PINMUX_GPIO61__FUNC_ANT_SEL4 (MTK_PIN_NO(61) | 2)
+#define PINMUX_GPIO61__FUNC_SPINOR_CK (MTK_PIN_NO(61) | 4)
+#define PINMUX_GPIO61__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(61) | 5)
+
+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define PINMUX_GPIO62__FUNC_TDM_RX_MCK (MTK_PIN_NO(62) | 1)
+#define PINMUX_GPIO62__FUNC_ANT_SEL5 (MTK_PIN_NO(62) | 2)
+#define PINMUX_GPIO62__FUNC_SPINOR_CS (MTK_PIN_NO(62) | 4)
+#define PINMUX_GPIO62__FUNC_CONN_MCU_TDI (MTK_PIN_NO(62) | 5)
+
+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define PINMUX_GPIO63__FUNC_TDM_RX_DATA0 (MTK_PIN_NO(63) | 1)
+#define PINMUX_GPIO63__FUNC_ANT_SEL6 (MTK_PIN_NO(63) | 2)
+#define PINMUX_GPIO63__FUNC_SPINOR_IO0 (MTK_PIN_NO(63) | 4)
+#define PINMUX_GPIO63__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(63) | 5)
+
+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define PINMUX_GPIO64__FUNC_TDM_RX_DATA1 (MTK_PIN_NO(64) | 1)
+#define PINMUX_GPIO64__FUNC_ANT_SEL7 (MTK_PIN_NO(64) | 2)
+#define PINMUX_GPIO64__FUNC_PWM0 (MTK_PIN_NO(64) | 3)
+#define PINMUX_GPIO64__FUNC_SPINOR_IO1 (MTK_PIN_NO(64) | 4)
+#define PINMUX_GPIO64__FUNC_CONN_MCU_TCK (MTK_PIN_NO(64) | 5)
+
+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define PINMUX_GPIO65__FUNC_TDM_RX_DATA2 (MTK_PIN_NO(65) | 1)
+#define PINMUX_GPIO65__FUNC_UCTS0 (MTK_PIN_NO(65) | 2)
+#define PINMUX_GPIO65__FUNC_PWM1 (MTK_PIN_NO(65) | 3)
+#define PINMUX_GPIO65__FUNC_SPINOR_IO2 (MTK_PIN_NO(65) | 4)
+#define PINMUX_GPIO65__FUNC_CONN_MCU_TDO (MTK_PIN_NO(65) | 5)
+#define PINMUX_GPIO65__FUNC_TP_UCTS1_AO (MTK_PIN_NO(65) | 6)
+#define PINMUX_GPIO65__FUNC_TP_UCTS2_AO (MTK_PIN_NO(65) | 7)
+
+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define PINMUX_GPIO66__FUNC_TDM_RX_DATA3 (MTK_PIN_NO(66) | 1)
+#define PINMUX_GPIO66__FUNC_URTS0 (MTK_PIN_NO(66) | 2)
+#define PINMUX_GPIO66__FUNC_PWM2 (MTK_PIN_NO(66) | 3)
+#define PINMUX_GPIO66__FUNC_SPINOR_IO3 (MTK_PIN_NO(66) | 4)
+#define PINMUX_GPIO66__FUNC_CONN_MCU_TMS (MTK_PIN_NO(66) | 5)
+#define PINMUX_GPIO66__FUNC_TP_URTS1_AO (MTK_PIN_NO(66) | 6)
+#define PINMUX_GPIO66__FUNC_TP_URTS2_AO (MTK_PIN_NO(66) | 7)
+
+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define PINMUX_GPIO67__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1)
+
+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define PINMUX_GPIO68__FUNC_MSDC0_CLK (MTK_PIN_NO(68) | 1)
+
+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define PINMUX_GPIO69__FUNC_MSDC0_CMD (MTK_PIN_NO(69) | 1)
+
+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define PINMUX_GPIO70__FUNC_MSDC0_RSTB (MTK_PIN_NO(70) | 1)
+
+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define PINMUX_GPIO71__FUNC_MSDC0_DAT0 (MTK_PIN_NO(71) | 1)
+
+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define PINMUX_GPIO72__FUNC_MSDC0_DAT1 (MTK_PIN_NO(72) | 1)
+
+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define PINMUX_GPIO73__FUNC_MSDC0_DAT2 (MTK_PIN_NO(73) | 1)
+
+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define PINMUX_GPIO74__FUNC_MSDC0_DAT3 (MTK_PIN_NO(74) | 1)
+
+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define PINMUX_GPIO75__FUNC_MSDC0_DAT4 (MTK_PIN_NO(75) | 1)
+
+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define PINMUX_GPIO76__FUNC_MSDC0_DAT5 (MTK_PIN_NO(76) | 1)
+
+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define PINMUX_GPIO77__FUNC_MSDC0_DAT6 (MTK_PIN_NO(77) | 1)
+
+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define PINMUX_GPIO78__FUNC_MSDC0_DAT7 (MTK_PIN_NO(78) | 1)
+
+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define PINMUX_GPIO79__FUNC_KPCOL0 (MTK_PIN_NO(79) | 1)
+
+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define PINMUX_GPIO80__FUNC_KPCOL1 (MTK_PIN_NO(80) | 1)
+#define PINMUX_GPIO80__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(80) | 2)
+#define PINMUX_GPIO80__FUNC_PWM0 (MTK_PIN_NO(80) | 3)
+#define PINMUX_GPIO80__FUNC_CLKM0 (MTK_PIN_NO(80) | 4)
+
+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define PINMUX_GPIO81__FUNC_KPROW0 (MTK_PIN_NO(81) | 1)
+#define PINMUX_GPIO81__FUNC_PWM1 (MTK_PIN_NO(81) | 3)
+#define PINMUX_GPIO81__FUNC_CLKM1 (MTK_PIN_NO(81) | 4)
+
+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define PINMUX_GPIO82__FUNC_KPROW1 (MTK_PIN_NO(82) | 1)
+#define PINMUX_GPIO82__FUNC_PWM2 (MTK_PIN_NO(82) | 3)
+#define PINMUX_GPIO82__FUNC_CLKM2 (MTK_PIN_NO(82) | 4)
+
+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define PINMUX_GPIO83__FUNC_AP_GOOD (MTK_PIN_NO(83) | 1)
+#define PINMUX_GPIO83__FUNC_GPS_PPS (MTK_PIN_NO(83) | 2)
+#define PINMUX_GPIO83__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(83) | 4)
+#define PINMUX_GPIO83__FUNC_DBG_MON_A28 (MTK_PIN_NO(83) | 7)
+
+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define PINMUX_GPIO84__FUNC_MSDC1_CLK (MTK_PIN_NO(84) | 1)
+#define PINMUX_GPIO84__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(84) | 2)
+#define PINMUX_GPIO84__FUNC_UDI_TCK (MTK_PIN_NO(84) | 4)
+#define PINMUX_GPIO84__FUNC_CONN_DSP_JCK (MTK_PIN_NO(84) | 5)
+#define PINMUX_GPIO84__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(84) | 6)
+#define PINMUX_GPIO84__FUNC_DFD_TCK_XI (MTK_PIN_NO(84) | 7)
+
+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define PINMUX_GPIO85__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1)
+#define PINMUX_GPIO85__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(85) | 2)
+#define PINMUX_GPIO85__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(85) | 3)
+#define PINMUX_GPIO85__FUNC_UDI_TMS (MTK_PIN_NO(85) | 4)
+#define PINMUX_GPIO85__FUNC_CONN_DSP_JMS (MTK_PIN_NO(85) | 5)
+#define PINMUX_GPIO85__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(85) | 6)
+#define PINMUX_GPIO85__FUNC_DFD_TMS (MTK_PIN_NO(85) | 7)
+
+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define PINMUX_GPIO86__FUNC_MSDC1_DAT0 (MTK_PIN_NO(86) | 1)
+#define PINMUX_GPIO86__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(86) | 2)
+#define PINMUX_GPIO86__FUNC_UDI_TDI (MTK_PIN_NO(86) | 4)
+#define PINMUX_GPIO86__FUNC_CONN_DSP_JDI (MTK_PIN_NO(86) | 5)
+#define PINMUX_GPIO86__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(86) | 6)
+#define PINMUX_GPIO86__FUNC_DFD_TDI (MTK_PIN_NO(86) | 7)
+
+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define PINMUX_GPIO87__FUNC_MSDC1_DAT1 (MTK_PIN_NO(87) | 1)
+#define PINMUX_GPIO87__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(87) | 2)
+#define PINMUX_GPIO87__FUNC_UDI_TDO (MTK_PIN_NO(87) | 4)
+#define PINMUX_GPIO87__FUNC_CONN_DSP_JDO (MTK_PIN_NO(87) | 5)
+#define PINMUX_GPIO87__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(87) | 6)
+#define PINMUX_GPIO87__FUNC_DFD_TDO (MTK_PIN_NO(87) | 7)
+
+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define PINMUX_GPIO88__FUNC_MSDC1_DAT2 (MTK_PIN_NO(88) | 1)
+#define PINMUX_GPIO88__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(88) | 2)
+#define PINMUX_GPIO88__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 3)
+#define PINMUX_GPIO88__FUNC_UDI_NTRST (MTK_PIN_NO(88) | 4)
+#define PINMUX_GPIO88__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(88) | 5)
+#define PINMUX_GPIO88__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(88) | 6)
+
+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define PINMUX_GPIO89__FUNC_MSDC1_DAT3 (MTK_PIN_NO(89) | 1)
+#define PINMUX_GPIO89__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(89) | 5)
+
+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define PINMUX_GPIO90__FUNC_IDDIG_P0 (MTK_PIN_NO(90) | 1)
+#define PINMUX_GPIO90__FUNC_PGD_HV_HSC_PWR4 (MTK_PIN_NO(90) | 4)
+#define PINMUX_GPIO90__FUNC_GDU_SUM_TROOP2_2 (MTK_PIN_NO(90) | 5)
+
+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define PINMUX_GPIO91__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(91) | 1)
+#define PINMUX_GPIO91__FUNC_PGD_HV_HSC_PWR5 (MTK_PIN_NO(91) | 4)
+#define PINMUX_GPIO91__FUNC_GDU_TROOPS_DET0 (MTK_PIN_NO(91) | 5)
+
+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define PINMUX_GPIO92__FUNC_VBUS_VALID_P0 (MTK_PIN_NO(92) | 1)
+#define PINMUX_GPIO92__FUNC_PGD_DA_EFUSE_RDY (MTK_PIN_NO(92) | 4)
+#define PINMUX_GPIO92__FUNC_GDU_TROOPS_DET1 (MTK_PIN_NO(92) | 5)
+
+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define PINMUX_GPIO93__FUNC_IDDIG_P1 (MTK_PIN_NO(93) | 1)
+#define PINMUX_GPIO93__FUNC_PWM0 (MTK_PIN_NO(93) | 2)
+#define PINMUX_GPIO93__FUNC_CLKM0 (MTK_PIN_NO(93) | 3)
+#define PINMUX_GPIO93__FUNC_PGD_DA_EFUSE_RDY_PRE (MTK_PIN_NO(93) | 4)
+#define PINMUX_GPIO93__FUNC_GDU_TROOPS_DET2 (MTK_PIN_NO(93) | 5)
+
+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define PINMUX_GPIO94__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(94) | 1)
+#define PINMUX_GPIO94__FUNC_PWM1 (MTK_PIN_NO(94) | 2)
+#define PINMUX_GPIO94__FUNC_CLKM1 (MTK_PIN_NO(94) | 3)
+#define PINMUX_GPIO94__FUNC_PGD_DA_PWRGD_RESET (MTK_PIN_NO(94) | 4)
+
+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define PINMUX_GPIO95__FUNC_VBUS_VALID_P1 (MTK_PIN_NO(95) | 1)
+#define PINMUX_GPIO95__FUNC_PWM2 (MTK_PIN_NO(95) | 2)
+#define PINMUX_GPIO95__FUNC_CLKM2 (MTK_PIN_NO(95) | 3)
+#define PINMUX_GPIO95__FUNC_PGD_DA_PWRGD_ENB (MTK_PIN_NO(95) | 4)
+
+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define PINMUX_GPIO96__FUNC_DSI_TE (MTK_PIN_NO(96) | 1)
+#define PINMUX_GPIO96__FUNC_DBG_MON_A29 (MTK_PIN_NO(96) | 7)
+
+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define PINMUX_GPIO97__FUNC_DISP_PWM (MTK_PIN_NO(97) | 1)
+#define PINMUX_GPIO97__FUNC_DBG_MON_A30 (MTK_PIN_NO(97) | 7)
+
+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define PINMUX_GPIO98__FUNC_LCM_RST (MTK_PIN_NO(98) | 1)
+
+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define PINMUX_GPIO99__FUNC_DPI_PCLK (MTK_PIN_NO(99) | 1)
+#define PINMUX_GPIO99__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(99) | 2)
+#define PINMUX_GPIO99__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(99) | 3)
+#define PINMUX_GPIO99__FUNC_ANT_SEL0 (MTK_PIN_NO(99) | 5)
+#define PINMUX_GPIO99__FUNC_TP_GPIO0_AO (MTK_PIN_NO(99) | 6)
+#define PINMUX_GPIO99__FUNC_PGD_LV_LSC_PWR0 (MTK_PIN_NO(99) | 7)
+
+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define PINMUX_GPIO100__FUNC_DPI_VSYNC (MTK_PIN_NO(100) | 1)
+#define PINMUX_GPIO100__FUNC_KPCOL2 (MTK_PIN_NO(100) | 2)
+#define PINMUX_GPIO100__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(100) | 3)
+#define PINMUX_GPIO100__FUNC_ANT_SEL1 (MTK_PIN_NO(100) | 5)
+#define PINMUX_GPIO100__FUNC_TP_GPIO1_AO (MTK_PIN_NO(100) | 6)
+#define PINMUX_GPIO100__FUNC_PGD_LV_LSC_PWR1 (MTK_PIN_NO(100) | 7)
+
+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define PINMUX_GPIO101__FUNC_DPI_HSYNC (MTK_PIN_NO(101) | 1)
+#define PINMUX_GPIO101__FUNC_KPROW2 (MTK_PIN_NO(101) | 2)
+#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(101) | 3)
+#define PINMUX_GPIO101__FUNC_ANT_SEL2 (MTK_PIN_NO(101) | 5)
+#define PINMUX_GPIO101__FUNC_TP_GPIO2_AO (MTK_PIN_NO(101) | 6)
+#define PINMUX_GPIO101__FUNC_PGD_LV_LSC_PWR2 (MTK_PIN_NO(101) | 7)
+
+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define PINMUX_GPIO102__FUNC_DPI_DE (MTK_PIN_NO(102) | 1)
+#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(102) | 3)
+#define PINMUX_GPIO102__FUNC_ANT_SEL3 (MTK_PIN_NO(102) | 5)
+#define PINMUX_GPIO102__FUNC_TP_GPIO3_AO (MTK_PIN_NO(102) | 6)
+#define PINMUX_GPIO102__FUNC_PGD_LV_LSC_PWR3 (MTK_PIN_NO(102) | 7)
+
+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define PINMUX_GPIO103__FUNC_DPI_DATA0 (MTK_PIN_NO(103) | 1)
+#define PINMUX_GPIO103__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(103) | 3)
+#define PINMUX_GPIO103__FUNC_CLKM0 (MTK_PIN_NO(103) | 4)
+#define PINMUX_GPIO103__FUNC_ANT_SEL4 (MTK_PIN_NO(103) | 5)
+#define PINMUX_GPIO103__FUNC_TP_GPIO4_AO (MTK_PIN_NO(103) | 6)
+#define PINMUX_GPIO103__FUNC_PGD_LV_LSC_PWR4 (MTK_PIN_NO(103) | 7)
+
+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define PINMUX_GPIO104__FUNC_DPI_DATA1 (MTK_PIN_NO(104) | 1)
+#define PINMUX_GPIO104__FUNC_GPS_PPS (MTK_PIN_NO(104) | 2)
+#define PINMUX_GPIO104__FUNC_UCTS2 (MTK_PIN_NO(104) | 3)
+#define PINMUX_GPIO104__FUNC_CLKM1 (MTK_PIN_NO(104) | 4)
+#define PINMUX_GPIO104__FUNC_ANT_SEL5 (MTK_PIN_NO(104) | 5)
+#define PINMUX_GPIO104__FUNC_TP_GPIO5_AO (MTK_PIN_NO(104) | 6)
+#define PINMUX_GPIO104__FUNC_PGD_LV_LSC_PWR5 (MTK_PIN_NO(104) | 7)
+
+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define PINMUX_GPIO105__FUNC_DPI_DATA2 (MTK_PIN_NO(105) | 1)
+#define PINMUX_GPIO105__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(105) | 2)
+#define PINMUX_GPIO105__FUNC_URTS2 (MTK_PIN_NO(105) | 3)
+#define PINMUX_GPIO105__FUNC_CLKM2 (MTK_PIN_NO(105) | 4)
+#define PINMUX_GPIO105__FUNC_ANT_SEL6 (MTK_PIN_NO(105) | 5)
+#define PINMUX_GPIO105__FUNC_TP_GPIO6_AO (MTK_PIN_NO(105) | 6)
+#define PINMUX_GPIO105__FUNC_PGD_LV_HSC_PWR0 (MTK_PIN_NO(105) | 7)
+
+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define PINMUX_GPIO106__FUNC_DPI_DATA3 (MTK_PIN_NO(106) | 1)
+#define PINMUX_GPIO106__FUNC_TP_UTXD1_AO (MTK_PIN_NO(106) | 2)
+#define PINMUX_GPIO106__FUNC_UTXD2 (MTK_PIN_NO(106) | 3)
+#define PINMUX_GPIO106__FUNC_PWM0 (MTK_PIN_NO(106) | 4)
+#define PINMUX_GPIO106__FUNC_ANT_SEL7 (MTK_PIN_NO(106) | 5)
+#define PINMUX_GPIO106__FUNC_TP_GPIO7_AO (MTK_PIN_NO(106) | 6)
+#define PINMUX_GPIO106__FUNC_PGD_LV_HSC_PWR1 (MTK_PIN_NO(106) | 7)
+
+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define PINMUX_GPIO107__FUNC_DPI_DATA4 (MTK_PIN_NO(107) | 1)
+#define PINMUX_GPIO107__FUNC_TP_URXD1_AO (MTK_PIN_NO(107) | 2)
+#define PINMUX_GPIO107__FUNC_URXD2 (MTK_PIN_NO(107) | 3)
+#define PINMUX_GPIO107__FUNC_PWM1 (MTK_PIN_NO(107) | 4)
+#define PINMUX_GPIO107__FUNC_GDU_SUM_TROOP0_0 (MTK_PIN_NO(107) | 6)
+#define PINMUX_GPIO107__FUNC_PGD_LV_HSC_PWR2 (MTK_PIN_NO(107) | 7)
+
+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define PINMUX_GPIO108__FUNC_DPI_DATA5 (MTK_PIN_NO(108) | 1)
+#define PINMUX_GPIO108__FUNC_TP_UCTS1_AO (MTK_PIN_NO(108) | 2)
+#define PINMUX_GPIO108__FUNC_UCTS0 (MTK_PIN_NO(108) | 3)
+#define PINMUX_GPIO108__FUNC_PWM2 (MTK_PIN_NO(108) | 4)
+#define PINMUX_GPIO108__FUNC_GDU_SUM_TROOP0_1 (MTK_PIN_NO(108) | 6)
+#define PINMUX_GPIO108__FUNC_PGD_LV_HSC_PWR3 (MTK_PIN_NO(108) | 7)
+
+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define PINMUX_GPIO109__FUNC_DPI_DATA6 (MTK_PIN_NO(109) | 1)
+#define PINMUX_GPIO109__FUNC_TP_URTS1_AO (MTK_PIN_NO(109) | 2)
+#define PINMUX_GPIO109__FUNC_URTS0 (MTK_PIN_NO(109) | 3)
+#define PINMUX_GPIO109__FUNC_I2S0_DI (MTK_PIN_NO(109) | 4)
+#define PINMUX_GPIO109__FUNC_I2S2_DI (MTK_PIN_NO(109) | 5)
+#define PINMUX_GPIO109__FUNC_GDU_SUM_TROOP0_2 (MTK_PIN_NO(109) | 6)
+#define PINMUX_GPIO109__FUNC_PGD_LV_HSC_PWR4 (MTK_PIN_NO(109) | 7)
+
+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define PINMUX_GPIO110__FUNC_DPI_DATA7 (MTK_PIN_NO(110) | 1)
+#define PINMUX_GPIO110__FUNC_TP_UCTS2_AO (MTK_PIN_NO(110) | 2)
+#define PINMUX_GPIO110__FUNC_UCTS1 (MTK_PIN_NO(110) | 3)
+#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 4)
+#define PINMUX_GPIO110__FUNC_I2S1_BCK (MTK_PIN_NO(110) | 5)
+#define PINMUX_GPIO110__FUNC_GDU_SUM_TROOP1_0 (MTK_PIN_NO(110) | 6)
+#define PINMUX_GPIO110__FUNC_PGD_LV_HSC_PWR5 (MTK_PIN_NO(110) | 7)
+
+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define PINMUX_GPIO111__FUNC_DPI_DATA8 (MTK_PIN_NO(111) | 1)
+#define PINMUX_GPIO111__FUNC_TP_URTS2_AO (MTK_PIN_NO(111) | 2)
+#define PINMUX_GPIO111__FUNC_URTS1 (MTK_PIN_NO(111) | 3)
+#define PINMUX_GPIO111__FUNC_I2S3_MCK (MTK_PIN_NO(111) | 4)
+#define PINMUX_GPIO111__FUNC_I2S1_MCK (MTK_PIN_NO(111) | 5)
+#define PINMUX_GPIO111__FUNC_GDU_SUM_TROOP1_1 (MTK_PIN_NO(111) | 6)
+#define PINMUX_GPIO111__FUNC_PGD_HV_HSC_PWR0 (MTK_PIN_NO(111) | 7)
+
+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define PINMUX_GPIO112__FUNC_DPI_DATA9 (MTK_PIN_NO(112) | 1)
+#define PINMUX_GPIO112__FUNC_TP_URXD2_AO (MTK_PIN_NO(112) | 2)
+#define PINMUX_GPIO112__FUNC_URXD1 (MTK_PIN_NO(112) | 3)
+#define PINMUX_GPIO112__FUNC_I2S3_LRCK (MTK_PIN_NO(112) | 4)
+#define PINMUX_GPIO112__FUNC_I2S1_LRCK (MTK_PIN_NO(112) | 5)
+#define PINMUX_GPIO112__FUNC_GDU_SUM_TROOP1_2 (MTK_PIN_NO(112) | 6)
+#define PINMUX_GPIO112__FUNC_PGD_HV_HSC_PWR1 (MTK_PIN_NO(112) | 7)
+
+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define PINMUX_GPIO113__FUNC_DPI_DATA10 (MTK_PIN_NO(113) | 1)
+#define PINMUX_GPIO113__FUNC_TP_UTXD2_AO (MTK_PIN_NO(113) | 2)
+#define PINMUX_GPIO113__FUNC_UTXD1 (MTK_PIN_NO(113) | 3)
+#define PINMUX_GPIO113__FUNC_I2S3_DO (MTK_PIN_NO(113) | 4)
+#define PINMUX_GPIO113__FUNC_I2S1_DO (MTK_PIN_NO(113) | 5)
+#define PINMUX_GPIO113__FUNC_GDU_SUM_TROOP2_0 (MTK_PIN_NO(113) | 6)
+#define PINMUX_GPIO113__FUNC_PGD_HV_HSC_PWR2 (MTK_PIN_NO(113) | 7)
+
+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define PINMUX_GPIO114__FUNC_DPI_DATA11 (MTK_PIN_NO(114) | 1)
+#define PINMUX_GPIO114__FUNC_GDU_SUM_TROOP2_1 (MTK_PIN_NO(114) | 6)
+#define PINMUX_GPIO114__FUNC_PGD_HV_HSC_PWR3 (MTK_PIN_NO(114) | 7)
+
+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define PINMUX_GPIO115__FUNC_PCM_CLK (MTK_PIN_NO(115) | 1)
+#define PINMUX_GPIO115__FUNC_I2S0_BCK (MTK_PIN_NO(115) | 2)
+#define PINMUX_GPIO115__FUNC_I2S2_BCK (MTK_PIN_NO(115) | 3)
+
+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define PINMUX_GPIO116__FUNC_PCM_SYNC (MTK_PIN_NO(116) | 1)
+#define PINMUX_GPIO116__FUNC_I2S0_LRCK (MTK_PIN_NO(116) | 2)
+#define PINMUX_GPIO116__FUNC_I2S2_LRCK (MTK_PIN_NO(116) | 3)
+
+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define PINMUX_GPIO117__FUNC_PCM_DI (MTK_PIN_NO(117) | 1)
+#define PINMUX_GPIO117__FUNC_I2S0_DI (MTK_PIN_NO(117) | 2)
+#define PINMUX_GPIO117__FUNC_I2S2_DI (MTK_PIN_NO(117) | 3)
+
+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define PINMUX_GPIO118__FUNC_PCM_DO (MTK_PIN_NO(118) | 1)
+#define PINMUX_GPIO118__FUNC_I2S0_MCK (MTK_PIN_NO(118) | 2)
+#define PINMUX_GPIO118__FUNC_I2S2_MCK (MTK_PIN_NO(118) | 3)
+#define PINMUX_GPIO118__FUNC_I2S3_DO (MTK_PIN_NO(118) | 4)
+#define PINMUX_GPIO118__FUNC_I2S1_DO (MTK_PIN_NO(118) | 5)
+
+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define PINMUX_GPIO119__FUNC_JTMS_SEL1 (MTK_PIN_NO(119) | 1)
+#define PINMUX_GPIO119__FUNC_UDI_TMS (MTK_PIN_NO(119) | 2)
+#define PINMUX_GPIO119__FUNC_DFD_TMS (MTK_PIN_NO(119) | 3)
+#define PINMUX_GPIO119__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(119) | 4)
+#define PINMUX_GPIO119__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(119) | 5)
+#define PINMUX_GPIO119__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(119) | 6)
+
+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define PINMUX_GPIO120__FUNC_JTCK_SEL1 (MTK_PIN_NO(120) | 1)
+#define PINMUX_GPIO120__FUNC_UDI_TCK (MTK_PIN_NO(120) | 2)
+#define PINMUX_GPIO120__FUNC_DFD_TCK_XI (MTK_PIN_NO(120) | 3)
+#define PINMUX_GPIO120__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(120) | 4)
+#define PINMUX_GPIO120__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(120) | 5)
+#define PINMUX_GPIO120__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(120) | 6)
+
+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define PINMUX_GPIO121__FUNC_JTDI_SEL1 (MTK_PIN_NO(121) | 1)
+#define PINMUX_GPIO121__FUNC_UDI_TDI (MTK_PIN_NO(121) | 2)
+#define PINMUX_GPIO121__FUNC_DFD_TDI (MTK_PIN_NO(121) | 3)
+#define PINMUX_GPIO121__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(121) | 4)
+#define PINMUX_GPIO121__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(121) | 5)
+#define PINMUX_GPIO121__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(121) | 6)
+
+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define PINMUX_GPIO122__FUNC_JTDO_SEL1 (MTK_PIN_NO(122) | 1)
+#define PINMUX_GPIO122__FUNC_UDI_TDO (MTK_PIN_NO(122) | 2)
+#define PINMUX_GPIO122__FUNC_DFD_TDO (MTK_PIN_NO(122) | 3)
+#define PINMUX_GPIO122__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(122) | 4)
+#define PINMUX_GPIO122__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(122) | 5)
+#define PINMUX_GPIO122__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(122) | 6)
+
+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define PINMUX_GPIO123__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(123) | 1)
+#define PINMUX_GPIO123__FUNC_UDI_NTRST (MTK_PIN_NO(123) | 2)
+#define PINMUX_GPIO123__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(123) | 4)
+#define PINMUX_GPIO123__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(123) | 5)
+#define PINMUX_GPIO123__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(123) | 6)
+
+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define PINMUX_GPIO124__FUNC_CMMCLK0 (MTK_PIN_NO(124) | 1)
+#define PINMUX_GPIO124__FUNC_CLKM0 (MTK_PIN_NO(124) | 2)
+#define PINMUX_GPIO124__FUNC_PWM0 (MTK_PIN_NO(124) | 3)
+
+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define PINMUX_GPIO125__FUNC_CMMCLK1 (MTK_PIN_NO(125) | 1)
+#define PINMUX_GPIO125__FUNC_CLKM1 (MTK_PIN_NO(125) | 2)
+#define PINMUX_GPIO125__FUNC_PWM1 (MTK_PIN_NO(125) | 3)
+#define PINMUX_GPIO125__FUNC_DBG_MON_B0 (MTK_PIN_NO(125) | 7)
+
+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define PINMUX_GPIO126__FUNC_CMMCLK2 (MTK_PIN_NO(126) | 1)
+#define PINMUX_GPIO126__FUNC_CLKM2 (MTK_PIN_NO(126) | 2)
+#define PINMUX_GPIO126__FUNC_PWM2 (MTK_PIN_NO(126) | 3)
+#define PINMUX_GPIO126__FUNC_DBG_MON_B1 (MTK_PIN_NO(126) | 7)
+
+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define PINMUX_GPIO127__FUNC_SCL0 (MTK_PIN_NO(127) | 1)
+#define PINMUX_GPIO127__FUNC_SCP_SCL0 (MTK_PIN_NO(127) | 4)
+#define PINMUX_GPIO127__FUNC_SCP_SCL1 (MTK_PIN_NO(127) | 5)
+
+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define PINMUX_GPIO128__FUNC_SDA0 (MTK_PIN_NO(128) | 1)
+#define PINMUX_GPIO128__FUNC_SCP_SDA0 (MTK_PIN_NO(128) | 4)
+#define PINMUX_GPIO128__FUNC_SCP_SDA1 (MTK_PIN_NO(128) | 5)
+
+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define PINMUX_GPIO129__FUNC_SCL1 (MTK_PIN_NO(129) | 1)
+#define PINMUX_GPIO129__FUNC_SCP_SCL0 (MTK_PIN_NO(129) | 4)
+#define PINMUX_GPIO129__FUNC_SCP_SCL1 (MTK_PIN_NO(129) | 5)
+#define PINMUX_GPIO129__FUNC_DBG_MON_B4 (MTK_PIN_NO(129) | 7)
+
+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define PINMUX_GPIO130__FUNC_SDA1 (MTK_PIN_NO(130) | 1)
+#define PINMUX_GPIO130__FUNC_SCP_SDA0 (MTK_PIN_NO(130) | 4)
+#define PINMUX_GPIO130__FUNC_SCP_SDA1 (MTK_PIN_NO(130) | 5)
+#define PINMUX_GPIO130__FUNC_DBG_MON_B5 (MTK_PIN_NO(130) | 7)
+
+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define PINMUX_GPIO131__FUNC_SCL2 (MTK_PIN_NO(131) | 1)
+#define PINMUX_GPIO131__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(131) | 2)
+#define PINMUX_GPIO131__FUNC_CONN_UART0_TXD (MTK_PIN_NO(131) | 3)
+#define PINMUX_GPIO131__FUNC_SCP_SCL0 (MTK_PIN_NO(131) | 4)
+#define PINMUX_GPIO131__FUNC_SCP_SCL1 (MTK_PIN_NO(131) | 5)
+#define PINMUX_GPIO131__FUNC_DBG_MON_B6 (MTK_PIN_NO(131) | 7)
+
+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define PINMUX_GPIO132__FUNC_SDA2 (MTK_PIN_NO(132) | 1)
+#define PINMUX_GPIO132__FUNC_SSPM_URXD_AO (MTK_PIN_NO(132) | 2)
+#define PINMUX_GPIO132__FUNC_CONN_UART0_RXD (MTK_PIN_NO(132) | 3)
+#define PINMUX_GPIO132__FUNC_SCP_SDA0 (MTK_PIN_NO(132) | 4)
+#define PINMUX_GPIO132__FUNC_SCP_SDA1 (MTK_PIN_NO(132) | 5)
+#define PINMUX_GPIO132__FUNC_DBG_MON_B7 (MTK_PIN_NO(132) | 7)
+
+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define PINMUX_GPIO133__FUNC_SCL3 (MTK_PIN_NO(133) | 1)
+#define PINMUX_GPIO133__FUNC_SCP_SCL0 (MTK_PIN_NO(133) | 4)
+#define PINMUX_GPIO133__FUNC_SCP_SCL1 (MTK_PIN_NO(133) | 5)
+#define PINMUX_GPIO133__FUNC_DBG_MON_B8 (MTK_PIN_NO(133) | 7)
+
+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define PINMUX_GPIO134__FUNC_SDA3 (MTK_PIN_NO(134) | 1)
+#define PINMUX_GPIO134__FUNC_GPS_PPS (MTK_PIN_NO(134) | 3)
+#define PINMUX_GPIO134__FUNC_SCP_SDA0 (MTK_PIN_NO(134) | 4)
+#define PINMUX_GPIO134__FUNC_SCP_SDA1 (MTK_PIN_NO(134) | 5)
+#define PINMUX_GPIO134__FUNC_DBG_MON_B9 (MTK_PIN_NO(134) | 7)
+
+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define PINMUX_GPIO135__FUNC_SCL4 (MTK_PIN_NO(135) | 1)
+#define PINMUX_GPIO135__FUNC_TP_UTXD1_AO (MTK_PIN_NO(135) | 2)
+#define PINMUX_GPIO135__FUNC_UTXD1 (MTK_PIN_NO(135) | 3)
+#define PINMUX_GPIO135__FUNC_SCP_SCL0 (MTK_PIN_NO(135) | 4)
+#define PINMUX_GPIO135__FUNC_SCP_SCL1 (MTK_PIN_NO(135) | 5)
+#define PINMUX_GPIO135__FUNC_DBG_MON_B10 (MTK_PIN_NO(135) | 7)
+
+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define PINMUX_GPIO136__FUNC_SDA4 (MTK_PIN_NO(136) | 1)
+#define PINMUX_GPIO136__FUNC_TP_URXD1_AO (MTK_PIN_NO(136) | 2)
+#define PINMUX_GPIO136__FUNC_URXD1 (MTK_PIN_NO(136) | 3)
+#define PINMUX_GPIO136__FUNC_SCP_SDA0 (MTK_PIN_NO(136) | 4)
+#define PINMUX_GPIO136__FUNC_SCP_SDA1 (MTK_PIN_NO(136) | 5)
+#define PINMUX_GPIO136__FUNC_DBG_MON_B11 (MTK_PIN_NO(136) | 7)
+
+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define PINMUX_GPIO137__FUNC_SCL5 (MTK_PIN_NO(137) | 1)
+#define PINMUX_GPIO137__FUNC_UTXD2 (MTK_PIN_NO(137) | 2)
+#define PINMUX_GPIO137__FUNC_UCTS1 (MTK_PIN_NO(137) | 3)
+#define PINMUX_GPIO137__FUNC_SCP_SCL0 (MTK_PIN_NO(137) | 4)
+#define PINMUX_GPIO137__FUNC_SCP_SCL1 (MTK_PIN_NO(137) | 5)
+
+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define PINMUX_GPIO138__FUNC_SDA5 (MTK_PIN_NO(138) | 1)
+#define PINMUX_GPIO138__FUNC_URXD2 (MTK_PIN_NO(138) | 2)
+#define PINMUX_GPIO138__FUNC_URTS1 (MTK_PIN_NO(138) | 3)
+#define PINMUX_GPIO138__FUNC_SCP_SDA0 (MTK_PIN_NO(138) | 4)
+#define PINMUX_GPIO138__FUNC_SCP_SDA1 (MTK_PIN_NO(138) | 5)
+
+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define PINMUX_GPIO139__FUNC_SCL6 (MTK_PIN_NO(139) | 1)
+#define PINMUX_GPIO139__FUNC_UTXD1 (MTK_PIN_NO(139) | 2)
+#define PINMUX_GPIO139__FUNC_TP_UTXD1_AO (MTK_PIN_NO(139) | 3)
+#define PINMUX_GPIO139__FUNC_SCP_SCL0 (MTK_PIN_NO(139) | 4)
+#define PINMUX_GPIO139__FUNC_SCP_SCL1 (MTK_PIN_NO(139) | 5)
+#define PINMUX_GPIO139__FUNC_DBG_MON_B12 (MTK_PIN_NO(139) | 7)
+
+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define PINMUX_GPIO140__FUNC_SDA6 (MTK_PIN_NO(140) | 1)
+#define PINMUX_GPIO140__FUNC_URXD1 (MTK_PIN_NO(140) | 2)
+#define PINMUX_GPIO140__FUNC_TP_URXD1_AO (MTK_PIN_NO(140) | 3)
+#define PINMUX_GPIO140__FUNC_SCP_SDA0 (MTK_PIN_NO(140) | 4)
+#define PINMUX_GPIO140__FUNC_SCP_SDA1 (MTK_PIN_NO(140) | 5)
+#define PINMUX_GPIO140__FUNC_DBG_MON_B13 (MTK_PIN_NO(140) | 7)
+
+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define PINMUX_GPIO141__FUNC_SCL7 (MTK_PIN_NO(141) | 1)
+#define PINMUX_GPIO141__FUNC_URTS0 (MTK_PIN_NO(141) | 2)
+#define PINMUX_GPIO141__FUNC_TP_URTS1_AO (MTK_PIN_NO(141) | 3)
+#define PINMUX_GPIO141__FUNC_SCP_SCL0 (MTK_PIN_NO(141) | 4)
+#define PINMUX_GPIO141__FUNC_SCP_SCL1 (MTK_PIN_NO(141) | 5)
+#define PINMUX_GPIO141__FUNC_UDI_TCK (MTK_PIN_NO(141) | 6)
+#define PINMUX_GPIO141__FUNC_DBG_MON_B14 (MTK_PIN_NO(141) | 7)
+
+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define PINMUX_GPIO142__FUNC_SDA7 (MTK_PIN_NO(142) | 1)
+#define PINMUX_GPIO142__FUNC_UCTS0 (MTK_PIN_NO(142) | 2)
+#define PINMUX_GPIO142__FUNC_TP_UCTS1_AO (MTK_PIN_NO(142) | 3)
+#define PINMUX_GPIO142__FUNC_SCP_SDA0 (MTK_PIN_NO(142) | 4)
+#define PINMUX_GPIO142__FUNC_SCP_SDA1 (MTK_PIN_NO(142) | 5)
+
+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define PINMUX_GPIO143__FUNC_SCL8 (MTK_PIN_NO(143) | 1)
+#define PINMUX_GPIO143__FUNC_SCP_SCL0 (MTK_PIN_NO(143) | 4)
+#define PINMUX_GPIO143__FUNC_SCP_SCL1 (MTK_PIN_NO(143) | 5)
+#define PINMUX_GPIO143__FUNC_DBG_MON_B16 (MTK_PIN_NO(143) | 7)
+
+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define PINMUX_GPIO144__FUNC_SDA8 (MTK_PIN_NO(144) | 1)
+#define PINMUX_GPIO144__FUNC_SCP_SDA0 (MTK_PIN_NO(144) | 4)
+#define PINMUX_GPIO144__FUNC_SCP_SDA1 (MTK_PIN_NO(144) | 5)
+#define PINMUX_GPIO144__FUNC_DBG_MON_B17 (MTK_PIN_NO(144) | 7)
+
+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define PINMUX_GPIO145__FUNC_SCL9 (MTK_PIN_NO(145) | 1)
+#define PINMUX_GPIO145__FUNC_CMVREF1 (MTK_PIN_NO(145) | 2)
+#define PINMUX_GPIO145__FUNC_GPS_PPS (MTK_PIN_NO(145) | 3)
+#define PINMUX_GPIO145__FUNC_SCP_SCL0 (MTK_PIN_NO(145) | 4)
+#define PINMUX_GPIO145__FUNC_SCP_SCL1 (MTK_PIN_NO(145) | 5)
+#define PINMUX_GPIO145__FUNC_DBG_MON_B18 (MTK_PIN_NO(145) | 7)
+
+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define PINMUX_GPIO146__FUNC_SDA9 (MTK_PIN_NO(146) | 1)
+#define PINMUX_GPIO146__FUNC_CMVREF0 (MTK_PIN_NO(146) | 2)
+#define PINMUX_GPIO146__FUNC_SCP_SDA0 (MTK_PIN_NO(146) | 4)
+#define PINMUX_GPIO146__FUNC_SCP_SDA1 (MTK_PIN_NO(146) | 5)
+#define PINMUX_GPIO146__FUNC_DBG_MON_B19 (MTK_PIN_NO(146) | 7)
+
+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define PINMUX_GPIO147__FUNC_CMFLASH0 (MTK_PIN_NO(147) | 1)
+#define PINMUX_GPIO147__FUNC_LVTS_SDI (MTK_PIN_NO(147) | 2)
+#define PINMUX_GPIO147__FUNC_DPI_DATA12 (MTK_PIN_NO(147) | 3)
+#define PINMUX_GPIO147__FUNC_TP_GPIO0_AO (MTK_PIN_NO(147) | 4)
+#define PINMUX_GPIO147__FUNC_ANT_SEL3 (MTK_PIN_NO(147) | 5)
+#define PINMUX_GPIO147__FUNC_DFD_TCK_XI (MTK_PIN_NO(147) | 6)
+#define PINMUX_GPIO147__FUNC_DBG_MON_B20 (MTK_PIN_NO(147) | 7)
+
+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define PINMUX_GPIO148__FUNC_CMFLASH1 (MTK_PIN_NO(148) | 1)
+#define PINMUX_GPIO148__FUNC_LVTS_SCF (MTK_PIN_NO(148) | 2)
+#define PINMUX_GPIO148__FUNC_DPI_DATA13 (MTK_PIN_NO(148) | 3)
+#define PINMUX_GPIO148__FUNC_TP_GPIO1_AO (MTK_PIN_NO(148) | 4)
+#define PINMUX_GPIO148__FUNC_ANT_SEL4 (MTK_PIN_NO(148) | 5)
+#define PINMUX_GPIO148__FUNC_DFD_TMS (MTK_PIN_NO(148) | 6)
+#define PINMUX_GPIO148__FUNC_DBG_MON_B21 (MTK_PIN_NO(148) | 7)
+
+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define PINMUX_GPIO149__FUNC_CMFLASH2 (MTK_PIN_NO(149) | 1)
+#define PINMUX_GPIO149__FUNC_CLKM0 (MTK_PIN_NO(149) | 2)
+#define PINMUX_GPIO149__FUNC_DPI_DATA14 (MTK_PIN_NO(149) | 3)
+#define PINMUX_GPIO149__FUNC_TP_GPIO2_AO (MTK_PIN_NO(149) | 4)
+#define PINMUX_GPIO149__FUNC_ANT_SEL5 (MTK_PIN_NO(149) | 5)
+#define PINMUX_GPIO149__FUNC_DFD_TDI (MTK_PIN_NO(149) | 6)
+#define PINMUX_GPIO149__FUNC_DBG_MON_B22 (MTK_PIN_NO(149) | 7)
+
+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define PINMUX_GPIO150__FUNC_CLKM1 (MTK_PIN_NO(150) | 2)
+#define PINMUX_GPIO150__FUNC_DPI_DATA15 (MTK_PIN_NO(150) | 3)
+#define PINMUX_GPIO150__FUNC_TP_GPIO3_AO (MTK_PIN_NO(150) | 4)
+#define PINMUX_GPIO150__FUNC_ANT_SEL6 (MTK_PIN_NO(150) | 5)
+#define PINMUX_GPIO150__FUNC_DFD_TDO (MTK_PIN_NO(150) | 6)
+#define PINMUX_GPIO150__FUNC_DBG_MON_B23 (MTK_PIN_NO(150) | 7)
+
+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define PINMUX_GPIO151__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(151) | 1)
+#define PINMUX_GPIO151__FUNC_CLKM2 (MTK_PIN_NO(151) | 2)
+#define PINMUX_GPIO151__FUNC_DPI_DATA16 (MTK_PIN_NO(151) | 3)
+#define PINMUX_GPIO151__FUNC_TP_GPIO4_AO (MTK_PIN_NO(151) | 4)
+#define PINMUX_GPIO151__FUNC_ANT_SEL7 (MTK_PIN_NO(151) | 5)
+#define PINMUX_GPIO151__FUNC_UDI_TMS (MTK_PIN_NO(151) | 6)
+#define PINMUX_GPIO151__FUNC_DBG_MON_B24 (MTK_PIN_NO(151) | 7)
+
+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define PINMUX_GPIO152__FUNC_CLKM3 (MTK_PIN_NO(152) | 2)
+#define PINMUX_GPIO152__FUNC_DPI_DATA17 (MTK_PIN_NO(152) | 3)
+#define PINMUX_GPIO152__FUNC_TP_GPIO5_AO (MTK_PIN_NO(152) | 4)
+
+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define PINMUX_GPIO153__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(153) | 1)
+#define PINMUX_GPIO153__FUNC_DPI_DATA18 (MTK_PIN_NO(153) | 3)
+#define PINMUX_GPIO153__FUNC_TP_GPIO6_AO (MTK_PIN_NO(153) | 4)
+#define PINMUX_GPIO153__FUNC_UDI_TDI (MTK_PIN_NO(153) | 6)
+#define PINMUX_GPIO153__FUNC_DBG_MON_B26 (MTK_PIN_NO(153) | 7)
+
+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define PINMUX_GPIO154__FUNC_PWM0 (MTK_PIN_NO(154) | 1)
+#define PINMUX_GPIO154__FUNC_CMVREF2 (MTK_PIN_NO(154) | 2)
+#define PINMUX_GPIO154__FUNC_DPI_DATA19 (MTK_PIN_NO(154) | 3)
+#define PINMUX_GPIO154__FUNC_TP_GPIO7_AO (MTK_PIN_NO(154) | 4)
+#define PINMUX_GPIO154__FUNC_UDI_TDO (MTK_PIN_NO(154) | 6)
+#define PINMUX_GPIO154__FUNC_DBG_MON_B27 (MTK_PIN_NO(154) | 7)
+
+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define PINMUX_GPIO155__FUNC_PWM1 (MTK_PIN_NO(155) | 1)
+#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 2)
+#define PINMUX_GPIO155__FUNC_DPI_DATA20 (MTK_PIN_NO(155) | 3)
+#define PINMUX_GPIO155__FUNC_UDI_NTRST (MTK_PIN_NO(155) | 6)
+#define PINMUX_GPIO155__FUNC_DBG_MON_B28 (MTK_PIN_NO(155) | 7)
+
+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define PINMUX_GPIO156__FUNC_PWM2 (MTK_PIN_NO(156) | 1)
+#define PINMUX_GPIO156__FUNC_CMVREF0 (MTK_PIN_NO(156) | 2)
+#define PINMUX_GPIO156__FUNC_DPI_DATA21 (MTK_PIN_NO(156) | 3)
+
+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define PINMUX_GPIO157__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(157) | 1)
+
+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define PINMUX_GPIO158__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(158) | 1)
+
+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define PINMUX_GPIO159__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(159) | 1)
+#define PINMUX_GPIO159__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(159) | 2)
+
+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define PINMUX_GPIO160__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(160) | 1)
+#define PINMUX_GPIO160__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(160) | 2)
+
+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define PINMUX_GPIO161__FUNC_SRCLKENA0 (MTK_PIN_NO(161) | 1)
+
+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define PINMUX_GPIO162__FUNC_SRCLKENA1 (MTK_PIN_NO(162) | 1)
+#define PINMUX_GPIO162__FUNC_DBG_MON_A31 (MTK_PIN_NO(162) | 7)
+
+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define PINMUX_GPIO163__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(163) | 1)
+#define PINMUX_GPIO163__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(163) | 2)
+
+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define PINMUX_GPIO164__FUNC_RTC32K_CK (MTK_PIN_NO(164) | 1)
+
+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+#define PINMUX_GPIO165__FUNC_WATCHDOG (MTK_PIN_NO(165) | 1)
+
+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+#define PINMUX_GPIO166__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(166) | 1)
+#define PINMUX_GPIO166__FUNC_AUD_CLK_MISO (MTK_PIN_NO(166) | 2)
+#define PINMUX_GPIO166__FUNC_I2S1_MCK (MTK_PIN_NO(166) | 3)
+
+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+#define PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(167) | 1)
+#define PINMUX_GPIO167__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(167) | 2)
+#define PINMUX_GPIO167__FUNC_I2S1_BCK (MTK_PIN_NO(167) | 3)
+
+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+#define PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(168) | 1)
+#define PINMUX_GPIO168__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(168) | 2)
+#define PINMUX_GPIO168__FUNC_I2S1_LRCK (MTK_PIN_NO(168) | 3)
+
+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(169) | 1)
+#define PINMUX_GPIO169__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(169) | 2)
+#define PINMUX_GPIO169__FUNC_I2S1_DO (MTK_PIN_NO(169) | 3)
+
+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define PINMUX_GPIO170__FUNC_AUD_CLK_MISO (MTK_PIN_NO(170) | 1)
+#define PINMUX_GPIO170__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(170) | 2)
+#define PINMUX_GPIO170__FUNC_I2S2_MCK (MTK_PIN_NO(170) | 3)
+
+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define PINMUX_GPIO171__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(171) | 1)
+#define PINMUX_GPIO171__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(171) | 2)
+#define PINMUX_GPIO171__FUNC_I2S2_BCK (MTK_PIN_NO(171) | 3)
+
+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define PINMUX_GPIO172__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(172) | 1)
+#define PINMUX_GPIO172__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(172) | 2)
+#define PINMUX_GPIO172__FUNC_I2S2_LRCK (MTK_PIN_NO(172) | 3)
+#define PINMUX_GPIO172__FUNC_VOW_DAT_MISO (MTK_PIN_NO(172) | 4)
+
+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define PINMUX_GPIO173__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(173) | 1)
+#define PINMUX_GPIO173__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(173) | 2)
+#define PINMUX_GPIO173__FUNC_I2S2_DI (MTK_PIN_NO(173) | 3)
+#define PINMUX_GPIO173__FUNC_VOW_CLK_MISO (MTK_PIN_NO(173) | 4)
+
+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define PINMUX_GPIO174__FUNC_CONN_TOP_CLK (MTK_PIN_NO(174) | 1)
+#define PINMUX_GPIO174__FUNC_AUXIF_CLK (MTK_PIN_NO(174) | 2)
+#define PINMUX_GPIO174__FUNC_DFD_TCK_XI (MTK_PIN_NO(174) | 3)
+#define PINMUX_GPIO174__FUNC_DBG_MON_B3 (MTK_PIN_NO(174) | 7)
+
+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define PINMUX_GPIO175__FUNC_CONN_TOP_DATA (MTK_PIN_NO(175) | 1)
+#define PINMUX_GPIO175__FUNC_AUXIF_ST (MTK_PIN_NO(175) | 2)
+#define PINMUX_GPIO175__FUNC_DFD_TMS (MTK_PIN_NO(175) | 3)
+#define PINMUX_GPIO175__FUNC_DBG_MON_B15 (MTK_PIN_NO(175) | 7)
+
+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define PINMUX_GPIO176__FUNC_CONN_BT_CLK (MTK_PIN_NO(176) | 1)
+#define PINMUX_GPIO176__FUNC_DFD_TDI (MTK_PIN_NO(176) | 3)
+#define PINMUX_GPIO176__FUNC_DBG_MON_B2 (MTK_PIN_NO(176) | 7)
+
+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define PINMUX_GPIO177__FUNC_CONN_BT_DATA (MTK_PIN_NO(177) | 1)
+#define PINMUX_GPIO177__FUNC_DFD_TDO (MTK_PIN_NO(177) | 3)
+
+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define PINMUX_GPIO178__FUNC_CONN_HRST_B (MTK_PIN_NO(178) | 1)
+#define PINMUX_GPIO178__FUNC_UDI_TMS (MTK_PIN_NO(178) | 3)
+#define PINMUX_GPIO178__FUNC_DBG_MON_B25 (MTK_PIN_NO(178) | 7)
+
+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define PINMUX_GPIO179__FUNC_CONN_WB_PTA (MTK_PIN_NO(179) | 1)
+#define PINMUX_GPIO179__FUNC_UDI_TCK (MTK_PIN_NO(179) | 3)
+#define PINMUX_GPIO179__FUNC_DBG_MON_B29 (MTK_PIN_NO(179) | 7)
+
+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(180) | 1)
+#define PINMUX_GPIO180__FUNC_UDI_TDI (MTK_PIN_NO(180) | 3)
+
+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(181) | 1)
+#define PINMUX_GPIO181__FUNC_UDI_TDO (MTK_PIN_NO(181) | 3)
+
+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(182) | 1)
+#define PINMUX_GPIO182__FUNC_UDI_NTRST (MTK_PIN_NO(182) | 3)
+
+#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
+#define PINMUX_GPIO183__FUNC_SPMI_SCL (MTK_PIN_NO(183) | 1)
+
+#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
+#define PINMUX_GPIO184__FUNC_SPMI_SDA (MTK_PIN_NO(184) | 1)
+
+#endif /* __MT8168-PINFUNC_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186
2022-02-10 6:21 [PATCH v3 0/2] pinctrl: mediatek: Support pinctrl driver on mt8186 Guodong Liu
2022-02-10 6:21 ` [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document Guodong Liu
@ 2022-02-10 6:21 ` Guodong Liu
2022-02-10 8:57 ` AngeloGioacchino Del Regno
2022-02-10 6:21 ` [PATCH v3 3/3] pinctrl: canonical rsel resistance selection property Guodong Liu
2 siblings, 1 reply; 13+ messages in thread
From: Guodong Liu @ 2022-02-10 6:21 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Guodong Liu
This commit includes pinctrl driver for mt8186.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
---
drivers/pinctrl/mediatek/Kconfig | 7 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8186.c | 1313 ++++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h | 2186 +++++++++++++++++
4 files changed, 3507 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8186.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 66db4ac5d169..8dca1ef04965 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -147,6 +147,13 @@ config PINCTRL_MT8183
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
+config PINCTRL_MT8186
+ bool "Mediatek MT8186 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_PARIS
+
config PINCTRL_MT8192
bool "Mediatek MT8192 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 90f43bb9d9a7..31c3784c6089 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
+obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8186.c b/drivers/pinctrl/mediatek/pinctrl-mt8186.c
new file mode 100644
index 000000000000..1e550b15b9d4
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8186.c
@@ -0,0 +1,1313 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ *
+ * Author: Guodong Liu <guodong.liu@mediatek.com>
+ *
+ */
+
+#include "pinctrl-mtk-mt8186.h"
+#include "pinctrl-paris.h"
+
+/* MT8186 have multiple bases to program pin configuration listed as the below:
+ * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
+ * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
+ * iocfg[6]:0x10002C00.
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 0)
+
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+ PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+ 32, 1)
+
+static const struct mtk_pin_field_calc mt8186_pin_mode_range[] = {
+ PIN_FIELD(0, 184, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_dir_range[] = {
+ PIN_FIELD(0, 184, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_di_range[] = {
+ PIN_FIELD(0, 184, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_do_range[] = {
+ PIN_FIELD(0, 184, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_ies_range[] = {
+ PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1),
+ PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1),
+ PIN_FIELD_BASE(2, 2, 6, 0x0030, 0x10, 17, 1),
+ PIN_FIELD_BASE(3, 3, 6, 0x0030, 0x10, 18, 1),
+ PIN_FIELD_BASE(4, 4, 6, 0x0030, 0x10, 19, 1),
+ PIN_FIELD_BASE(5, 5, 6, 0x0030, 0x10, 20, 1),
+ PIN_FIELD_BASE(6, 6, 4, 0x0020, 0x10, 19, 1),
+ PIN_FIELD_BASE(7, 7, 4, 0x0020, 0x10, 20, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x0020, 0x10, 21, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x0020, 0x10, 22, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x0020, 0x10, 16, 1),
+ PIN_FIELD_BASE(11, 11, 4, 0x0020, 0x10, 17, 1),
+ PIN_FIELD_BASE(12, 12, 4, 0x0020, 0x10, 18, 1),
+ PIN_FIELD_BASE(13, 13, 3, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(14, 14, 3, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(15, 15, 6, 0x0030, 0x10, 15, 1),
+ PIN_FIELD_BASE(16, 16, 6, 0x0030, 0x10, 16, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(19, 19, 5, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(20, 20, 5, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(21, 21, 5, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(22, 22, 5, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(23, 23, 5, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(24, 24, 5, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(25, 25, 5, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(26, 26, 5, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, 5, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(28, 28, 5, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(29, 29, 6, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0030, 0x10, 1, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0030, 0x10, 2, 1),
+ PIN_FIELD_BASE(32, 32, 2, 0x0040, 0x10, 25, 1),
+ PIN_FIELD_BASE(33, 33, 2, 0x0040, 0x10, 27, 1),
+ PIN_FIELD_BASE(34, 34, 2, 0x0040, 0x10, 26, 1),
+ PIN_FIELD_BASE(35, 35, 2, 0x0040, 0x10, 28, 1),
+ PIN_FIELD_BASE(36, 36, 2, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(40, 40, 2, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(41, 41, 2, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(44, 44, 5, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(45, 45, 5, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(46, 46, 5, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(47, 47, 5, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(48, 48, 2, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0040, 0x10, 20, 1),
+ PIN_FIELD_BASE(51, 51, 2, 0x0040, 0x10, 19, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x0040, 0x10, 19, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x0040, 0x10, 21, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0040, 0x10, 20, 1),
+ PIN_FIELD_BASE(56, 56, 5, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(57, 57, 5, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, 5, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(59, 59, 5, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x0040, 0x10, 27, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 22, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 28, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 23, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 24, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 25, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 26, 1),
+ PIN_FIELD_BASE(67, 67, 1, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(69, 69, 1, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(70, 70, 1, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(71, 71, 1, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(72, 72, 1, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(73, 73, 1, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(74, 74, 1, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(75, 75, 1, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(76, 76, 1, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(77, 77, 1, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(78, 78, 1, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(79, 79, 5, 0x0050, 0x10, 24, 1),
+ PIN_FIELD_BASE(80, 80, 5, 0x0050, 0x10, 25, 1),
+ PIN_FIELD_BASE(81, 81, 5, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(82, 82, 5, 0x0050, 0x10, 27, 1),
+ PIN_FIELD_BASE(83, 83, 6, 0x0030, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(85, 85, 3, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(86, 86, 3, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(87, 87, 3, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(88, 88, 3, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(89, 89, 3, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(90, 90, 3, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(91, 91, 3, 0x0040, 0x10, 29, 1),
+ PIN_FIELD_BASE(92, 92, 3, 0x0040, 0x10, 31, 1),
+ PIN_FIELD_BASE(93, 93, 3, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(94, 94, 3, 0x0040, 0x10, 30, 1),
+ PIN_FIELD_BASE(95, 95, 3, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(99, 99, 4, 0x0020, 0x10, 14, 1),
+ PIN_FIELD_BASE(100, 100, 4, 0x0020, 0x10, 15, 1),
+ PIN_FIELD_BASE(101, 101, 4, 0x0020, 0x10, 13, 1),
+ PIN_FIELD_BASE(102, 102, 4, 0x0020, 0x10, 12, 1),
+ PIN_FIELD_BASE(103, 103, 4, 0x0020, 0x10, 0, 1),
+ PIN_FIELD_BASE(104, 104, 4, 0x0020, 0x10, 1, 1),
+ PIN_FIELD_BASE(105, 105, 4, 0x0020, 0x10, 4, 1),
+ PIN_FIELD_BASE(106, 106, 4, 0x0020, 0x10, 5, 1),
+ PIN_FIELD_BASE(107, 107, 4, 0x0020, 0x10, 6, 1),
+ PIN_FIELD_BASE(108, 108, 4, 0x0020, 0x10, 7, 1),
+ PIN_FIELD_BASE(109, 109, 4, 0x0020, 0x10, 8, 1),
+ PIN_FIELD_BASE(110, 110, 4, 0x0020, 0x10, 9, 1),
+ PIN_FIELD_BASE(111, 111, 4, 0x0020, 0x10, 10, 1),
+ PIN_FIELD_BASE(112, 112, 4, 0x0020, 0x10, 11, 1),
+ PIN_FIELD_BASE(113, 113, 4, 0x0020, 0x10, 2, 1),
+ PIN_FIELD_BASE(114, 114, 4, 0x0020, 0x10, 3, 1),
+ PIN_FIELD_BASE(115, 115, 3, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(116, 116, 3, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(117, 117, 3, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(118, 118, 3, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(119, 119, 5, 0x0050, 0x10, 22, 1),
+ PIN_FIELD_BASE(120, 120, 5, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(121, 121, 5, 0x0050, 0x10, 20, 1),
+ PIN_FIELD_BASE(122, 122, 5, 0x0050, 0x10, 21, 1),
+ PIN_FIELD_BASE(123, 123, 5, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(124, 124, 5, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(125, 125, 5, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 126, 5, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(127, 127, 3, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(128, 128, 3, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(129, 129, 5, 0x0050, 0x10, 28, 1),
+ PIN_FIELD_BASE(130, 130, 5, 0x0050, 0x10, 30, 1),
+ PIN_FIELD_BASE(131, 131, 5, 0x0050, 0x10, 29, 1),
+ PIN_FIELD_BASE(132, 132, 5, 0x0050, 0x10, 31, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x0050, 0x10, 21, 1),
+ PIN_FIELD_BASE(134, 134, 1, 0x0050, 0x10, 24, 1),
+ PIN_FIELD_BASE(135, 135, 6, 0x0030, 0x10, 21, 1),
+ PIN_FIELD_BASE(136, 136, 6, 0x0030, 0x10, 24, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x0050, 0x10, 22, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x0050, 0x10, 25, 1),
+ PIN_FIELD_BASE(139, 139, 2, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(140, 140, 2, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(141, 141, 3, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(142, 142, 3, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(143, 143, 6, 0x0030, 0x10, 22, 1),
+ PIN_FIELD_BASE(144, 144, 6, 0x0030, 0x10, 25, 1),
+ PIN_FIELD_BASE(145, 145, 6, 0x0030, 0x10, 23, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0030, 0x10, 26, 1),
+ PIN_FIELD_BASE(147, 147, 4, 0x0020, 0x10, 23, 1),
+ PIN_FIELD_BASE(148, 148, 4, 0x0020, 0x10, 24, 1),
+ PIN_FIELD_BASE(149, 149, 4, 0x0020, 0x10, 25, 1),
+ PIN_FIELD_BASE(150, 150, 4, 0x0020, 0x10, 26, 1),
+ PIN_FIELD_BASE(151, 151, 4, 0x0020, 0x10, 27, 1),
+ PIN_FIELD_BASE(152, 152, 4, 0x0020, 0x10, 28, 1),
+ PIN_FIELD_BASE(153, 153, 4, 0x0020, 0x10, 29, 1),
+ PIN_FIELD_BASE(154, 154, 4, 0x0020, 0x10, 30, 1),
+ PIN_FIELD_BASE(155, 155, 4, 0x0020, 0x10, 31, 1),
+ PIN_FIELD_BASE(156, 156, 4, 0x0030, 0x10, 0, 1),
+ PIN_FIELD_BASE(157, 157, 2, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(158, 158, 2, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(159, 159, 2, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(160, 160, 2, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(161, 161, 2, 0x0040, 0x10, 23, 1),
+ PIN_FIELD_BASE(162, 162, 2, 0x0040, 0x10, 24, 1),
+ PIN_FIELD_BASE(163, 163, 1, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(164, 164, 1, 0x0050, 0x10, 20, 1),
+ PIN_FIELD_BASE(165, 165, 1, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(166, 166, 1, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(167, 167, 1, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(168, 168, 1, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(169, 169, 1, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(170, 170, 1, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(171, 171, 1, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(172, 172, 1, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(173, 173, 1, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(174, 174, 6, 0x0030, 0x10, 7, 1),
+ PIN_FIELD_BASE(175, 175, 6, 0x0030, 0x10, 8, 1),
+ PIN_FIELD_BASE(176, 176, 6, 0x0030, 0x10, 4, 1),
+ PIN_FIELD_BASE(177, 177, 6, 0x0030, 0x10, 5, 1),
+ PIN_FIELD_BASE(178, 178, 6, 0x0030, 0x10, 6, 1),
+ PIN_FIELD_BASE(179, 179, 6, 0x0030, 0x10, 9, 1),
+ PIN_FIELD_BASE(180, 180, 6, 0x0030, 0x10, 10, 1),
+ PIN_FIELD_BASE(181, 181, 6, 0x0030, 0x10, 11, 1),
+ PIN_FIELD_BASE(182, 182, 6, 0x0030, 0x10, 12, 1),
+ PIN_FIELD_BASE(183, 183, 2, 0x0040, 0x10, 21, 1),
+ PIN_FIELD_BASE(184, 184, 2, 0x0040, 0x10, 22, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_smt_range[] = {
+ PIN_FIELD_BASE(0, 0, 6, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(1, 1, 6, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(2, 2, 6, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(3, 3, 6, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, 6, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, 6, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(11, 11, 4, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(12, 12, 4, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(13, 13, 3, 0x00e0, 0x10, 11, 1),
+ PIN_FIELD_BASE(14, 14, 3, 0x00e0, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, 6, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, 6, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(19, 19, 5, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, 5, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(21, 21, 5, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(22, 22, 5, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(23, 23, 5, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(24, 24, 5, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(25, 25, 5, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(26, 26, 5, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(27, 27, 5, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(28, 28, 5, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(32, 32, 2, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(33, 33, 2, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(34, 34, 2, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(35, 35, 2, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(36, 36, 2, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(40, 40, 2, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(41, 41, 2, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(44, 44, 5, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(45, 45, 5, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(46, 46, 5, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(47, 47, 5, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(48, 48, 2, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(51, 51, 2, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(56, 56, 5, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(57, 57, 5, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(58, 58, 5, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(59, 59, 5, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x00e0, 0x10, 6, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(67, 67, 1, 0x00f0, 0x10, 10, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x00f0, 0x10, 0, 1),
+ PIN_FIELD_BASE(69, 69, 1, 0x00f0, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 1, 0x00f0, 0x10, 11, 1),
+ PIN_FIELD_BASE(71, 71, 1, 0x00f0, 0x10, 2, 1),
+ PIN_FIELD_BASE(72, 72, 1, 0x00f0, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 1, 0x00f0, 0x10, 4, 1),
+ PIN_FIELD_BASE(74, 74, 1, 0x00f0, 0x10, 5, 1),
+ PIN_FIELD_BASE(75, 75, 1, 0x00f0, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, 1, 0x00f0, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, 1, 0x00f0, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, 1, 0x00f0, 0x10, 9, 1),
+ PIN_FIELD_BASE(79, 79, 5, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(80, 80, 5, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(81, 81, 5, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(82, 82, 5, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(83, 83, 6, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(84, 84, 3, 0x00e0, 0x10, 0, 1),
+ PIN_FIELD_BASE(85, 85, 3, 0x00e0, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 3, 0x00e0, 0x10, 2, 1),
+ PIN_FIELD_BASE(87, 87, 3, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(88, 88, 3, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(89, 89, 3, 0x00e0, 0x10, 5, 1),
+ PIN_FIELD_BASE(90, 90, 3, 0x00e0, 0x10, 7, 1),
+ PIN_FIELD_BASE(91, 91, 3, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(92, 92, 3, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(93, 93, 3, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(94, 94, 3, 0x00e0, 0x10, 8, 1),
+ PIN_FIELD_BASE(95, 95, 3, 0x00e0, 0x10, 9, 1),
+ PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(98, 98, 2, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(99, 99, 4, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(100, 100, 4, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(101, 101, 4, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(102, 102, 4, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(103, 103, 4, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(104, 104, 4, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(105, 105, 4, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(106, 106, 4, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(107, 107, 4, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(108, 108, 4, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(109, 109, 4, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(110, 110, 4, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(111, 111, 4, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(112, 112, 4, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(113, 113, 4, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(114, 114, 4, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(115, 115, 3, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(116, 116, 3, 0x00e0, 0x10, 11, 1),
+ PIN_FIELD_BASE(117, 117, 3, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(118, 118, 3, 0x00e0, 0x10, 10, 1),
+ PIN_FIELD_BASE(119, 119, 5, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(120, 120, 5, 0x00e0, 0x10, 4, 1),
+ PIN_FIELD_BASE(121, 121, 5, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(122, 122, 5, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(123, 123, 5, 0x00e0, 0x10, 3, 1),
+ PIN_FIELD_BASE(124, 124, 5, 0x00e0, 0x10, 0, 1),
+ PIN_FIELD_BASE(125, 125, 5, 0x00e0, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 126, 5, 0x00e0, 0x10, 2, 1),
+ PIN_FIELD_BASE(127, 127, 3, 0x00e0, 0x10, 12, 1),
+ PIN_FIELD_BASE(128, 128, 3, 0x00e0, 0x10, 14, 1),
+ PIN_FIELD_BASE(129, 129, 5, 0x00e0, 0x10, 11, 1),
+ PIN_FIELD_BASE(130, 130, 5, 0x00e0, 0x10, 13, 1),
+ PIN_FIELD_BASE(131, 131, 5, 0x00e0, 0x10, 12, 1),
+ PIN_FIELD_BASE(132, 132, 5, 0x00e0, 0x10, 14, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x00f0, 0x10, 15, 1),
+ PIN_FIELD_BASE(134, 134, 1, 0x00f0, 0x10, 17, 1),
+ PIN_FIELD_BASE(135, 135, 6, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(136, 136, 6, 0x0080, 0x10, 9, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x00f0, 0x10, 16, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x00f0, 0x10, 18, 1),
+ PIN_FIELD_BASE(139, 139, 2, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(140, 140, 2, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 13, 1),
+ PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 15, 1),
+ PIN_FIELD_BASE(143, 143, 6, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(144, 144, 6, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(145, 145, 6, 0x0080, 0x10, 8, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(147, 147, 4, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(148, 148, 4, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(149, 149, 4, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(150, 150, 4, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(151, 151, 4, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(152, 152, 4, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(153, 153, 4, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(154, 154, 4, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(155, 155, 4, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(156, 156, 4, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(157, 157, 2, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(158, 158, 2, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(159, 159, 2, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(160, 160, 2, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(161, 161, 2, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(162, 162, 2, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(163, 163, 1, 0x00f0, 0x10, 14, 1),
+ PIN_FIELD_BASE(164, 164, 1, 0x00f0, 0x10, 12, 1),
+ PIN_FIELD_BASE(165, 165, 1, 0x00f0, 0x10, 12, 1),
+ PIN_FIELD_BASE(166, 166, 1, 0x00f0, 0x10, 13, 1),
+ PIN_FIELD_BASE(167, 167, 1, 0x00f0, 0x10, 13, 1),
+ PIN_FIELD_BASE(168, 168, 1, 0x00f0, 0x10, 12, 1),
+ PIN_FIELD_BASE(169, 169, 1, 0x00f0, 0x10, 14, 1),
+ PIN_FIELD_BASE(170, 170, 1, 0x00f0, 0x10, 13, 1),
+ PIN_FIELD_BASE(171, 171, 1, 0x00f0, 0x10, 13, 1),
+ PIN_FIELD_BASE(172, 172, 1, 0x00f0, 0x10, 14, 1),
+ PIN_FIELD_BASE(173, 173, 1, 0x00f0, 0x10, 12, 1),
+ PIN_FIELD_BASE(174, 174, 6, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(175, 175, 6, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(176, 176, 6, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(177, 177, 6, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(178, 178, 6, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(179, 179, 6, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(180, 180, 6, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(181, 181, 6, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(182, 182, 6, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(183, 183, 2, 0x0090, 0x10, 9, 1),
+ PIN_FIELD_BASE(184, 184, 2, 0x0090, 0x10, 10, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_pu_range[] = {
+ PIN_FIELD_BASE(0, 0, 6, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(1, 1, 6, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(2, 2, 6, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(3, 3, 6, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(4, 4, 6, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(5, 5, 6, 0x0050, 0x10, 20, 1),
+ PIN_FIELD_BASE(6, 6, 4, 0x0060, 0x10, 19, 1),
+ PIN_FIELD_BASE(7, 7, 4, 0x0060, 0x10, 20, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x0060, 0x10, 21, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x0060, 0x10, 22, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(11, 11, 4, 0x0060, 0x10, 17, 1),
+ PIN_FIELD_BASE(12, 12, 4, 0x0060, 0x10, 18, 1),
+ PIN_FIELD_BASE(13, 13, 3, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(15, 15, 6, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(16, 16, 6, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0x0090, 0x10, 9, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0x0090, 0x10, 10, 1),
+ PIN_FIELD_BASE(19, 19, 5, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(20, 20, 5, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(21, 21, 5, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(22, 22, 5, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(23, 23, 5, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(24, 24, 5, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(25, 25, 5, 0x0090, 0x10, 18, 1),
+ PIN_FIELD_BASE(26, 26, 5, 0x0090, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, 5, 0x0090, 0x10, 17, 1),
+ PIN_FIELD_BASE(28, 28, 5, 0x0090, 0x10, 16, 1),
+ PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(32, 32, 2, 0x0060, 0x10, 25, 1),
+ PIN_FIELD_BASE(33, 33, 2, 0x0060, 0x10, 27, 1),
+ PIN_FIELD_BASE(34, 34, 2, 0x0060, 0x10, 26, 1),
+ PIN_FIELD_BASE(35, 35, 2, 0x0060, 0x10, 28, 1),
+ PIN_FIELD_BASE(36, 36, 2, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(40, 40, 2, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(41, 41, 2, 0x0060, 0x10, 14, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0060, 0x10, 15, 1),
+ PIN_FIELD_BASE(44, 44, 5, 0x0090, 0x10, 28, 1),
+ PIN_FIELD_BASE(45, 45, 5, 0x0090, 0x10, 29, 1),
+ PIN_FIELD_BASE(46, 46, 5, 0x0090, 0x10, 31, 1),
+ PIN_FIELD_BASE(47, 47, 5, 0x0090, 0x10, 30, 1),
+ PIN_FIELD_BASE(48, 48, 2, 0x0060, 0x10, 17, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0060, 0x10, 18, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0060, 0x10, 20, 1),
+ PIN_FIELD_BASE(51, 51, 2, 0x0060, 0x10, 19, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x0080, 0x10, 12, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x0080, 0x10, 13, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x0080, 0x10, 15, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0080, 0x10, 14, 1),
+ PIN_FIELD_BASE(56, 56, 5, 0x0090, 0x10, 12, 1),
+ PIN_FIELD_BASE(57, 57, 5, 0x0090, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, 5, 0x0090, 0x10, 13, 1),
+ PIN_FIELD_BASE(59, 59, 5, 0x0090, 0x10, 14, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 21, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0080, 0x10, 16, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0080, 0x10, 22, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0080, 0x10, 17, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0080, 0x10, 18, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0080, 0x10, 19, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0080, 0x10, 20, 1),
+ PIN_FIELD_BASE(83, 83, 6, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(91, 91, 3, 0x0080, 0x10, 23, 1),
+ PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 25, 1),
+ PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 24, 1),
+ PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 26, 1),
+ PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(99, 99, 4, 0x0060, 0x10, 14, 1),
+ PIN_FIELD_BASE(100, 100, 4, 0x0060, 0x10, 15, 1),
+ PIN_FIELD_BASE(101, 101, 4, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(102, 102, 4, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(103, 103, 4, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(104, 104, 4, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(105, 105, 4, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(106, 106, 4, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(107, 107, 4, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(108, 108, 4, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(109, 109, 4, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(110, 110, 4, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(111, 111, 4, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(112, 112, 4, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(113, 113, 4, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(114, 114, 4, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(115, 115, 3, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(116, 116, 3, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(117, 117, 3, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(118, 118, 3, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(119, 119, 5, 0x0090, 0x10, 22, 1),
+ PIN_FIELD_BASE(120, 120, 5, 0x0090, 0x10, 19, 1),
+ PIN_FIELD_BASE(121, 121, 5, 0x0090, 0x10, 20, 1),
+ PIN_FIELD_BASE(122, 122, 5, 0x0090, 0x10, 21, 1),
+ PIN_FIELD_BASE(123, 123, 5, 0x0090, 0x10, 23, 1),
+ PIN_FIELD_BASE(124, 124, 5, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(125, 125, 5, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 126, 5, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(127, 127, 3, 0x0080, 0x10, 8, 1),
+ PIN_FIELD_BASE(128, 128, 3, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(129, 129, 5, 0x0090, 0x10, 24, 1),
+ PIN_FIELD_BASE(130, 130, 5, 0x0090, 0x10, 26, 1),
+ PIN_FIELD_BASE(131, 131, 5, 0x0090, 0x10, 25, 1),
+ PIN_FIELD_BASE(132, 132, 5, 0x0090, 0x10, 27, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 9, 1),
+ PIN_FIELD_BASE(134, 134, 1, 0x0080, 0x10, 12, 1),
+ PIN_FIELD_BASE(135, 135, 6, 0x0050, 0x10, 21, 1),
+ PIN_FIELD_BASE(136, 136, 6, 0x0050, 0x10, 24, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x0080, 0x10, 10, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x0080, 0x10, 13, 1),
+ PIN_FIELD_BASE(139, 139, 2, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(140, 140, 2, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(141, 141, 3, 0x0080, 0x10, 9, 1),
+ PIN_FIELD_BASE(142, 142, 3, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(143, 143, 6, 0x0050, 0x10, 22, 1),
+ PIN_FIELD_BASE(144, 144, 6, 0x0050, 0x10, 25, 1),
+ PIN_FIELD_BASE(145, 145, 6, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(147, 147, 4, 0x0060, 0x10, 23, 1),
+ PIN_FIELD_BASE(148, 148, 4, 0x0060, 0x10, 24, 1),
+ PIN_FIELD_BASE(149, 149, 4, 0x0060, 0x10, 25, 1),
+ PIN_FIELD_BASE(150, 150, 4, 0x0060, 0x10, 26, 1),
+ PIN_FIELD_BASE(151, 151, 4, 0x0060, 0x10, 27, 1),
+ PIN_FIELD_BASE(152, 152, 4, 0x0060, 0x10, 28, 1),
+ PIN_FIELD_BASE(153, 153, 4, 0x0060, 0x10, 29, 1),
+ PIN_FIELD_BASE(154, 154, 4, 0x0060, 0x10, 30, 1),
+ PIN_FIELD_BASE(155, 155, 4, 0x0060, 0x10, 31, 1),
+ PIN_FIELD_BASE(156, 156, 4, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(157, 157, 2, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(158, 158, 2, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(159, 159, 2, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(160, 160, 2, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(161, 161, 2, 0x0060, 0x10, 23, 1),
+ PIN_FIELD_BASE(162, 162, 2, 0x0060, 0x10, 24, 1),
+ PIN_FIELD_BASE(163, 163, 1, 0x0080, 0x10, 11, 1),
+ PIN_FIELD_BASE(164, 164, 1, 0x0080, 0x10, 8, 1),
+ PIN_FIELD_BASE(165, 165, 1, 0x0080, 0x10, 16, 1),
+ PIN_FIELD_BASE(166, 166, 1, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(167, 167, 1, 0x0080, 0x10, 7, 1),
+ PIN_FIELD_BASE(168, 168, 1, 0x0080, 0x10, 4, 1),
+ PIN_FIELD_BASE(169, 169, 1, 0x0080, 0x10, 5, 1),
+ PIN_FIELD_BASE(170, 170, 1, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(171, 171, 1, 0x0080, 0x10, 6, 1),
+ PIN_FIELD_BASE(172, 172, 1, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(173, 173, 1, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(174, 174, 6, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(175, 175, 6, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(176, 176, 6, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(177, 177, 6, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(178, 178, 6, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(179, 179, 6, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(180, 180, 6, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(181, 181, 6, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(182, 182, 6, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(183, 183, 2, 0x0060, 0x10, 21, 1),
+ PIN_FIELD_BASE(184, 184, 2, 0x0060, 0x10, 22, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_pd_range[] = {
+ PIN_FIELD_BASE(0, 0, 6, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(1, 1, 6, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(2, 2, 6, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(3, 3, 6, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(4, 4, 6, 0x0040, 0x10, 19, 1),
+ PIN_FIELD_BASE(5, 5, 6, 0x0040, 0x10, 20, 1),
+ PIN_FIELD_BASE(6, 6, 4, 0x0040, 0x10, 19, 1),
+ PIN_FIELD_BASE(7, 7, 4, 0x0040, 0x10, 20, 1),
+ PIN_FIELD_BASE(8, 8, 4, 0x0040, 0x10, 21, 1),
+ PIN_FIELD_BASE(9, 9, 4, 0x0040, 0x10, 22, 1),
+ PIN_FIELD_BASE(10, 10, 4, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(11, 11, 4, 0x0040, 0x10, 17, 1),
+ PIN_FIELD_BASE(12, 12, 4, 0x0040, 0x10, 18, 1),
+ PIN_FIELD_BASE(13, 13, 3, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(14, 14, 3, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 16, 1),
+ PIN_FIELD_BASE(17, 17, 5, 0x0070, 0x10, 9, 1),
+ PIN_FIELD_BASE(18, 18, 5, 0x0070, 0x10, 10, 1),
+ PIN_FIELD_BASE(19, 19, 5, 0x0070, 0x10, 3, 1),
+ PIN_FIELD_BASE(20, 20, 5, 0x0070, 0x10, 6, 1),
+ PIN_FIELD_BASE(21, 21, 5, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(22, 22, 5, 0x0070, 0x10, 7, 1),
+ PIN_FIELD_BASE(23, 23, 5, 0x0070, 0x10, 5, 1),
+ PIN_FIELD_BASE(24, 24, 5, 0x0070, 0x10, 8, 1),
+ PIN_FIELD_BASE(25, 25, 5, 0x0070, 0x10, 18, 1),
+ PIN_FIELD_BASE(26, 26, 5, 0x0070, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, 5, 0x0070, 0x10, 17, 1),
+ PIN_FIELD_BASE(28, 28, 5, 0x0070, 0x10, 16, 1),
+ PIN_FIELD_BASE(29, 29, 6, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(30, 30, 6, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(31, 31, 6, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(32, 32, 2, 0x0050, 0x10, 25, 1),
+ PIN_FIELD_BASE(33, 33, 2, 0x0050, 0x10, 27, 1),
+ PIN_FIELD_BASE(34, 34, 2, 0x0050, 0x10, 26, 1),
+ PIN_FIELD_BASE(35, 35, 2, 0x0050, 0x10, 28, 1),
+ PIN_FIELD_BASE(36, 36, 2, 0x0050, 0x10, 9, 1),
+ PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 10, 1),
+ PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 12, 1),
+ PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 11, 1),
+ PIN_FIELD_BASE(40, 40, 2, 0x0050, 0x10, 13, 1),
+ PIN_FIELD_BASE(41, 41, 2, 0x0050, 0x10, 14, 1),
+ PIN_FIELD_BASE(42, 42, 2, 0x0050, 0x10, 16, 1),
+ PIN_FIELD_BASE(43, 43, 2, 0x0050, 0x10, 15, 1),
+ PIN_FIELD_BASE(44, 44, 5, 0x0070, 0x10, 28, 1),
+ PIN_FIELD_BASE(45, 45, 5, 0x0070, 0x10, 29, 1),
+ PIN_FIELD_BASE(46, 46, 5, 0x0070, 0x10, 31, 1),
+ PIN_FIELD_BASE(47, 47, 5, 0x0070, 0x10, 30, 1),
+ PIN_FIELD_BASE(48, 48, 2, 0x0050, 0x10, 17, 1),
+ PIN_FIELD_BASE(49, 49, 2, 0x0050, 0x10, 18, 1),
+ PIN_FIELD_BASE(50, 50, 2, 0x0050, 0x10, 20, 1),
+ PIN_FIELD_BASE(51, 51, 2, 0x0050, 0x10, 19, 1),
+ PIN_FIELD_BASE(52, 52, 3, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(53, 53, 3, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(54, 54, 3, 0x0060, 0x10, 15, 1),
+ PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 14, 1),
+ PIN_FIELD_BASE(56, 56, 5, 0x0070, 0x10, 12, 1),
+ PIN_FIELD_BASE(57, 57, 5, 0x0070, 0x10, 11, 1),
+ PIN_FIELD_BASE(58, 58, 5, 0x0070, 0x10, 13, 1),
+ PIN_FIELD_BASE(59, 59, 5, 0x0070, 0x10, 14, 1),
+ PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 21, 1),
+ PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(62, 62, 3, 0x0060, 0x10, 22, 1),
+ PIN_FIELD_BASE(63, 63, 3, 0x0060, 0x10, 17, 1),
+ PIN_FIELD_BASE(64, 64, 3, 0x0060, 0x10, 18, 1),
+ PIN_FIELD_BASE(65, 65, 3, 0x0060, 0x10, 19, 1),
+ PIN_FIELD_BASE(66, 66, 3, 0x0060, 0x10, 20, 1),
+ PIN_FIELD_BASE(83, 83, 6, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(91, 91, 3, 0x0060, 0x10, 23, 1),
+ PIN_FIELD_BASE(92, 92, 3, 0x0060, 0x10, 25, 1),
+ PIN_FIELD_BASE(93, 93, 3, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(94, 94, 3, 0x0060, 0x10, 24, 1),
+ PIN_FIELD_BASE(95, 95, 3, 0x0060, 0x10, 26, 1),
+ PIN_FIELD_BASE(96, 96, 2, 0x0050, 0x10, 1, 1),
+ PIN_FIELD_BASE(97, 97, 2, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(98, 98, 2, 0x0050, 0x10, 2, 1),
+ PIN_FIELD_BASE(99, 99, 4, 0x0040, 0x10, 14, 1),
+ PIN_FIELD_BASE(100, 100, 4, 0x0040, 0x10, 15, 1),
+ PIN_FIELD_BASE(101, 101, 4, 0x0040, 0x10, 13, 1),
+ PIN_FIELD_BASE(102, 102, 4, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(103, 103, 4, 0x0040, 0x10, 0, 1),
+ PIN_FIELD_BASE(104, 104, 4, 0x0040, 0x10, 1, 1),
+ PIN_FIELD_BASE(105, 105, 4, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(106, 106, 4, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(107, 107, 4, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(108, 108, 4, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(109, 109, 4, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(110, 110, 4, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(111, 111, 4, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(112, 112, 4, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(113, 113, 4, 0x0040, 0x10, 2, 1),
+ PIN_FIELD_BASE(114, 114, 4, 0x0040, 0x10, 3, 1),
+ PIN_FIELD_BASE(115, 115, 3, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(116, 116, 3, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(117, 117, 3, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(118, 118, 3, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(119, 119, 5, 0x0070, 0x10, 22, 1),
+ PIN_FIELD_BASE(120, 120, 5, 0x0070, 0x10, 19, 1),
+ PIN_FIELD_BASE(121, 121, 5, 0x0070, 0x10, 20, 1),
+ PIN_FIELD_BASE(122, 122, 5, 0x0070, 0x10, 21, 1),
+ PIN_FIELD_BASE(123, 123, 5, 0x0070, 0x10, 23, 1),
+ PIN_FIELD_BASE(124, 124, 5, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(125, 125, 5, 0x0070, 0x10, 1, 1),
+ PIN_FIELD_BASE(126, 126, 5, 0x0070, 0x10, 2, 1),
+ PIN_FIELD_BASE(127, 127, 3, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(128, 128, 3, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(129, 129, 5, 0x0070, 0x10, 24, 1),
+ PIN_FIELD_BASE(130, 130, 5, 0x0070, 0x10, 26, 1),
+ PIN_FIELD_BASE(131, 131, 5, 0x0070, 0x10, 25, 1),
+ PIN_FIELD_BASE(132, 132, 5, 0x0070, 0x10, 27, 1),
+ PIN_FIELD_BASE(133, 133, 1, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(134, 134, 1, 0x0060, 0x10, 12, 1),
+ PIN_FIELD_BASE(135, 135, 6, 0x0040, 0x10, 21, 1),
+ PIN_FIELD_BASE(136, 136, 6, 0x0040, 0x10, 24, 1),
+ PIN_FIELD_BASE(137, 137, 1, 0x0060, 0x10, 10, 1),
+ PIN_FIELD_BASE(138, 138, 1, 0x0060, 0x10, 13, 1),
+ PIN_FIELD_BASE(139, 139, 2, 0x0050, 0x10, 7, 1),
+ PIN_FIELD_BASE(140, 140, 2, 0x0050, 0x10, 8, 1),
+ PIN_FIELD_BASE(141, 141, 3, 0x0060, 0x10, 9, 1),
+ PIN_FIELD_BASE(142, 142, 3, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(143, 143, 6, 0x0040, 0x10, 22, 1),
+ PIN_FIELD_BASE(144, 144, 6, 0x0040, 0x10, 25, 1),
+ PIN_FIELD_BASE(145, 145, 6, 0x0040, 0x10, 23, 1),
+ PIN_FIELD_BASE(146, 146, 6, 0x0040, 0x10, 26, 1),
+ PIN_FIELD_BASE(147, 147, 4, 0x0040, 0x10, 23, 1),
+ PIN_FIELD_BASE(148, 148, 4, 0x0040, 0x10, 24, 1),
+ PIN_FIELD_BASE(149, 149, 4, 0x0040, 0x10, 25, 1),
+ PIN_FIELD_BASE(150, 150, 4, 0x0040, 0x10, 26, 1),
+ PIN_FIELD_BASE(151, 151, 4, 0x0040, 0x10, 27, 1),
+ PIN_FIELD_BASE(152, 152, 4, 0x0040, 0x10, 28, 1),
+ PIN_FIELD_BASE(153, 153, 4, 0x0040, 0x10, 29, 1),
+ PIN_FIELD_BASE(154, 154, 4, 0x0040, 0x10, 30, 1),
+ PIN_FIELD_BASE(155, 155, 4, 0x0040, 0x10, 31, 1),
+ PIN_FIELD_BASE(156, 156, 4, 0x0050, 0x10, 0, 1),
+ PIN_FIELD_BASE(157, 157, 2, 0x0050, 0x10, 4, 1),
+ PIN_FIELD_BASE(158, 158, 2, 0x0050, 0x10, 3, 1),
+ PIN_FIELD_BASE(159, 159, 2, 0x0050, 0x10, 6, 1),
+ PIN_FIELD_BASE(160, 160, 2, 0x0050, 0x10, 5, 1),
+ PIN_FIELD_BASE(161, 161, 2, 0x0050, 0x10, 23, 1),
+ PIN_FIELD_BASE(162, 162, 2, 0x0050, 0x10, 24, 1),
+ PIN_FIELD_BASE(163, 163, 1, 0x0060, 0x10, 11, 1),
+ PIN_FIELD_BASE(164, 164, 1, 0x0060, 0x10, 8, 1),
+ PIN_FIELD_BASE(165, 165, 1, 0x0060, 0x10, 16, 1),
+ PIN_FIELD_BASE(166, 166, 1, 0x0060, 0x10, 1, 1),
+ PIN_FIELD_BASE(167, 167, 1, 0x0060, 0x10, 7, 1),
+ PIN_FIELD_BASE(168, 168, 1, 0x0060, 0x10, 4, 1),
+ PIN_FIELD_BASE(169, 169, 1, 0x0060, 0x10, 5, 1),
+ PIN_FIELD_BASE(170, 170, 1, 0x0060, 0x10, 0, 1),
+ PIN_FIELD_BASE(171, 171, 1, 0x0060, 0x10, 6, 1),
+ PIN_FIELD_BASE(172, 172, 1, 0x0060, 0x10, 2, 1),
+ PIN_FIELD_BASE(173, 173, 1, 0x0060, 0x10, 3, 1),
+ PIN_FIELD_BASE(174, 174, 6, 0x0040, 0x10, 7, 1),
+ PIN_FIELD_BASE(175, 175, 6, 0x0040, 0x10, 8, 1),
+ PIN_FIELD_BASE(176, 176, 6, 0x0040, 0x10, 4, 1),
+ PIN_FIELD_BASE(177, 177, 6, 0x0040, 0x10, 5, 1),
+ PIN_FIELD_BASE(178, 178, 6, 0x0040, 0x10, 6, 1),
+ PIN_FIELD_BASE(179, 179, 6, 0x0040, 0x10, 9, 1),
+ PIN_FIELD_BASE(180, 180, 6, 0x0040, 0x10, 10, 1),
+ PIN_FIELD_BASE(181, 181, 6, 0x0040, 0x10, 11, 1),
+ PIN_FIELD_BASE(182, 182, 6, 0x0040, 0x10, 12, 1),
+ PIN_FIELD_BASE(183, 183, 2, 0x0050, 0x10, 21, 1),
+ PIN_FIELD_BASE(184, 184, 2, 0x0050, 0x10, 22, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_pupd_range[] = {
+ PIN_FIELD_BASE(67, 67, 1, 0x0070, 0x10, 10, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(69, 69, 1, 0x0070, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 1, 0x0070, 0x10, 11, 1),
+ PIN_FIELD_BASE(71, 71, 1, 0x0070, 0x10, 2, 1),
+ PIN_FIELD_BASE(72, 72, 1, 0x0070, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 1, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(74, 74, 1, 0x0070, 0x10, 5, 1),
+ PIN_FIELD_BASE(75, 75, 1, 0x0070, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, 1, 0x0070, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, 1, 0x0070, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, 1, 0x0070, 0x10, 9, 1),
+ PIN_FIELD_BASE(79, 79, 5, 0x0080, 0x10, 0, 1),
+ PIN_FIELD_BASE(80, 80, 5, 0x0080, 0x10, 1, 1),
+ PIN_FIELD_BASE(81, 81, 5, 0x0080, 0x10, 2, 1),
+ PIN_FIELD_BASE(82, 82, 5, 0x0080, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 3, 0x0070, 0x10, 0, 1),
+ PIN_FIELD_BASE(85, 85, 3, 0x0070, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 3, 0x0070, 0x10, 2, 1),
+ PIN_FIELD_BASE(87, 87, 3, 0x0070, 0x10, 3, 1),
+ PIN_FIELD_BASE(88, 88, 3, 0x0070, 0x10, 4, 1),
+ PIN_FIELD_BASE(89, 89, 3, 0x0070, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_r0_range[] = {
+ PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 10, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 11, 1),
+ PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 5, 1),
+ PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, 1, 0x0090, 0x10, 9, 1),
+ PIN_FIELD_BASE(79, 79, 5, 0x00a0, 0x10, 0, 1),
+ PIN_FIELD_BASE(80, 80, 5, 0x00a0, 0x10, 1, 1),
+ PIN_FIELD_BASE(81, 81, 5, 0x00a0, 0x10, 2, 1),
+ PIN_FIELD_BASE(82, 82, 5, 0x00a0, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 3, 0x0090, 0x10, 0, 1),
+ PIN_FIELD_BASE(85, 85, 3, 0x0090, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 3, 0x0090, 0x10, 2, 1),
+ PIN_FIELD_BASE(87, 87, 3, 0x0090, 0x10, 3, 1),
+ PIN_FIELD_BASE(88, 88, 3, 0x0090, 0x10, 4, 1),
+ PIN_FIELD_BASE(89, 89, 3, 0x0090, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_r1_range[] = {
+ PIN_FIELD_BASE(67, 67, 1, 0x00a0, 0x10, 10, 1),
+ PIN_FIELD_BASE(68, 68, 1, 0x00a0, 0x10, 0, 1),
+ PIN_FIELD_BASE(69, 69, 1, 0x00a0, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, 1, 0x00a0, 0x10, 11, 1),
+ PIN_FIELD_BASE(71, 71, 1, 0x00a0, 0x10, 2, 1),
+ PIN_FIELD_BASE(72, 72, 1, 0x00a0, 0x10, 3, 1),
+ PIN_FIELD_BASE(73, 73, 1, 0x00a0, 0x10, 4, 1),
+ PIN_FIELD_BASE(74, 74, 1, 0x00a0, 0x10, 5, 1),
+ PIN_FIELD_BASE(75, 75, 1, 0x00a0, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, 1, 0x00a0, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, 1, 0x00a0, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, 1, 0x00a0, 0x10, 9, 1),
+ PIN_FIELD_BASE(79, 79, 5, 0x00b0, 0x10, 0, 1),
+ PIN_FIELD_BASE(80, 80, 5, 0x00b0, 0x10, 1, 1),
+ PIN_FIELD_BASE(81, 81, 5, 0x00b0, 0x10, 2, 1),
+ PIN_FIELD_BASE(82, 82, 5, 0x00b0, 0x10, 3, 1),
+ PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 0, 1),
+ PIN_FIELD_BASE(85, 85, 3, 0x00a0, 0x10, 1, 1),
+ PIN_FIELD_BASE(86, 86, 3, 0x00a0, 0x10, 2, 1),
+ PIN_FIELD_BASE(87, 87, 3, 0x00a0, 0x10, 3, 1),
+ PIN_FIELD_BASE(88, 88, 3, 0x00a0, 0x10, 4, 1),
+ PIN_FIELD_BASE(89, 89, 3, 0x00a0, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_drv_range[] = {
+ PIN_FIELD_BASE(0, 0, 6, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(1, 1, 6, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(2, 2, 6, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(3, 3, 6, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(4, 4, 6, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(5, 5, 6, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(6, 6, 4, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(7, 7, 4, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(8, 8, 4, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(9, 9, 4, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(10, 10, 4, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(11, 11, 4, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(12, 12, 4, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(13, 13, 3, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(15, 15, 6, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(17, 17, 5, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(18, 18, 5, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(19, 19, 5, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(20, 20, 5, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(21, 21, 5, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(22, 22, 5, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(23, 23, 5, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(24, 24, 5, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(25, 25, 5, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(26, 26, 5, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(27, 27, 5, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(28, 28, 5, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(29, 29, 6, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(30, 30, 6, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(31, 31, 6, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(32, 32, 2, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(33, 33, 2, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(34, 34, 2, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(35, 35, 2, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(36, 36, 2, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(37, 37, 2, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(38, 38, 2, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(39, 39, 2, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(40, 40, 2, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(41, 41, 2, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(42, 42, 2, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(43, 43, 2, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(44, 44, 5, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(45, 45, 5, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(46, 46, 5, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(47, 47, 5, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(48, 48, 2, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(49, 49, 2, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(50, 50, 2, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(51, 51, 2, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(53, 53, 3, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(54, 54, 3, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(56, 56, 5, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(57, 57, 5, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(58, 58, 5, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(59, 59, 5, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(60, 60, 3, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(61, 61, 3, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(62, 62, 3, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(63, 63, 3, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(64, 64, 3, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(65, 65, 3, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(66, 66, 3, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(67, 67, 1, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(68, 68, 1, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(69, 69, 1, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(70, 70, 1, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(71, 71, 1, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(72, 72, 1, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(73, 73, 1, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(74, 74, 1, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(75, 75, 1, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(76, 76, 1, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(77, 77, 1, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(78, 78, 1, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(79, 79, 5, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(80, 80, 5, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(81, 81, 5, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(82, 82, 5, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(83, 83, 6, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(84, 84, 3, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(85, 85, 3, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(86, 86, 3, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(87, 87, 3, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(88, 88, 3, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(89, 89, 3, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(91, 91, 3, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(92, 92, 3, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(93, 93, 3, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(94, 94, 3, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(95, 95, 3, 0x0010, 0x10, 3, 3),
+ PIN_FIELD_BASE(96, 96, 2, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(97, 97, 2, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(98, 98, 2, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(99, 99, 4, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(100, 100, 4, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(101, 101, 4, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(102, 102, 4, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(103, 103, 4, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(104, 104, 4, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(105, 105, 4, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(106, 106, 4, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(107, 107, 4, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(108, 108, 4, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(109, 109, 4, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(110, 110, 4, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(111, 111, 4, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(112, 112, 4, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(113, 113, 4, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(114, 114, 4, 0x0010, 0x10, 0, 3),
+ PIN_FIELD_BASE(115, 115, 3, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(116, 116, 3, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(117, 117, 3, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(118, 118, 3, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(119, 119, 5, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(120, 120, 5, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(121, 121, 5, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(122, 122, 5, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(123, 123, 5, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(124, 124, 5, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(125, 125, 5, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(126, 126, 5, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(127, 127, 3, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(128, 128, 3, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(129, 129, 5, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(130, 130, 5, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(131, 131, 5, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(132, 132, 5, 0x0010, 0x10, 21, 3),
+ PIN_FIELD_BASE(133, 133, 1, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(134, 134, 1, 0x0010, 0x10, 21, 3),
+ PIN_FIELD_BASE(135, 135, 6, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(136, 136, 6, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(137, 137, 1, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(138, 138, 1, 0x0010, 0x10, 24, 3),
+ PIN_FIELD_BASE(139, 139, 2, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(140, 140, 2, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(141, 141, 3, 0x0010, 0x10, 15, 3),
+ PIN_FIELD_BASE(142, 142, 3, 0x0010, 0x10, 21, 3),
+ PIN_FIELD_BASE(143, 143, 6, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(144, 144, 6, 0x0010, 0x10, 18, 3),
+ PIN_FIELD_BASE(145, 145, 6, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(146, 146, 6, 0x0010, 0x10, 21, 3),
+ PIN_FIELD_BASE(147, 147, 4, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(148, 148, 4, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(149, 149, 4, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(150, 150, 4, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(151, 151, 4, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(152, 152, 4, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(153, 153, 4, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(154, 154, 4, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(155, 155, 4, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(156, 156, 4, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(157, 157, 2, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(158, 158, 2, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(159, 159, 2, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(160, 160, 2, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(161, 161, 2, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(162, 162, 2, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(163, 163, 1, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(165, 165, 1, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(166, 166, 1, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(167, 167, 1, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(168, 168, 1, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(169, 169, 1, 0x0010, 0x10, 12, 3),
+ PIN_FIELD_BASE(170, 170, 1, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(171, 171, 1, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(172, 172, 1, 0x0010, 0x10, 9, 3),
+ PIN_FIELD_BASE(173, 173, 1, 0x0010, 0x10, 6, 3),
+ PIN_FIELD_BASE(174, 174, 6, 0x0000, 0x10, 9, 3),
+ PIN_FIELD_BASE(175, 175, 6, 0x0000, 0x10, 12, 3),
+ PIN_FIELD_BASE(176, 176, 6, 0x0000, 0x10, 0, 3),
+ PIN_FIELD_BASE(177, 177, 6, 0x0000, 0x10, 3, 3),
+ PIN_FIELD_BASE(178, 178, 6, 0x0000, 0x10, 6, 3),
+ PIN_FIELD_BASE(179, 179, 6, 0x0000, 0x10, 15, 3),
+ PIN_FIELD_BASE(180, 180, 6, 0x0000, 0x10, 18, 3),
+ PIN_FIELD_BASE(181, 181, 6, 0x0000, 0x10, 21, 3),
+ PIN_FIELD_BASE(182, 182, 6, 0x0000, 0x10, 24, 3),
+ PIN_FIELD_BASE(183, 183, 2, 0x0000, 0x10, 27, 3),
+ PIN_FIELD_BASE(184, 184, 2, 0x0010, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_drv_adv_range[] = {
+ PIN_FIELD_BASE(127, 127, 3, 0x0030, 0x10, 0, 3),
+ PIN_FIELD_BASE(128, 128, 3, 0x0030, 0x10, 6, 3),
+ PIN_FIELD_BASE(129, 129, 5, 0x0030, 0x10, 0, 3),
+ PIN_FIELD_BASE(130, 130, 5, 0x0030, 0x10, 6, 3),
+ PIN_FIELD_BASE(131, 131, 5, 0x0030, 0x10, 3, 3),
+ PIN_FIELD_BASE(132, 132, 5, 0x0030, 0x10, 9, 3),
+ PIN_FIELD_BASE(133, 133, 1, 0x0030, 0x10, 0, 3),
+ PIN_FIELD_BASE(134, 134, 1, 0x0030, 0x10, 6, 3),
+ PIN_FIELD_BASE(135, 135, 6, 0x0020, 0x10, 0, 3),
+ PIN_FIELD_BASE(136, 136, 6, 0x0020, 0x10, 9, 3),
+ PIN_FIELD_BASE(137, 137, 1, 0x0030, 0x10, 3, 3),
+ PIN_FIELD_BASE(138, 138, 1, 0x0030, 0x10, 9, 3),
+ PIN_FIELD_BASE(139, 139, 2, 0x0020, 0x10, 0, 3),
+ PIN_FIELD_BASE(140, 140, 2, 0x0020, 0x10, 3, 3),
+ PIN_FIELD_BASE(141, 141, 3, 0x0030, 0x10, 3, 3),
+ PIN_FIELD_BASE(142, 142, 3, 0x0030, 0x10, 9, 3),
+ PIN_FIELD_BASE(143, 143, 6, 0x0020, 0x10, 3, 3),
+ PIN_FIELD_BASE(144, 144, 6, 0x0020, 0x10, 12, 3),
+ PIN_FIELD_BASE(145, 145, 6, 0x0020, 0x10, 6, 3),
+ PIN_FIELD_BASE(146, 146, 6, 0x0020, 0x10, 15, 3),
+};
+
+static const struct mtk_pin_field_calc mt8186_pin_rsel_range[] = {
+ PIN_FIELD_BASE(127, 127, 3, 0x00d0, 0x10, 0, 2),
+ PIN_FIELD_BASE(128, 128, 3, 0x00d0, 0x10, 4, 2),
+ PIN_FIELD_BASE(129, 129, 5, 0x00d0, 0x10, 0, 2),
+ PIN_FIELD_BASE(130, 130, 5, 0x00d0, 0x10, 4, 2),
+ PIN_FIELD_BASE(131, 131, 5, 0x00d0, 0x10, 2, 2),
+ PIN_FIELD_BASE(132, 132, 5, 0x00d0, 0x10, 6, 2),
+ PIN_FIELD_BASE(133, 133, 1, 0x00e0, 0x10, 0, 2),
+ PIN_FIELD_BASE(134, 134, 1, 0x00e0, 0x10, 4, 2),
+ PIN_FIELD_BASE(135, 135, 6, 0x0070, 0x10, 0, 2),
+ PIN_FIELD_BASE(136, 136, 6, 0x0070, 0x10, 6, 2),
+ PIN_FIELD_BASE(137, 137, 1, 0x00e0, 0x10, 2, 2),
+ PIN_FIELD_BASE(138, 138, 1, 0x00e0, 0x10, 6, 2),
+ PIN_FIELD_BASE(139, 139, 2, 0x0080, 0x10, 0, 2),
+ PIN_FIELD_BASE(140, 140, 2, 0x0080, 0x10, 2, 2),
+ PIN_FIELD_BASE(141, 141, 3, 0x00d0, 0x10, 2, 2),
+ PIN_FIELD_BASE(142, 142, 3, 0x00d0, 0x10, 6, 2),
+ PIN_FIELD_BASE(143, 143, 6, 0x0070, 0x10, 2, 2),
+ PIN_FIELD_BASE(144, 144, 6, 0x0070, 0x10, 8, 2),
+ PIN_FIELD_BASE(145, 145, 6, 0x0070, 0x10, 4, 2),
+ PIN_FIELD_BASE(146, 146, 6, 0x0070, 0x10, 10, 2),
+};
+
+static const struct mtk_pin_rsel mt8186_pin_rsel_val_range[] = {
+ PIN_RSEL(127, 128, 0x0, 75000, 75000),
+ PIN_RSEL(127, 128, 0x1, 10000, 5000),
+ PIN_RSEL(127, 128, 0x2, 5000, 75000),
+ PIN_RSEL(127, 128, 0x3, 4000, 5000),
+ PIN_RSEL(127, 128, 0x4, 3000, 75000),
+ PIN_RSEL(127, 128, 0x5, 2000, 5000),
+ PIN_RSEL(127, 128, 0x6, 1500, 75000),
+ PIN_RSEL(127, 128, 0x7, 1000, 5000),
+ PIN_RSEL(129, 130, 0x0, 75000, 75000),
+ PIN_RSEL(129, 130, 0x1, 10000, 5000),
+ PIN_RSEL(129, 130, 0x2, 5000, 75000),
+ PIN_RSEL(129, 130, 0x3, 4000, 5000),
+ PIN_RSEL(129, 130, 0x4, 3000, 75000),
+ PIN_RSEL(129, 130, 0x5, 2000, 5000),
+ PIN_RSEL(129, 130, 0x6, 1500, 75000),
+ PIN_RSEL(129, 130, 0x7, 1000, 5000),
+ PIN_RSEL(131, 132, 0x0, 75000, 75000),
+ PIN_RSEL(131, 132, 0x1, 10000, 5000),
+ PIN_RSEL(131, 132, 0x2, 5000, 75000),
+ PIN_RSEL(131, 132, 0x3, 4000, 5000),
+ PIN_RSEL(131, 132, 0x4, 3000, 75000),
+ PIN_RSEL(131, 132, 0x5, 2000, 5000),
+ PIN_RSEL(131, 132, 0x6, 1500, 75000),
+ PIN_RSEL(131, 132, 0x7, 1000, 5000),
+ PIN_RSEL(133, 134, 0x0, 75000, 75000),
+ PIN_RSEL(133, 134, 0x1, 10000, 5000),
+ PIN_RSEL(133, 134, 0x2, 5000, 75000),
+ PIN_RSEL(133, 134, 0x3, 4000, 5000),
+ PIN_RSEL(133, 134, 0x4, 3000, 75000),
+ PIN_RSEL(133, 134, 0x5, 2000, 5000),
+ PIN_RSEL(133, 134, 0x6, 1500, 75000),
+ PIN_RSEL(133, 134, 0x7, 1000, 5000),
+ PIN_RSEL(135, 136, 0x0, 75000, 75000),
+ PIN_RSEL(135, 136, 0x1, 10000, 5000),
+ PIN_RSEL(135, 136, 0x2, 5000, 75000),
+ PIN_RSEL(135, 136, 0x3, 4000, 5000),
+ PIN_RSEL(135, 136, 0x4, 3000, 75000),
+ PIN_RSEL(135, 136, 0x5, 2000, 5000),
+ PIN_RSEL(135, 136, 0x6, 1500, 75000),
+ PIN_RSEL(135, 136, 0x7, 1000, 5000),
+ PIN_RSEL(137, 138, 0x0, 75000, 75000),
+ PIN_RSEL(137, 138, 0x1, 10000, 5000),
+ PIN_RSEL(137, 138, 0x2, 5000, 75000),
+ PIN_RSEL(137, 138, 0x3, 4000, 5000),
+ PIN_RSEL(137, 138, 0x4, 3000, 75000),
+ PIN_RSEL(137, 138, 0x5, 2000, 5000),
+ PIN_RSEL(137, 138, 0x6, 1500, 75000),
+ PIN_RSEL(137, 138, 0x7, 1000, 5000),
+ PIN_RSEL(139, 140, 0x0, 75000, 75000),
+ PIN_RSEL(139, 140, 0x1, 10000, 5000),
+ PIN_RSEL(139, 140, 0x2, 5000, 75000),
+ PIN_RSEL(139, 140, 0x3, 4000, 5000),
+ PIN_RSEL(139, 140, 0x4, 3000, 75000),
+ PIN_RSEL(139, 140, 0x5, 2000, 5000),
+ PIN_RSEL(139, 140, 0x6, 1500, 75000),
+ PIN_RSEL(139, 140, 0x7, 1000, 5000),
+ PIN_RSEL(141, 142, 0x0, 75000, 75000),
+ PIN_RSEL(141, 142, 0x1, 10000, 5000),
+ PIN_RSEL(141, 142, 0x2, 5000, 75000),
+ PIN_RSEL(141, 142, 0x3, 4000, 5000),
+ PIN_RSEL(141, 142, 0x4, 3000, 75000),
+ PIN_RSEL(141, 142, 0x5, 2000, 5000),
+ PIN_RSEL(141, 142, 0x6, 1500, 75000),
+ PIN_RSEL(141, 142, 0x7, 1000, 5000),
+ PIN_RSEL(143, 144, 0x0, 75000, 75000),
+ PIN_RSEL(143, 144, 0x1, 10000, 5000),
+ PIN_RSEL(143, 144, 0x2, 5000, 75000),
+ PIN_RSEL(143, 144, 0x3, 4000, 5000),
+ PIN_RSEL(143, 144, 0x4, 3000, 75000),
+ PIN_RSEL(143, 144, 0x5, 2000, 5000),
+ PIN_RSEL(143, 144, 0x6, 1500, 75000),
+ PIN_RSEL(143, 144, 0x7, 1000, 5000),
+ PIN_RSEL(145, 146, 0x0, 75000, 75000),
+ PIN_RSEL(145, 146, 0x1, 10000, 5000),
+ PIN_RSEL(145, 146, 0x2, 5000, 75000),
+ PIN_RSEL(145, 146, 0x3, 4000, 5000),
+ PIN_RSEL(145, 146, 0x4, 3000, 75000),
+ PIN_RSEL(145, 146, 0x5, 2000, 5000),
+ PIN_RSEL(145, 146, 0x6, 1500, 75000),
+ PIN_RSEL(145, 146, 0x7, 1000, 5000),
+};
+
+static const unsigned int mt8186_pull_type[] = {
+ MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/
+ MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/
+ MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/
+ MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/
+ MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/
+ MTK_PULL_PU_PD_TYPE,/*10*/ MTK_PULL_PU_PD_TYPE,/*11*/
+ MTK_PULL_PU_PD_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,/*13*/
+ MTK_PULL_PU_PD_TYPE,/*14*/ MTK_PULL_PU_PD_TYPE,/*15*/
+ MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/
+ MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/
+ MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/
+ MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/
+ MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/
+ MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/
+ MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/
+ MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/
+ MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/
+ MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/
+ MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/
+ MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/
+ MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
+ MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
+ MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
+ MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
+ MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
+ MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
+ MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
+ MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
+ MTK_PULL_PU_PD_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/
+ MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/
+ MTK_PULL_PU_PD_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/
+ MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/
+ MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/
+ MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PUPD_R1R0_TYPE,/*71*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PUPD_R1R0_TYPE,/*75*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*76*/ MTK_PULL_PUPD_R1R0_TYPE,/*77*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*78*/ MTK_PULL_PUPD_R1R0_TYPE,/*79*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*84*/ MTK_PULL_PUPD_R1R0_TYPE,/*85*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*86*/ MTK_PULL_PUPD_R1R0_TYPE,/*87*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*88*/ MTK_PULL_PUPD_R1R0_TYPE,/*89*/
+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
+ MTK_PULL_PU_PD_TYPE,/*100*/ MTK_PULL_PU_PD_TYPE,/*101*/
+ MTK_PULL_PU_PD_TYPE,/*102*/ MTK_PULL_PU_PD_TYPE,/*103*/
+ MTK_PULL_PU_PD_TYPE,/*104*/ MTK_PULL_PU_PD_TYPE,/*105*/
+ MTK_PULL_PU_PD_TYPE,/*106*/ MTK_PULL_PU_PD_TYPE,/*107*/
+ MTK_PULL_PU_PD_TYPE,/*108*/ MTK_PULL_PU_PD_TYPE,/*109*/
+ MTK_PULL_PU_PD_TYPE,/*110*/ MTK_PULL_PU_PD_TYPE,/*111*/
+ MTK_PULL_PU_PD_TYPE,/*112*/ MTK_PULL_PU_PD_TYPE,/*113*/
+ MTK_PULL_PU_PD_TYPE,/*114*/ MTK_PULL_PU_PD_TYPE,/*115*/
+ MTK_PULL_PU_PD_TYPE,/*116*/ MTK_PULL_PU_PD_TYPE,/*117*/
+ MTK_PULL_PU_PD_TYPE,/*118*/ MTK_PULL_PU_PD_TYPE,/*119*/
+ MTK_PULL_PU_PD_TYPE,/*120*/ MTK_PULL_PU_PD_TYPE,/*121*/
+ MTK_PULL_PU_PD_TYPE,/*122*/ MTK_PULL_PU_PD_TYPE,/*123*/
+ MTK_PULL_PU_PD_TYPE,/*124*/ MTK_PULL_PU_PD_TYPE,/*125*/
+ MTK_PULL_PU_PD_TYPE,/*126*/ MTK_PULL_PU_PD_RSEL_TYPE,/*127*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*128*/ MTK_PULL_PU_PD_RSEL_TYPE,/*129*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*130*/ MTK_PULL_PU_PD_RSEL_TYPE,/*131*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*132*/ MTK_PULL_PU_PD_RSEL_TYPE,/*133*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*134*/ MTK_PULL_PU_PD_RSEL_TYPE,/*135*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*136*/ MTK_PULL_PU_PD_RSEL_TYPE,/*137*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*138*/ MTK_PULL_PU_PD_RSEL_TYPE,/*139*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*140*/ MTK_PULL_PU_PD_RSEL_TYPE,/*141*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*142*/ MTK_PULL_PU_PD_RSEL_TYPE,/*143*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*144*/ MTK_PULL_PU_PD_RSEL_TYPE,/*145*/
+ MTK_PULL_PU_PD_RSEL_TYPE,/*146*/ MTK_PULL_PU_PD_TYPE,/*147*/
+ MTK_PULL_PU_PD_TYPE,/*148*/ MTK_PULL_PU_PD_TYPE,/*149*/
+ MTK_PULL_PU_PD_TYPE,/*150*/ MTK_PULL_PU_PD_TYPE,/*151*/
+ MTK_PULL_PU_PD_TYPE,/*152*/ MTK_PULL_PU_PD_TYPE,/*153*/
+ MTK_PULL_PU_PD_TYPE,/*154*/ MTK_PULL_PU_PD_TYPE,/*155*/
+ MTK_PULL_PU_PD_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/
+ MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/
+ MTK_PULL_PU_PD_TYPE,/*160*/ MTK_PULL_PU_PD_TYPE,/*161*/
+ MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/
+ MTK_PULL_PU_PD_TYPE,/*164*/ MTK_PULL_PU_PD_TYPE,/*165*/
+ MTK_PULL_PU_PD_TYPE,/*166*/ MTK_PULL_PU_PD_TYPE,/*167*/
+ MTK_PULL_PU_PD_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/
+ MTK_PULL_PU_PD_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/
+ MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/
+ MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/
+ MTK_PULL_PU_PD_TYPE,/*176*/ MTK_PULL_PU_PD_TYPE,/*177*/
+ MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/
+ MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/
+ MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PU_PD_TYPE,/*183*/
+ MTK_PULL_PU_PD_TYPE,/*184*/
+};
+
+static const struct mtk_pin_reg_calc mt8186_reg_cals[PINCTRL_PIN_REG_MAX] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8186_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8186_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8186_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8186_pin_do_range),
+ [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8186_pin_dir_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8186_pin_smt_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8186_pin_ies_range),
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8186_pin_pu_range),
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8186_pin_pd_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8186_pin_drv_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8186_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8186_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8186_pin_r1_range),
+ [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8186_pin_drv_adv_range),
+ [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8186_pin_rsel_range),
+
+};
+
+static const char * const mt8186_pinctrl_register_base_names[] = {
+ "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", "iocfg_bl",
+ "iocfg_rb", "iocfg_rt",
+};
+
+static const struct mtk_eint_hw mt8186_eint_hw = {
+ .port_mask = 0xf,
+ .ports = 7,
+ .ap_num = 217,
+ .db_cnt = 32,
+};
+
+static const struct mtk_pin_soc mt8186_data = {
+ .reg_cal = mt8186_reg_cals,
+ .pins = mtk_pins_mt8186,
+ .npins = ARRAY_SIZE(mtk_pins_mt8186),
+ .ngrps = ARRAY_SIZE(mtk_pins_mt8186),
+ .nfuncs = 8,
+ .gpio_m = 0,
+ .eint_hw = &mt8186_eint_hw,
+ .base_names = mt8186_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt8186_pinctrl_register_base_names),
+ .pull_type = mt8186_pull_type,
+ .pin_rsel = mt8186_pin_rsel_val_range,
+ .npin_rsel = ARRAY_SIZE(mt8186_pin_rsel_val_range),
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_drive_get = mtk_pinconf_adv_drive_get_raw,
+ .adv_drive_set = mtk_pinconf_adv_drive_set_raw,
+};
+
+static const struct of_device_id mt8186_pinctrl_of_match[] = {
+ { .compatible = "mediatek,mt8186-pinctrl", },
+ { }
+};
+static int mt8186_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_paris_pinctrl_probe(pdev, &mt8186_data);
+}
+
+static struct platform_driver mt8186_pinctrl_driver = {
+ .driver = {
+ .name = "mt8186-pinctrl",
+ .of_match_table = mt8186_pinctrl_of_match,
+ .pm = &mtk_paris_pinctrl_pm_ops,
+ },
+ .probe = mt8186_pinctrl_probe,
+};
+
+static int __init mt8186_pinctrl_init(void)
+{
+ return platform_driver_register(&mt8186_pinctrl_driver);
+}
+
+arch_initcall(mt8186_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
new file mode 100644
index 000000000000..464651f7b44b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
@@ -0,0 +1,2186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ *
+ * Author: Guodong Liu <guodong.liu@mediatek.com>
+ *
+ */
+
+#ifndef __PINCTRL_MTK_MT8186_H
+#define __PINCTRL_MTK_MT8186_H
+
+#include "pinctrl-paris.h"
+
+static const struct mtk_pin_desc mtk_pins_mt8186[] = {
+ MTK_PIN(
+ 0, "GPIO0",
+ MTK_EINT_FUNCTION(0, 0),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "I2S0_MCK"),
+ MTK_FUNCTION(2, "SPI0_CLK_B"),
+ MTK_FUNCTION(3, "I2S2_MCK"),
+ MTK_FUNCTION(4, "CMFLASH0"),
+ MTK_FUNCTION(5, "SCP_SPI0_CK"),
+ MTK_FUNCTION(6, "TP_GPIO0_AO"),
+ MTK_FUNCTION(7, "dbg_mon_a0")
+ ),
+
+ MTK_PIN(
+ 1, "GPIO1",
+ MTK_EINT_FUNCTION(0, 1),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(2, "SPI0_CSB_B"),
+ MTK_FUNCTION(3, "I2S2_BCK"),
+ MTK_FUNCTION(4, "CMFLASH1"),
+ MTK_FUNCTION(5, "SCP_SPI0_CS"),
+ MTK_FUNCTION(6, "TP_GPIO1_AO")
+ ),
+
+ MTK_PIN(
+ 2, "GPIO2",
+ MTK_EINT_FUNCTION(0, 2),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(2, "SPI0_MO_B"),
+ MTK_FUNCTION(3, "I2S2_LRCK"),
+ MTK_FUNCTION(4, "CMFLASH2"),
+ MTK_FUNCTION(5, "SCP_SPI0_MO"),
+ MTK_FUNCTION(6, "TP_GPIO2_AO")
+ ),
+
+ MTK_PIN(
+ 3, "GPIO3",
+ MTK_EINT_FUNCTION(0, 3),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "SPI0_MI_B"),
+ MTK_FUNCTION(3, "I2S2_DI"),
+ MTK_FUNCTION(4, "SRCLKENAI1"),
+ MTK_FUNCTION(5, "SCP_SPI0_MI"),
+ MTK_FUNCTION(6, "TP_GPIO3_AO")
+ ),
+
+ MTK_PIN(
+ 4, "GPIO4",
+ MTK_EINT_FUNCTION(0, 4),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "I2S3_DO"),
+ MTK_FUNCTION(3, "I2S1_DO"),
+ MTK_FUNCTION(6, "TP_GPIO4_AO")
+ ),
+
+ MTK_PIN(
+ 5, "GPIO5",
+ MTK_EINT_FUNCTION(0, 5),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(6, "TP_GPIO5_AO")
+ ),
+
+ MTK_PIN(
+ 6, "GPIO6",
+ MTK_EINT_FUNCTION(0, 6),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "I2S3_MCK"),
+ MTK_FUNCTION(2, "SPI1_CLK_B"),
+ MTK_FUNCTION(3, "I2S1_MCK"),
+ MTK_FUNCTION(4, "DPI_DATA22"),
+ MTK_FUNCTION(6, "TP_GPIO6_AO")
+ ),
+
+ MTK_PIN(
+ 7, "GPIO7",
+ MTK_EINT_FUNCTION(0, 7),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "I2S3_BCK"),
+ MTK_FUNCTION(2, "SPI1_CSB_B"),
+ MTK_FUNCTION(3, "I2S1_BCK"),
+ MTK_FUNCTION(4, "DPI_DATA23"),
+ MTK_FUNCTION(6, "TP_GPIO7_AO")
+ ),
+
+ MTK_PIN(
+ 8, "GPIO8",
+ MTK_EINT_FUNCTION(0, 8),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "I2S3_LRCK"),
+ MTK_FUNCTION(2, "SPI1_MO_B"),
+ MTK_FUNCTION(3, "I2S1_LRCK"),
+ MTK_FUNCTION(4, "CONN_UART0_RXD"),
+ MTK_FUNCTION(5, "SSPM_URXD_AO"),
+ MTK_FUNCTION(6, "ADSP_UART_RX"),
+ MTK_FUNCTION(7, "CONN_MCU_DBGACK_N")
+ ),
+
+ MTK_PIN(
+ 9, "GPIO9",
+ MTK_EINT_FUNCTION(0, 9),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "I2S3_DO"),
+ MTK_FUNCTION(2, "SPI1_MI_B"),
+ MTK_FUNCTION(3, "I2S1_DO"),
+ MTK_FUNCTION(4, "CONN_UART0_TXD"),
+ MTK_FUNCTION(5, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(6, "ADSP_UART_TX"),
+ MTK_FUNCTION(7, "CONN_MCU_DBGI_N")
+ ),
+
+ MTK_PIN(
+ 10, "GPIO10",
+ MTK_EINT_FUNCTION(0, 10),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "I2S0_MCK"),
+ MTK_FUNCTION(2, "SPI4_CLK_A"),
+ MTK_FUNCTION(3, "I2S2_MCK"),
+ MTK_FUNCTION(4, "SPM_JTAG_TDI"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDI"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TDI"),
+ MTK_FUNCTION(7, "CONN_MCU_TDI")
+ ),
+
+ MTK_PIN(
+ 11, "GPIO11",
+ MTK_EINT_FUNCTION(0, 11),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(2, "SPI4_CSB_A"),
+ MTK_FUNCTION(3, "I2S2_BCK"),
+ MTK_FUNCTION(4, "SPM_JTAG_TRSTN"),
+ MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TRSTN"),
+ MTK_FUNCTION(7, "CONN_MCU_TRST_B")
+ ),
+
+ MTK_PIN(
+ 12, "GPIO12",
+ MTK_EINT_FUNCTION(0, 12),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(2, "SPI4_MO_A"),
+ MTK_FUNCTION(3, "I2S2_LRCK"),
+ MTK_FUNCTION(4, "SPM_JTAG_TCK"),
+ MTK_FUNCTION(5, "SCP_JTAG_TCK"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TCK"),
+ MTK_FUNCTION(7, "CONN_MCU_TCK")
+ ),
+
+ MTK_PIN(
+ 13, "GPIO13",
+ MTK_EINT_FUNCTION(0, 13),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "SPI4_MI_A"),
+ MTK_FUNCTION(3, "I2S2_DI"),
+ MTK_FUNCTION(4, "SPM_JTAG_TDO"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDO"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TDO"),
+ MTK_FUNCTION(7, "CONN_MCU_TDO")
+ ),
+
+ MTK_PIN(
+ 14, "GPIO14",
+ MTK_EINT_FUNCTION(0, 14),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "SPM_JTAG_TMS"),
+ MTK_FUNCTION(5, "SCP_JTAG_TMS"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TMS"),
+ MTK_FUNCTION(7, "CONN_MCU_TMS")
+ ),
+
+ MTK_PIN(
+ 15, "GPIO15",
+ MTK_EINT_FUNCTION(0, 15),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(2, "SRCLKENAI1"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "PWM0")
+ ),
+
+ MTK_PIN(
+ 16, "GPIO16",
+ MTK_EINT_FUNCTION(0, 16),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "CONN_WIFI_TXD"),
+ MTK_FUNCTION(2, "SRCLKENAI0"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "PWM1")
+ ),
+
+ MTK_PIN(
+ 17, "GPIO17",
+ MTK_EINT_FUNCTION(0, 17),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(7, "dbg_mon_a32")
+ ),
+
+ MTK_PIN(
+ 18, "GPIO18",
+ MTK_EINT_FUNCTION(0, 18),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(2, "CMVREF0"),
+ MTK_FUNCTION(6, "SPI2_CLK_B"),
+ MTK_FUNCTION(7, "dbg_mon_a26")
+ ),
+
+ MTK_PIN(
+ 19, "GPIO19",
+ MTK_EINT_FUNCTION(0, 19),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(2, "CMVREF1"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "SPI2_CSB_B"),
+ MTK_FUNCTION(7, "dbg_mon_a2")
+ ),
+
+ MTK_PIN(
+ 20, "GPIO20",
+ MTK_EINT_FUNCTION(0, 20),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(2, "CMVREF2"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "SPI2_MO_B"),
+ MTK_FUNCTION(7, "dbg_mon_a3")
+ ),
+
+ MTK_PIN(
+ 21, "GPIO21",
+ MTK_EINT_FUNCTION(0, 21),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "I2S0_MCK"),
+ MTK_FUNCTION(2, "I2S1_MCK"),
+ MTK_FUNCTION(3, "I2S3_MCK"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(6, "SPI2_MI_B"),
+ MTK_FUNCTION(7, "dbg_mon_a4")
+ ),
+
+ MTK_PIN(
+ 22, "GPIO22",
+ MTK_EINT_FUNCTION(0, 22),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(2, "I2S1_BCK"),
+ MTK_FUNCTION(3, "I2S3_BCK"),
+ MTK_FUNCTION(4, "TDM_RX_LRCK"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(7, "dbg_mon_a5")
+ ),
+
+ MTK_PIN(
+ 23, "GPIO23",
+ MTK_EINT_FUNCTION(0, 23),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(2, "I2S1_LRCK"),
+ MTK_FUNCTION(3, "I2S3_LRCK"),
+ MTK_FUNCTION(4, "TDM_RX_BCK"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(7, "dbg_mon_a6")
+ ),
+
+ MTK_PIN(
+ 24, "GPIO24",
+ MTK_EINT_FUNCTION(0, 24),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "I2S1_DO"),
+ MTK_FUNCTION(3, "I2S3_DO"),
+ MTK_FUNCTION(4, "TDM_RX_MCK"),
+ MTK_FUNCTION(7, "dbg_mon_a7")
+ ),
+
+ MTK_PIN(
+ 25, "GPIO25",
+ MTK_EINT_FUNCTION(0, 25),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "I2S2_MCK"),
+ MTK_FUNCTION(2, "PCM_CLK"),
+ MTK_FUNCTION(3, "SPI4_CLK_B"),
+ MTK_FUNCTION(4, "TDM_RX_DATA0"),
+ MTK_FUNCTION(7, "dbg_mon_a8")
+ ),
+
+ MTK_PIN(
+ 26, "GPIO26",
+ MTK_EINT_FUNCTION(0, 26),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "I2S2_BCK"),
+ MTK_FUNCTION(2, "PCM_SYNC"),
+ MTK_FUNCTION(3, "SPI4_CSB_B"),
+ MTK_FUNCTION(4, "TDM_RX_DATA1"),
+ MTK_FUNCTION(7, "dbg_mon_a9")
+ ),
+
+ MTK_PIN(
+ 27, "GPIO27",
+ MTK_EINT_FUNCTION(0, 27),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "I2S2_LRCK"),
+ MTK_FUNCTION(2, "PCM_DI"),
+ MTK_FUNCTION(3, "SPI4_MO_B"),
+ MTK_FUNCTION(4, "TDM_RX_DATA2"),
+ MTK_FUNCTION(7, "dbg_mon_a10")
+ ),
+
+ MTK_PIN(
+ 28, "GPIO28",
+ MTK_EINT_FUNCTION(0, 28),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "I2S2_DI"),
+ MTK_FUNCTION(2, "PCM_DO"),
+ MTK_FUNCTION(3, "SPI4_MI_B"),
+ MTK_FUNCTION(4, "TDM_RX_DATA3")
+ ),
+
+ MTK_PIN(
+ 29, "GPIO29",
+ MTK_EINT_FUNCTION(0, 29),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "ANT_SEL0"),
+ MTK_FUNCTION(2, "GPS_L1_ELNA_EN")
+ ),
+
+ MTK_PIN(
+ 30, "GPIO30",
+ MTK_EINT_FUNCTION(0, 30),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "ANT_SEL1")
+ ),
+
+ MTK_PIN(
+ 31, "GPIO31",
+ MTK_EINT_FUNCTION(0, 31),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "ANT_SEL2"),
+ MTK_FUNCTION(2, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(3, "SRCLKENAI1")
+ ),
+
+ MTK_PIN(
+ 32, "GPIO32",
+ MTK_EINT_FUNCTION(0, 32),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0"),
+ MTK_FUNCTION(3, "ADSP_UART_RX"),
+ MTK_FUNCTION(4, "TP_URXD1_AO")
+ ),
+
+ MTK_PIN(
+ 33, "GPIO33",
+ MTK_EINT_FUNCTION(0, 33),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0"),
+ MTK_FUNCTION(3, "ADSP_UART_TX"),
+ MTK_FUNCTION(4, "TP_UTXD1_AO")
+ ),
+
+ MTK_PIN(
+ 34, "GPIO34",
+ MTK_EINT_FUNCTION(0, 34),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "TP_URXD2_AO"),
+ MTK_FUNCTION(3, "SSPM_URXD_AO"),
+ MTK_FUNCTION(4, "ADSP_UART_RX"),
+ MTK_FUNCTION(5, "CONN_UART0_RXD")
+ ),
+
+ MTK_PIN(
+ 35, "GPIO35",
+ MTK_EINT_FUNCTION(0, 35),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "TP_UTXD2_AO"),
+ MTK_FUNCTION(3, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(4, "ADSP_UART_TX"),
+ MTK_FUNCTION(5, "CONN_UART0_TXD"),
+ MTK_FUNCTION(6, "CONN_WIFI_TXD")
+ ),
+
+ MTK_PIN(
+ 36, "GPIO36",
+ MTK_EINT_FUNCTION(0, 36),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "SPI0_CLK_A"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(4, "SCP_SPI0_CK"),
+ MTK_FUNCTION(5, "SPINOR_CK"),
+ MTK_FUNCTION(7, "dbg_mon_a11")
+ ),
+
+ MTK_PIN(
+ 37, "GPIO37",
+ MTK_EINT_FUNCTION(0, 37),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "SPI0_CSB_A"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "SCP_SPI0_CS"),
+ MTK_FUNCTION(5, "SPINOR_CS"),
+ MTK_FUNCTION(7, "dbg_mon_a12")
+ ),
+
+ MTK_PIN(
+ 38, "GPIO38",
+ MTK_EINT_FUNCTION(0, 38),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "SPI0_MO_A"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(4, "SCP_SPI0_MO"),
+ MTK_FUNCTION(5, "SPINOR_IO0"),
+ MTK_FUNCTION(7, "dbg_mon_a13")
+ ),
+
+ MTK_PIN(
+ 39, "GPIO39",
+ MTK_EINT_FUNCTION(0, 39),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "SPI0_MI_A"),
+ MTK_FUNCTION(2, "CLKM3"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(4, "SCP_SPI0_MI"),
+ MTK_FUNCTION(5, "SPINOR_IO1"),
+ MTK_FUNCTION(7, "dbg_mon_a14")
+ ),
+
+ MTK_PIN(
+ 40, "GPIO40",
+ MTK_EINT_FUNCTION(0, 40),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "SPI1_CLK_A"),
+ MTK_FUNCTION(2, "SCP_SPI1_CK"),
+ MTK_FUNCTION(4, "UCTS0"),
+ MTK_FUNCTION(5, "SPINOR_IO2"),
+ MTK_FUNCTION(6, "TP_UCTS1_AO"),
+ MTK_FUNCTION(7, "dbg_mon_a15")
+ ),
+
+ MTK_PIN(
+ 41, "GPIO41",
+ MTK_EINT_FUNCTION(0, 41),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "SPI1_CSB_A"),
+ MTK_FUNCTION(2, "SCP_SPI1_CS"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "URTS0"),
+ MTK_FUNCTION(5, "SPINOR_IO3"),
+ MTK_FUNCTION(6, "TP_URTS1_AO"),
+ MTK_FUNCTION(7, "dbg_mon_a16")
+ ),
+
+ MTK_PIN(
+ 42, "GPIO42",
+ MTK_EINT_FUNCTION(0, 42),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "SPI1_MO_A"),
+ MTK_FUNCTION(2, "SCP_SPI1_MO"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(4, "UCTS1"),
+ MTK_FUNCTION(6, "TP_UCTS2_AO"),
+ MTK_FUNCTION(7, "dbg_mon_a17")
+ ),
+
+ MTK_PIN(
+ 43, "GPIO43",
+ MTK_EINT_FUNCTION(0, 43),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "SPI1_MI_A"),
+ MTK_FUNCTION(2, "SCP_SPI1_MI"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(4, "URTS1"),
+ MTK_FUNCTION(6, "TP_URTS2_AO"),
+ MTK_FUNCTION(7, "dbg_mon_a18")
+ ),
+
+ MTK_PIN(
+ 44, "GPIO44",
+ MTK_EINT_FUNCTION(0, 44),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "SPI2_CLK_A"),
+ MTK_FUNCTION(2, "SCP_SPI0_CK"),
+ MTK_FUNCTION(7, "dbg_mon_a19")
+ ),
+
+ MTK_PIN(
+ 45, "GPIO45",
+ MTK_EINT_FUNCTION(0, 45),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "SPI2_CSB_A"),
+ MTK_FUNCTION(2, "SCP_SPI0_CS"),
+ MTK_FUNCTION(7, "dbg_mon_a20")
+ ),
+
+ MTK_PIN(
+ 46, "GPIO46",
+ MTK_EINT_FUNCTION(0, 46),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "SPI2_MO_A"),
+ MTK_FUNCTION(2, "SCP_SPI0_MO"),
+ MTK_FUNCTION(7, "dbg_mon_a21")
+ ),
+
+ MTK_PIN(
+ 47, "GPIO47",
+ MTK_EINT_FUNCTION(0, 47),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "SPI2_MI_A"),
+ MTK_FUNCTION(2, "SCP_SPI0_MI"),
+ MTK_FUNCTION(7, "dbg_mon_a22")
+ ),
+
+ MTK_PIN(
+ 48, "GPIO48",
+ MTK_EINT_FUNCTION(0, 48),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "SPI3_CLK"),
+ MTK_FUNCTION(2, "TP_URXD1_AO"),
+ MTK_FUNCTION(3, "TP_URXD2_AO"),
+ MTK_FUNCTION(4, "URXD1"),
+ MTK_FUNCTION(5, "I2S2_MCK"),
+ MTK_FUNCTION(6, "SCP_SPI0_CK")
+ ),
+
+ MTK_PIN(
+ 49, "GPIO49",
+ MTK_EINT_FUNCTION(0, 49),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "SPI3_CSB"),
+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
+ MTK_FUNCTION(3, "TP_UTXD2_AO"),
+ MTK_FUNCTION(4, "UTXD1"),
+ MTK_FUNCTION(5, "I2S2_BCK"),
+ MTK_FUNCTION(6, "SCP_SPI0_CS")
+ ),
+
+ MTK_PIN(
+ 50, "GPIO50",
+ MTK_EINT_FUNCTION(0, 50),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "SPI3_MO"),
+ MTK_FUNCTION(5, "I2S2_LRCK"),
+ MTK_FUNCTION(6, "SCP_SPI0_MO")
+ ),
+
+ MTK_PIN(
+ 51, "GPIO51",
+ MTK_EINT_FUNCTION(0, 51),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "SPI3_MI"),
+ MTK_FUNCTION(5, "I2S2_DI"),
+ MTK_FUNCTION(6, "SCP_SPI0_MI")
+ ),
+
+ MTK_PIN(
+ 52, "GPIO52",
+ MTK_EINT_FUNCTION(0, 52),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "SPI5_CLK"),
+ MTK_FUNCTION(2, "I2S2_MCK"),
+ MTK_FUNCTION(3, "I2S1_MCK"),
+ MTK_FUNCTION(4, "SCP_SPI1_CK"),
+ MTK_FUNCTION(5, "LVTS_26M"),
+ MTK_FUNCTION(6, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "dbg_mon_b30")
+ ),
+
+ MTK_PIN(
+ 53, "GPIO53",
+ MTK_EINT_FUNCTION(0, 53),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "SPI5_CSB"),
+ MTK_FUNCTION(2, "I2S2_BCK"),
+ MTK_FUNCTION(3, "I2S1_BCK"),
+ MTK_FUNCTION(4, "SCP_SPI1_CS"),
+ MTK_FUNCTION(5, "LVTS_FOUT"),
+ MTK_FUNCTION(6, "DFD_TDI"),
+ MTK_FUNCTION(7, "dbg_mon_b31")
+ ),
+
+ MTK_PIN(
+ 54, "GPIO54",
+ MTK_EINT_FUNCTION(0, 54),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "SPI5_MO"),
+ MTK_FUNCTION(2, "I2S2_LRCK"),
+ MTK_FUNCTION(3, "I2S1_LRCK"),
+ MTK_FUNCTION(4, "SCP_SPI1_MO"),
+ MTK_FUNCTION(5, "LVTS_SCK"),
+ MTK_FUNCTION(6, "DFD_TDO"),
+ MTK_FUNCTION(7, "dbg_mon_a1")
+ ),
+
+ MTK_PIN(
+ 55, "GPIO55",
+ MTK_EINT_FUNCTION(0, 55),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "SPI5_MI"),
+ MTK_FUNCTION(2, "I2S2_DI"),
+ MTK_FUNCTION(3, "I2S1_DO"),
+ MTK_FUNCTION(4, "SCP_SPI1_MI"),
+ MTK_FUNCTION(5, "LVTS_SDO"),
+ MTK_FUNCTION(6, "DFD_TMS"),
+ MTK_FUNCTION(7, "dbg_mon_b32")
+ ),
+
+ MTK_PIN(
+ 56, "GPIO56",
+ MTK_EINT_FUNCTION(0, 56),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "I2S1_DO"),
+ MTK_FUNCTION(2, "I2S3_DO"),
+ MTK_FUNCTION(7, "dbg_mon_a23")
+ ),
+
+ MTK_PIN(
+ 57, "GPIO57",
+ MTK_EINT_FUNCTION(0, 57),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "I2S1_BCK"),
+ MTK_FUNCTION(2, "I2S3_BCK"),
+ MTK_FUNCTION(7, "dbg_mon_a24")
+ ),
+
+ MTK_PIN(
+ 58, "GPIO58",
+ MTK_EINT_FUNCTION(0, 58),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "I2S1_LRCK"),
+ MTK_FUNCTION(2, "I2S3_LRCK"),
+ MTK_FUNCTION(7, "dbg_mon_a25")
+ ),
+
+ MTK_PIN(
+ 59, "GPIO59",
+ MTK_EINT_FUNCTION(0, 59),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "I2S1_MCK"),
+ MTK_FUNCTION(2, "I2S3_MCK"),
+ MTK_FUNCTION(7, "dbg_mon_a27")
+ ),
+
+ MTK_PIN(
+ 60, "GPIO60",
+ MTK_EINT_FUNCTION(0, 60),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "TDM_RX_LRCK"),
+ MTK_FUNCTION(2, "ANT_SEL3"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N")
+ ),
+
+ MTK_PIN(
+ 61, "GPIO61",
+ MTK_EINT_FUNCTION(0, 61),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "TDM_RX_BCK"),
+ MTK_FUNCTION(2, "ANT_SEL4"),
+ MTK_FUNCTION(4, "SPINOR_CK"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGI_N")
+ ),
+
+ MTK_PIN(
+ 62, "GPIO62",
+ MTK_EINT_FUNCTION(0, 62),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "TDM_RX_MCK"),
+ MTK_FUNCTION(2, "ANT_SEL5"),
+ MTK_FUNCTION(4, "SPINOR_CS"),
+ MTK_FUNCTION(5, "CONN_MCU_TDI")
+ ),
+
+ MTK_PIN(
+ 63, "GPIO63",
+ MTK_EINT_FUNCTION(0, 63),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "TDM_RX_DATA0"),
+ MTK_FUNCTION(2, "ANT_SEL6"),
+ MTK_FUNCTION(4, "SPINOR_IO0"),
+ MTK_FUNCTION(5, "CONN_MCU_TRST_B")
+ ),
+
+ MTK_PIN(
+ 64, "GPIO64",
+ MTK_EINT_FUNCTION(0, 64),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "TDM_RX_DATA1"),
+ MTK_FUNCTION(2, "ANT_SEL7"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "SPINOR_IO1"),
+ MTK_FUNCTION(5, "CONN_MCU_TCK")
+ ),
+
+ MTK_PIN(
+ 65, "GPIO65",
+ MTK_EINT_FUNCTION(0, 65),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "TDM_RX_DATA2"),
+ MTK_FUNCTION(2, "UCTS0"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(4, "SPINOR_IO2"),
+ MTK_FUNCTION(5, "CONN_MCU_TDO"),
+ MTK_FUNCTION(6, "TP_UCTS1_AO"),
+ MTK_FUNCTION(7, "TP_UCTS2_AO")
+ ),
+
+ MTK_PIN(
+ 66, "GPIO66",
+ MTK_EINT_FUNCTION(0, 66),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "TDM_RX_DATA3"),
+ MTK_FUNCTION(2, "URTS0"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(4, "SPINOR_IO3"),
+ MTK_FUNCTION(5, "CONN_MCU_TMS"),
+ MTK_FUNCTION(6, "TP_URTS1_AO"),
+ MTK_FUNCTION(7, "TP_URTS2_AO")
+ ),
+
+ MTK_PIN(
+ 67, "GPIO67",
+ MTK_EINT_FUNCTION(0, 67),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "MSDC0_DSL")
+ ),
+
+ MTK_PIN(
+ 68, "GPIO68",
+ MTK_EINT_FUNCTION(0, 68),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "MSDC0_CLK")
+ ),
+
+ MTK_PIN(
+ 69, "GPIO69",
+ MTK_EINT_FUNCTION(0, 69),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "MSDC0_CMD")
+ ),
+
+ MTK_PIN(
+ 70, "GPIO70",
+ MTK_EINT_FUNCTION(0, 70),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "MSDC0_RSTB")
+ ),
+
+ MTK_PIN(
+ 71, "GPIO71",
+ MTK_EINT_FUNCTION(0, 71),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "MSDC0_DAT0")
+ ),
+
+ MTK_PIN(
+ 72, "GPIO72",
+ MTK_EINT_FUNCTION(0, 72),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "MSDC0_DAT1")
+ ),
+
+ MTK_PIN(
+ 73, "GPIO73",
+ MTK_EINT_FUNCTION(0, 73),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "MSDC0_DAT2")
+ ),
+
+ MTK_PIN(
+ 74, "GPIO74",
+ MTK_EINT_FUNCTION(0, 74),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "MSDC0_DAT3")
+ ),
+
+ MTK_PIN(
+ 75, "GPIO75",
+ MTK_EINT_FUNCTION(0, 75),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "MSDC0_DAT4")
+ ),
+
+ MTK_PIN(
+ 76, "GPIO76",
+ MTK_EINT_FUNCTION(0, 76),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "MSDC0_DAT5")
+ ),
+
+ MTK_PIN(
+ 77, "GPIO77",
+ MTK_EINT_FUNCTION(0, 77),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "MSDC0_DAT6")
+ ),
+
+ MTK_PIN(
+ 78, "GPIO78",
+ MTK_EINT_FUNCTION(0, 78),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "MSDC0_DAT7")
+ ),
+
+ MTK_PIN(
+ 79, "GPIO79",
+ MTK_EINT_FUNCTION(0, 79),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "KPCOL0")
+ ),
+
+ MTK_PIN(
+ 80, "GPIO80",
+ MTK_EINT_FUNCTION(0, 80),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "KPCOL1"),
+ MTK_FUNCTION(2, "GPS_L1_ELNA_EN"),
+ MTK_FUNCTION(3, "PWM0"),
+ MTK_FUNCTION(4, "CLKM0")
+ ),
+
+ MTK_PIN(
+ 81, "GPIO81",
+ MTK_EINT_FUNCTION(0, 81),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "KPROW0"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(4, "CLKM1")
+ ),
+
+ MTK_PIN(
+ 82, "GPIO82",
+ MTK_EINT_FUNCTION(0, 82),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "KPROW1"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(4, "CLKM2")
+ ),
+
+ MTK_PIN(
+ 83, "GPIO83",
+ MTK_EINT_FUNCTION(0, 83),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "AP_GOOD"),
+ MTK_FUNCTION(2, "GPS_PPS"),
+ MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+ MTK_FUNCTION(7, "dbg_mon_a28")
+ ),
+
+ MTK_PIN(
+ 84, "GPIO84",
+ MTK_EINT_FUNCTION(0, 84),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "ADSP_JTAG_TCK"),
+ MTK_FUNCTION(4, "UDI_TCK"),
+ MTK_FUNCTION(5, "CONN_DSP_JCK"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TCK"),
+ MTK_FUNCTION(7, "DFD_TCK_XI")
+ ),
+
+ MTK_PIN(
+ 85, "GPIO85",
+ MTK_EINT_FUNCTION(0, 85),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(2, "ADSP_JTAG_TMS"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_TMSC"),
+ MTK_FUNCTION(4, "UDI_TMS"),
+ MTK_FUNCTION(5, "CONN_DSP_JMS"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TMS"),
+ MTK_FUNCTION(7, "DFD_TMS")
+ ),
+
+ MTK_PIN(
+ 86, "GPIO86",
+ MTK_EINT_FUNCTION(0, 86),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(2, "ADSP_JTAG_TDI"),
+ MTK_FUNCTION(4, "UDI_TDI"),
+ MTK_FUNCTION(5, "CONN_DSP_JDI"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TDI"),
+ MTK_FUNCTION(7, "DFD_TDI")
+ ),
+
+ MTK_PIN(
+ 87, "GPIO87",
+ MTK_EINT_FUNCTION(0, 87),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "ADSP_JTAG_TDO"),
+ MTK_FUNCTION(4, "UDI_TDO"),
+ MTK_FUNCTION(5, "CONN_DSP_JDO"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TDO"),
+ MTK_FUNCTION(7, "DFD_TDO")
+ ),
+
+ MTK_PIN(
+ 88, "GPIO88",
+ MTK_EINT_FUNCTION(0, 88),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(2, "ADSP_JTAG_TRSTN"),
+ MTK_FUNCTION(3, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(4, "UDI_NTRST"),
+ MTK_FUNCTION(5, "CONN_WIFI_TXD"),
+ MTK_FUNCTION(6, "SSPM_JTAG_TRSTN")
+ ),
+
+ MTK_PIN(
+ 89, "GPIO89",
+ MTK_EINT_FUNCTION(0, 89),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(5, "CONN_DSP_JINTP")
+ ),
+
+ MTK_PIN(
+ 90, "GPIO90",
+ MTK_EINT_FUNCTION(0, 90),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "IDDIG_P0"),
+ MTK_FUNCTION(4, "PGD_HV_HSC_PWR4"),
+ MTK_FUNCTION(5, "GDU_SUM_TROOP2_2")
+ ),
+
+ MTK_PIN(
+ 91, "GPIO91",
+ MTK_EINT_FUNCTION(0, 91),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "USB_DRVVBUS_P0"),
+ MTK_FUNCTION(4, "PGD_HV_HSC_PWR5"),
+ MTK_FUNCTION(5, "GDU_TROOPS_DET0")
+ ),
+
+ MTK_PIN(
+ 92, "GPIO92",
+ MTK_EINT_FUNCTION(0, 92),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "VBUS_VALID_P0"),
+ MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY"),
+ MTK_FUNCTION(5, "GDU_TROOPS_DET1")
+ ),
+
+ MTK_PIN(
+ 93, "GPIO93",
+ MTK_EINT_FUNCTION(0, 93),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "IDDIG_P1"),
+ MTK_FUNCTION(2, "PWM0"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY_PRE"),
+ MTK_FUNCTION(5, "GDU_TROOPS_DET2")
+ ),
+
+ MTK_PIN(
+ 94, "GPIO94",
+ MTK_EINT_FUNCTION(0, 94),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "USB_DRVVBUS_P1"),
+ MTK_FUNCTION(2, "PWM1"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "PGD_DA_PWRGD_RESET")
+ ),
+
+ MTK_PIN(
+ 95, "GPIO95",
+ MTK_EINT_FUNCTION(0, 95),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "VBUS_VALID_P1"),
+ MTK_FUNCTION(2, "PWM2"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "PGD_DA_PWRGD_ENB")
+ ),
+
+ MTK_PIN(
+ 96, "GPIO96",
+ MTK_EINT_FUNCTION(0, 96),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "DSI_TE"),
+ MTK_FUNCTION(7, "dbg_mon_a29")
+ ),
+
+ MTK_PIN(
+ 97, "GPIO97",
+ MTK_EINT_FUNCTION(0, 97),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "DISP_PWM"),
+ MTK_FUNCTION(7, "dbg_mon_a30")
+ ),
+
+ MTK_PIN(
+ 98, "GPIO98",
+ MTK_EINT_FUNCTION(0, 98),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "LCM_RST")
+ ),
+
+ MTK_PIN(
+ 99, "GPIO99",
+ MTK_EINT_FUNCTION(0, 99),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "DPI_PCLK"),
+ MTK_FUNCTION(2, "GPS_L1_ELNA_EN"),
+ MTK_FUNCTION(3, "SSPM_JTAG_TCK"),
+ MTK_FUNCTION(5, "ANT_SEL0"),
+ MTK_FUNCTION(6, "TP_GPIO0_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR0")
+ ),
+
+ MTK_PIN(
+ 100, "GPIO100",
+ MTK_EINT_FUNCTION(0, 100),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "DPI_VSYNC"),
+ MTK_FUNCTION(2, "KPCOL2"),
+ MTK_FUNCTION(3, "SSPM_JTAG_TMS"),
+ MTK_FUNCTION(5, "ANT_SEL1"),
+ MTK_FUNCTION(6, "TP_GPIO1_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR1")
+ ),
+
+ MTK_PIN(
+ 101, "GPIO101",
+ MTK_EINT_FUNCTION(0, 101),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "DPI_HSYNC"),
+ MTK_FUNCTION(2, "KPROW2"),
+ MTK_FUNCTION(3, "SSPM_JTAG_TDI"),
+ MTK_FUNCTION(5, "ANT_SEL2"),
+ MTK_FUNCTION(6, "TP_GPIO2_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR2")
+ ),
+
+ MTK_PIN(
+ 102, "GPIO102",
+ MTK_EINT_FUNCTION(0, 102),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "DPI_DE"),
+ MTK_FUNCTION(3, "SSPM_JTAG_TDO"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "TP_GPIO3_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR3")
+ ),
+
+ MTK_PIN(
+ 103, "GPIO103",
+ MTK_EINT_FUNCTION(0, 103),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "DPI_DATA0"),
+ MTK_FUNCTION(3, "SSPM_JTAG_TRSTN"),
+ MTK_FUNCTION(4, "CLKM0"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "TP_GPIO4_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR4")
+ ),
+
+ MTK_PIN(
+ 104, "GPIO104",
+ MTK_EINT_FUNCTION(0, 104),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "DPI_DATA1"),
+ MTK_FUNCTION(2, "GPS_PPS"),
+ MTK_FUNCTION(3, "UCTS2"),
+ MTK_FUNCTION(4, "CLKM1"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(6, "TP_GPIO5_AO"),
+ MTK_FUNCTION(7, "PGD_LV_LSC_PWR5")
+ ),
+
+ MTK_PIN(
+ 105, "GPIO105",
+ MTK_EINT_FUNCTION(0, 105),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "DPI_DATA2"),
+ MTK_FUNCTION(2, "CONN_TCXOENA_REQ"),
+ MTK_FUNCTION(3, "URTS2"),
+ MTK_FUNCTION(4, "CLKM2"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(6, "TP_GPIO6_AO"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR0")
+ ),
+
+ MTK_PIN(
+ 106, "GPIO106",
+ MTK_EINT_FUNCTION(0, 106),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "DPI_DATA3"),
+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
+ MTK_FUNCTION(3, "UTXD2"),
+ MTK_FUNCTION(4, "PWM0"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(6, "TP_GPIO7_AO"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR1")
+ ),
+
+ MTK_PIN(
+ 107, "GPIO107",
+ MTK_EINT_FUNCTION(0, 107),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "DPI_DATA4"),
+ MTK_FUNCTION(2, "TP_URXD1_AO"),
+ MTK_FUNCTION(3, "URXD2"),
+ MTK_FUNCTION(4, "PWM1"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP0_0"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR2")
+ ),
+
+ MTK_PIN(
+ 108, "GPIO108",
+ MTK_EINT_FUNCTION(0, 108),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "DPI_DATA5"),
+ MTK_FUNCTION(2, "TP_UCTS1_AO"),
+ MTK_FUNCTION(3, "UCTS0"),
+ MTK_FUNCTION(4, "PWM2"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP0_1"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR3")
+ ),
+
+ MTK_PIN(
+ 109, "GPIO109",
+ MTK_EINT_FUNCTION(0, 109),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "DPI_DATA6"),
+ MTK_FUNCTION(2, "TP_URTS1_AO"),
+ MTK_FUNCTION(3, "URTS0"),
+ MTK_FUNCTION(4, "I2S0_DI"),
+ MTK_FUNCTION(5, "I2S2_DI"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP0_2"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR4")
+ ),
+
+ MTK_PIN(
+ 110, "GPIO110",
+ MTK_EINT_FUNCTION(0, 110),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "DPI_DATA7"),
+ MTK_FUNCTION(2, "TP_UCTS2_AO"),
+ MTK_FUNCTION(3, "UCTS1"),
+ MTK_FUNCTION(4, "I2S3_BCK"),
+ MTK_FUNCTION(5, "I2S1_BCK"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP1_0"),
+ MTK_FUNCTION(7, "PGD_LV_HSC_PWR5")
+ ),
+
+ MTK_PIN(
+ 111, "GPIO111",
+ MTK_EINT_FUNCTION(0, 111),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "DPI_DATA8"),
+ MTK_FUNCTION(2, "TP_URTS2_AO"),
+ MTK_FUNCTION(3, "URTS1"),
+ MTK_FUNCTION(4, "I2S3_MCK"),
+ MTK_FUNCTION(5, "I2S1_MCK"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP1_1"),
+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR0")
+ ),
+
+ MTK_PIN(
+ 112, "GPIO112",
+ MTK_EINT_FUNCTION(0, 112),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "DPI_DATA9"),
+ MTK_FUNCTION(2, "TP_URXD2_AO"),
+ MTK_FUNCTION(3, "URXD1"),
+ MTK_FUNCTION(4, "I2S3_LRCK"),
+ MTK_FUNCTION(5, "I2S1_LRCK"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP1_2"),
+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR1")
+ ),
+
+ MTK_PIN(
+ 113, "GPIO113",
+ MTK_EINT_FUNCTION(0, 113),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "DPI_DATA10"),
+ MTK_FUNCTION(2, "TP_UTXD2_AO"),
+ MTK_FUNCTION(3, "UTXD1"),
+ MTK_FUNCTION(4, "I2S3_DO"),
+ MTK_FUNCTION(5, "I2S1_DO"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP2_0"),
+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR2")
+ ),
+
+ MTK_PIN(
+ 114, "GPIO114",
+ MTK_EINT_FUNCTION(0, 114),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "DPI_DATA11"),
+ MTK_FUNCTION(6, "GDU_SUM_TROOP2_1"),
+ MTK_FUNCTION(7, "PGD_HV_HSC_PWR3")
+ ),
+
+ MTK_PIN(
+ 115, "GPIO115",
+ MTK_EINT_FUNCTION(0, 115),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "PCM_CLK"),
+ MTK_FUNCTION(2, "I2S0_BCK"),
+ MTK_FUNCTION(3, "I2S2_BCK")
+ ),
+
+ MTK_PIN(
+ 116, "GPIO116",
+ MTK_EINT_FUNCTION(0, 116),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "PCM_SYNC"),
+ MTK_FUNCTION(2, "I2S0_LRCK"),
+ MTK_FUNCTION(3, "I2S2_LRCK")
+ ),
+
+ MTK_PIN(
+ 117, "GPIO117",
+ MTK_EINT_FUNCTION(0, 117),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "PCM_DI"),
+ MTK_FUNCTION(2, "I2S0_DI"),
+ MTK_FUNCTION(3, "I2S2_DI")
+ ),
+
+ MTK_PIN(
+ 118, "GPIO118",
+ MTK_EINT_FUNCTION(0, 118),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "PCM_DO"),
+ MTK_FUNCTION(2, "I2S0_MCK"),
+ MTK_FUNCTION(3, "I2S2_MCK"),
+ MTK_FUNCTION(4, "I2S3_DO"),
+ MTK_FUNCTION(5, "I2S1_DO")
+ ),
+
+ MTK_PIN(
+ 119, "GPIO119",
+ MTK_EINT_FUNCTION(0, 119),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "JTMS_SEL1"),
+ MTK_FUNCTION(2, "UDI_TMS"),
+ MTK_FUNCTION(3, "DFD_TMS"),
+ MTK_FUNCTION(4, "SPM_JTAG_TMS"),
+ MTK_FUNCTION(5, "SCP_JTAG_TMS"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TMS")
+ ),
+
+ MTK_PIN(
+ 120, "GPIO120",
+ MTK_EINT_FUNCTION(0, 120),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "JTCK_SEL1"),
+ MTK_FUNCTION(2, "UDI_TCK"),
+ MTK_FUNCTION(3, "DFD_TCK_XI"),
+ MTK_FUNCTION(4, "SPM_JTAG_TCK"),
+ MTK_FUNCTION(5, "SCP_JTAG_TCK"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TCK")
+ ),
+
+ MTK_PIN(
+ 121, "GPIO121",
+ MTK_EINT_FUNCTION(0, 121),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "JTDI_SEL1"),
+ MTK_FUNCTION(2, "UDI_TDI"),
+ MTK_FUNCTION(3, "DFD_TDI"),
+ MTK_FUNCTION(4, "SPM_JTAG_TDI"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDI"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TDI")
+ ),
+
+ MTK_PIN(
+ 122, "GPIO122",
+ MTK_EINT_FUNCTION(0, 122),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "JTDO_SEL1"),
+ MTK_FUNCTION(2, "UDI_TDO"),
+ MTK_FUNCTION(3, "DFD_TDO"),
+ MTK_FUNCTION(4, "SPM_JTAG_TDO"),
+ MTK_FUNCTION(5, "SCP_JTAG_TDO"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TDO")
+ ),
+
+ MTK_PIN(
+ 123, "GPIO123",
+ MTK_EINT_FUNCTION(0, 123),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "JTRSTN_SEL1"),
+ MTK_FUNCTION(2, "UDI_NTRST"),
+ MTK_FUNCTION(4, "SPM_JTAG_TRSTN"),
+ MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "ADSP_JTAG_TRSTN")
+ ),
+
+ MTK_PIN(
+ 124, "GPIO124",
+ MTK_EINT_FUNCTION(0, 124),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "CMMCLK0"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(3, "PWM0")
+ ),
+
+ MTK_PIN(
+ 125, "GPIO125",
+ MTK_EINT_FUNCTION(0, 125),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "CMMCLK1"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "PWM1"),
+ MTK_FUNCTION(7, "dbg_mon_b0")
+ ),
+
+ MTK_PIN(
+ 126, "GPIO126",
+ MTK_EINT_FUNCTION(0, 126),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "CMMCLK2"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(3, "PWM2"),
+ MTK_FUNCTION(7, "dbg_mon_b1")
+ ),
+
+ MTK_PIN(
+ 127, "GPIO127",
+ MTK_EINT_FUNCTION(0, 127),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "SCL0"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1")
+ ),
+
+ MTK_PIN(
+ 128, "GPIO128",
+ MTK_EINT_FUNCTION(0, 128),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "SDA0"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1")
+ ),
+
+ MTK_PIN(
+ 129, "GPIO129",
+ MTK_EINT_FUNCTION(0, 129),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "SCL1"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b4")
+ ),
+
+ MTK_PIN(
+ 130, "GPIO130",
+ MTK_EINT_FUNCTION(0, 130),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "SDA1"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b5")
+ ),
+
+ MTK_PIN(
+ 131, "GPIO131",
+ MTK_EINT_FUNCTION(0, 131),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "SCL2"),
+ MTK_FUNCTION(2, "SSPM_UTXD_AO"),
+ MTK_FUNCTION(3, "CONN_UART0_TXD"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b6")
+ ),
+
+ MTK_PIN(
+ 132, "GPIO132",
+ MTK_EINT_FUNCTION(0, 132),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "SDA2"),
+ MTK_FUNCTION(2, "SSPM_URXD_AO"),
+ MTK_FUNCTION(3, "CONN_UART0_RXD"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b7")
+ ),
+
+ MTK_PIN(
+ 133, "GPIO133",
+ MTK_EINT_FUNCTION(0, 133),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "SCL3"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b8")
+ ),
+
+ MTK_PIN(
+ 134, "GPIO134",
+ MTK_EINT_FUNCTION(0, 134),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "SDA3"),
+ MTK_FUNCTION(3, "GPS_PPS"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b9")
+ ),
+
+ MTK_PIN(
+ 135, "GPIO135",
+ MTK_EINT_FUNCTION(0, 135),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "SCL4"),
+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
+ MTK_FUNCTION(3, "UTXD1"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b10")
+ ),
+
+ MTK_PIN(
+ 136, "GPIO136",
+ MTK_EINT_FUNCTION(0, 136),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "SDA4"),
+ MTK_FUNCTION(2, "TP_URXD1_AO"),
+ MTK_FUNCTION(3, "URXD1"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b11")
+ ),
+
+ MTK_PIN(
+ 137, "GPIO137",
+ MTK_EINT_FUNCTION(0, 137),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "SCL5"),
+ MTK_FUNCTION(2, "UTXD2"),
+ MTK_FUNCTION(3, "UCTS1"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1")
+ ),
+
+ MTK_PIN(
+ 138, "GPIO138",
+ MTK_EINT_FUNCTION(0, 138),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "SDA5"),
+ MTK_FUNCTION(2, "URXD2"),
+ MTK_FUNCTION(3, "URTS1"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1")
+ ),
+
+ MTK_PIN(
+ 139, "GPIO139",
+ MTK_EINT_FUNCTION(0, 139),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "SCL6"),
+ MTK_FUNCTION(2, "UTXD1"),
+ MTK_FUNCTION(3, "TP_UTXD1_AO"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b12")
+ ),
+
+ MTK_PIN(
+ 140, "GPIO140",
+ MTK_EINT_FUNCTION(0, 140),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "SDA6"),
+ MTK_FUNCTION(2, "URXD1"),
+ MTK_FUNCTION(3, "TP_URXD1_AO"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b13")
+ ),
+
+ MTK_PIN(
+ 141, "GPIO141",
+ MTK_EINT_FUNCTION(0, 141),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "SCL7"),
+ MTK_FUNCTION(2, "URTS0"),
+ MTK_FUNCTION(3, "TP_URTS1_AO"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(6, "UDI_TCK"),
+ MTK_FUNCTION(7, "dbg_mon_b14")
+ ),
+
+ MTK_PIN(
+ 142, "GPIO142",
+ MTK_EINT_FUNCTION(0, 142),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "SDA7"),
+ MTK_FUNCTION(2, "UCTS0"),
+ MTK_FUNCTION(3, "TP_UCTS1_AO"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1")
+ ),
+
+ MTK_PIN(
+ 143, "GPIO143",
+ MTK_EINT_FUNCTION(0, 143),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "SCL8"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b16")
+ ),
+
+ MTK_PIN(
+ 144, "GPIO144",
+ MTK_EINT_FUNCTION(0, 144),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "SDA8"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b17")
+ ),
+
+ MTK_PIN(
+ 145, "GPIO145",
+ MTK_EINT_FUNCTION(0, 145),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "SCL9"),
+ MTK_FUNCTION(2, "CMVREF1"),
+ MTK_FUNCTION(3, "GPS_PPS"),
+ MTK_FUNCTION(4, "SCP_SCL0"),
+ MTK_FUNCTION(5, "SCP_SCL1"),
+ MTK_FUNCTION(7, "dbg_mon_b18")
+ ),
+
+ MTK_PIN(
+ 146, "GPIO146",
+ MTK_EINT_FUNCTION(0, 146),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "SDA9"),
+ MTK_FUNCTION(2, "CMVREF0"),
+ MTK_FUNCTION(4, "SCP_SDA0"),
+ MTK_FUNCTION(5, "SCP_SDA1"),
+ MTK_FUNCTION(7, "dbg_mon_b19")
+ ),
+
+ MTK_PIN(
+ 147, "GPIO147",
+ MTK_EINT_FUNCTION(0, 147),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "CMFLASH0"),
+ MTK_FUNCTION(2, "LVTS_SDI"),
+ MTK_FUNCTION(3, "DPI_DATA12"),
+ MTK_FUNCTION(4, "TP_GPIO0_AO"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "dbg_mon_b20")
+ ),
+
+ MTK_PIN(
+ 148, "GPIO148",
+ MTK_EINT_FUNCTION(0, 148),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "CMFLASH1"),
+ MTK_FUNCTION(2, "LVTS_SCF"),
+ MTK_FUNCTION(3, "DPI_DATA13"),
+ MTK_FUNCTION(4, "TP_GPIO1_AO"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "DFD_TMS"),
+ MTK_FUNCTION(7, "dbg_mon_b21")
+ ),
+
+ MTK_PIN(
+ 149, "GPIO149",
+ MTK_EINT_FUNCTION(0, 149),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "CMFLASH2"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(3, "DPI_DATA14"),
+ MTK_FUNCTION(4, "TP_GPIO2_AO"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(6, "DFD_TDI"),
+ MTK_FUNCTION(7, "dbg_mon_b22")
+ ),
+
+ MTK_PIN(
+ 150, "GPIO150",
+ MTK_EINT_FUNCTION(0, 150),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "DPI_DATA15"),
+ MTK_FUNCTION(4, "TP_GPIO3_AO"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(6, "DFD_TDO"),
+ MTK_FUNCTION(7, "dbg_mon_b23")
+ ),
+
+ MTK_PIN(
+ 151, "GPIO151",
+ MTK_EINT_FUNCTION(0, 151),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "GPS_L1_ELNA_EN"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(3, "DPI_DATA16"),
+ MTK_FUNCTION(4, "TP_GPIO4_AO"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(6, "UDI_TMS"),
+ MTK_FUNCTION(7, "dbg_mon_b24")
+ ),
+
+ MTK_PIN(
+ 152, "GPIO152",
+ MTK_EINT_FUNCTION(0, 152),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(2, "CLKM3"),
+ MTK_FUNCTION(3, "DPI_DATA17"),
+ MTK_FUNCTION(4, "TP_GPIO5_AO")
+ ),
+
+ MTK_PIN(
+ 153, "GPIO153",
+ MTK_EINT_FUNCTION(0, 153),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "CONN_TCXOENA_REQ"),
+ MTK_FUNCTION(3, "DPI_DATA18"),
+ MTK_FUNCTION(4, "TP_GPIO6_AO"),
+ MTK_FUNCTION(6, "UDI_TDI"),
+ MTK_FUNCTION(7, "dbg_mon_b26")
+ ),
+
+ MTK_PIN(
+ 154, "GPIO154",
+ MTK_EINT_FUNCTION(0, 154),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "PWM0"),
+ MTK_FUNCTION(2, "CMVREF2"),
+ MTK_FUNCTION(3, "DPI_DATA19"),
+ MTK_FUNCTION(4, "TP_GPIO7_AO"),
+ MTK_FUNCTION(6, "UDI_TDO"),
+ MTK_FUNCTION(7, "dbg_mon_b27")
+ ),
+
+ MTK_PIN(
+ 155, "GPIO155",
+ MTK_EINT_FUNCTION(0, 155),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "PWM1"),
+ MTK_FUNCTION(2, "CMVREF1"),
+ MTK_FUNCTION(3, "DPI_DATA20"),
+ MTK_FUNCTION(6, "UDI_NTRST"),
+ MTK_FUNCTION(7, "dbg_mon_b28")
+ ),
+
+ MTK_PIN(
+ 156, "GPIO156",
+ MTK_EINT_FUNCTION(0, 156),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "PWM2"),
+ MTK_FUNCTION(2, "CMVREF0"),
+ MTK_FUNCTION(3, "DPI_DATA21")
+ ),
+
+ MTK_PIN(
+ 157, "GPIO157",
+ MTK_EINT_FUNCTION(0, 157),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
+ ),
+
+ MTK_PIN(
+ 158, "GPIO158",
+ MTK_EINT_FUNCTION(0, 158),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_CK")
+ ),
+
+ MTK_PIN(
+ 159, "GPIO159",
+ MTK_EINT_FUNCTION(0, 159),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
+ MTK_FUNCTION(2, "PWRAP_SPI0_MI")
+ ),
+
+ MTK_PIN(
+ 160, "GPIO160",
+ MTK_EINT_FUNCTION(0, 160),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
+ MTK_FUNCTION(2, "PWRAP_SPI0_MO")
+ ),
+
+ MTK_PIN(
+ 161, "GPIO161",
+ MTK_EINT_FUNCTION(0, 161),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, "SRCLKENA0")
+ ),
+
+ MTK_PIN(
+ 162, "GPIO162",
+ MTK_EINT_FUNCTION(0, 162),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, "SRCLKENA1"),
+ MTK_FUNCTION(7, "dbg_mon_a31")
+ ),
+
+ MTK_PIN(
+ 163, "GPIO163",
+ MTK_EINT_FUNCTION(0, 163),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, "SCP_VREQ_VAO"),
+ MTK_FUNCTION(2, "DVFSRC_EXT_REQ")
+ ),
+
+ MTK_PIN(
+ 164, "GPIO164",
+ MTK_EINT_FUNCTION(0, 164),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+
+ MTK_PIN(
+ 165, "GPIO165",
+ MTK_EINT_FUNCTION(0, 165),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+
+ MTK_PIN(
+ 166, "GPIO166",
+ MTK_EINT_FUNCTION(0, 166),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, "AUD_CLK_MOSI"),
+ MTK_FUNCTION(2, "AUD_CLK_MISO"),
+ MTK_FUNCTION(3, "I2S1_MCK")
+ ),
+
+ MTK_PIN(
+ 167, "GPIO167",
+ MTK_EINT_FUNCTION(0, 167),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, "AUD_SYNC_MOSI"),
+ MTK_FUNCTION(2, "AUD_SYNC_MISO"),
+ MTK_FUNCTION(3, "I2S1_BCK")
+ ),
+
+ MTK_PIN(
+ 168, "GPIO168",
+ MTK_EINT_FUNCTION(0, 168),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI0"),
+ MTK_FUNCTION(2, "AUD_DAT_MISO0"),
+ MTK_FUNCTION(3, "I2S1_LRCK")
+ ),
+
+ MTK_PIN(
+ 169, "GPIO169",
+ MTK_EINT_FUNCTION(0, 169),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI1"),
+ MTK_FUNCTION(2, "AUD_DAT_MISO1"),
+ MTK_FUNCTION(3, "I2S1_DO")
+ ),
+
+ MTK_PIN(
+ 170, "GPIO170",
+ MTK_EINT_FUNCTION(0, 170),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "AUD_CLK_MISO"),
+ MTK_FUNCTION(2, "AUD_CLK_MOSI"),
+ MTK_FUNCTION(3, "I2S2_MCK")
+ ),
+
+ MTK_PIN(
+ 171, "GPIO171",
+ MTK_EINT_FUNCTION(0, 171),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "AUD_SYNC_MISO"),
+ MTK_FUNCTION(2, "AUD_SYNC_MOSI"),
+ MTK_FUNCTION(3, "I2S2_BCK")
+ ),
+
+ MTK_PIN(
+ 172, "GPIO172",
+ MTK_EINT_FUNCTION(0, 172),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO0"),
+ MTK_FUNCTION(2, "AUD_DAT_MOSI0"),
+ MTK_FUNCTION(3, "I2S2_LRCK"),
+ MTK_FUNCTION(4, "VOW_DAT_MISO")
+ ),
+
+ MTK_PIN(
+ 173, "GPIO173",
+ MTK_EINT_FUNCTION(0, 173),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO1"),
+ MTK_FUNCTION(2, "AUD_DAT_MOSI1"),
+ MTK_FUNCTION(3, "I2S2_DI"),
+ MTK_FUNCTION(4, "VOW_CLK_MISO")
+ ),
+
+ MTK_PIN(
+ 174, "GPIO174",
+ MTK_EINT_FUNCTION(0, 174),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "CONN_TOP_CLK"),
+ MTK_FUNCTION(2, "AUXIF_CLK"),
+ MTK_FUNCTION(3, "DFD_TCK_XI"),
+ MTK_FUNCTION(7, "dbg_mon_b3")
+ ),
+
+ MTK_PIN(
+ 175, "GPIO175",
+ MTK_EINT_FUNCTION(0, 175),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "CONN_TOP_DATA"),
+ MTK_FUNCTION(2, "AUXIF_ST"),
+ MTK_FUNCTION(3, "DFD_TMS"),
+ MTK_FUNCTION(7, "dbg_mon_b15")
+ ),
+
+ MTK_PIN(
+ 176, "GPIO176",
+ MTK_EINT_FUNCTION(0, 176),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "CONN_BT_CLK"),
+ MTK_FUNCTION(3, "DFD_TDI"),
+ MTK_FUNCTION(7, "dbg_mon_b2")
+ ),
+
+ MTK_PIN(
+ 177, "GPIO177",
+ MTK_EINT_FUNCTION(0, 177),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "CONN_BT_DATA"),
+ MTK_FUNCTION(3, "DFD_TDO")
+ ),
+
+ MTK_PIN(
+ 178, "GPIO178",
+ MTK_EINT_FUNCTION(0, 178),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "CONN_HRST_B"),
+ MTK_FUNCTION(3, "UDI_TMS"),
+ MTK_FUNCTION(7, "dbg_mon_b25")
+ ),
+
+ MTK_PIN(
+ 179, "GPIO179",
+ MTK_EINT_FUNCTION(0, 179),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "CONN_WB_PTA"),
+ MTK_FUNCTION(3, "UDI_TCK"),
+ MTK_FUNCTION(7, "dbg_mon_b29")
+ ),
+
+ MTK_PIN(
+ 180, "GPIO180",
+ MTK_EINT_FUNCTION(0, 180),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL0"),
+ MTK_FUNCTION(3, "UDI_TDI")
+ ),
+
+ MTK_PIN(
+ 181, "GPIO181",
+ MTK_EINT_FUNCTION(0, 181),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL1"),
+ MTK_FUNCTION(3, "UDI_TDO")
+ ),
+
+ MTK_PIN(
+ 182, "GPIO182",
+ MTK_EINT_FUNCTION(0, 182),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "CONN_WF_CTRL2"),
+ MTK_FUNCTION(3, "UDI_NTRST")
+ ),
+
+ MTK_PIN(
+ 183, "GPIO183",
+ MTK_EINT_FUNCTION(0, 183),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "SPMI_SCL")
+ ),
+
+ MTK_PIN(
+ 184, "GPIO184",
+ MTK_EINT_FUNCTION(0, 184),
+ DRV_GRP4,
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "SPMI_SDA")
+ ),
+
+ MTK_PIN(
+ 185, "GPIO185",
+ MTK_EINT_FUNCTION(0, 197),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 186, "GPIO186",
+ MTK_EINT_FUNCTION(0, 198),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 187, "GPIO187",
+ MTK_EINT_FUNCTION(0, 199),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 188, "GPIO188",
+ MTK_EINT_FUNCTION(0, 200),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 189, "GPIO189",
+ MTK_EINT_FUNCTION(0, 201),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 190, "GPIO190",
+ MTK_EINT_FUNCTION(0, 202),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 191, "GPIO191",
+ MTK_EINT_FUNCTION(0, 203),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 192, "GPIO192",
+ MTK_EINT_FUNCTION(0, 204),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 193, "GPIO193",
+ MTK_EINT_FUNCTION(0, 205),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 194, "GPIO194",
+ MTK_EINT_FUNCTION(0, 206),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 195, "GPIO195",
+ MTK_EINT_FUNCTION(0, 207),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ ),
+
+ MTK_PIN(
+ 196, "GPIO196",
+ MTK_EINT_FUNCTION(0, 208),
+ DRV_FIXED,
+ MTK_FUNCTION(0, NULL)
+ )
+};
+
+#endif /* __PINCTRL_MTK_MT8186_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 3/3] pinctrl: canonical rsel resistance selection property
2022-02-10 6:21 [PATCH v3 0/2] pinctrl: mediatek: Support pinctrl driver on mt8186 Guodong Liu
2022-02-10 6:21 ` [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document Guodong Liu
2022-02-10 6:21 ` [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186 Guodong Liu
@ 2022-02-10 6:21 ` Guodong Liu
2022-02-10 8:50 ` AngeloGioacchino Del Regno
2 siblings, 1 reply; 13+ messages in thread
From: Guodong Liu @ 2022-02-10 6:21 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, Guodong Liu
Change "mediatek,rsel_resistance_in_si_unit" to "mediatek,rsel-resistance-in-si-unit"
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
---
drivers/pinctrl/mediatek/pinctrl-paris.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index d4e02c5d74a8..38c0f0c4cf95 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -989,7 +989,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
hw->nbase = hw->soc->nbase_names;
if (of_find_property(hw->dev->of_node,
- "mediatek,rsel_resistance_in_si_unit", NULL))
+ "mediatek,rsel-resistance-in-si-unit", NULL))
hw->rsel_si_unit = true;
else
hw->rsel_si_unit = false;
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 3/3] pinctrl: canonical rsel resistance selection property
2022-02-10 6:21 ` [PATCH v3 3/3] pinctrl: canonical rsel resistance selection property Guodong Liu
@ 2022-02-10 8:50 ` AngeloGioacchino Del Regno
2022-02-14 3:03 ` Guodong Liu
0 siblings, 1 reply; 13+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-10 8:50 UTC (permalink / raw)
To: Guodong Liu, Linus Walleij, Rob Herring, Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Il 10/02/22 07:21, Guodong Liu ha scritto:
> Change "mediatek,rsel_resistance_in_si_unit" to "mediatek,rsel-resistance-in-si-unit"
>
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Hello Guodong,
thanks for the patch!
However, you forgot to add the required Fixes tag to this one; this patch
should be fixing fb34a9ae383a ("pinctrl: mediatek: support rsel feature").
Please add the required tag.
Thanks,
Angelo
> ---
> drivers/pinctrl/mediatek/pinctrl-paris.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
> index d4e02c5d74a8..38c0f0c4cf95 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-paris.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
> @@ -989,7 +989,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
> hw->nbase = hw->soc->nbase_names;
>
> if (of_find_property(hw->dev->of_node,
> - "mediatek,rsel_resistance_in_si_unit", NULL))
> + "mediatek,rsel-resistance-in-si-unit", NULL))
> hw->rsel_si_unit = true;
> else
> hw->rsel_si_unit = false;
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186
2022-02-10 6:21 ` [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186 Guodong Liu
@ 2022-02-10 8:57 ` AngeloGioacchino Del Regno
2022-02-14 3:02 ` Guodong Liu
0 siblings, 1 reply; 13+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-10 8:57 UTC (permalink / raw)
To: Guodong Liu, Linus Walleij, Rob Herring, Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
Il 10/02/22 07:21, Guodong Liu ha scritto:
> This commit includes pinctrl driver for mt8186.
>
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> ---
> drivers/pinctrl/mediatek/Kconfig | 7 +
> drivers/pinctrl/mediatek/Makefile | 1 +
> drivers/pinctrl/mediatek/pinctrl-mt8186.c | 1313 ++++++++++
> drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h | 2186 +++++++++++++++++
> 4 files changed, 3507 insertions(+)
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8186.c
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
>
> diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
> index 66db4ac5d169..8dca1ef04965 100644
> --- a/drivers/pinctrl/mediatek/Kconfig
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -147,6 +147,13 @@ config PINCTRL_MT8183
> default ARM64 && ARCH_MEDIATEK
> select PINCTRL_MTK_PARIS
>
> +config PINCTRL_MT8186
> + bool "Mediatek MT8186 pin control"
> + depends on OF
> + depends on ARM64 || COMPILE_TEST
> + default ARM64 && ARCH_MEDIATEK
> + select PINCTRL_MTK_PARIS
> +
> config PINCTRL_MT8192
> bool "Mediatek MT8192 pin control"
> depends on OF
> diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
> index 90f43bb9d9a7..31c3784c6089 100644
> --- a/drivers/pinctrl/mediatek/Makefile
> +++ b/drivers/pinctrl/mediatek/Makefile
> @@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
> obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
> obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
> obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
> +obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
> obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
> obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
> obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8186.c b/drivers/pinctrl/mediatek/pinctrl-mt8186.c
> new file mode 100644
> index 000000000000..1e550b15b9d4
> --- /dev/null
> +++ b/drivers/pinctrl/mediatek/pinctrl-mt8186.c
> @@ -0,0 +1,1313 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + *
> + * Author: Guodong Liu <guodong.liu@mediatek.com>
> + *
> + */
> +
> +#include "pinctrl-mtk-mt8186.h"
> +#include "pinctrl-paris.h"
> +
> +/* MT8186 have multiple bases to program pin configuration listed as the below:
> + * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
> + * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
> + * iocfg[6]:0x10002C00.
> + * _i_based could be used to indicate what base the pin should be mapped into.
> + */
> +
> +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
> + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
> + 32, 0)
Please don't break this line: 84 columns is fine.
> +
> +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
> + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
> + 32, 1)
Same here.
And with that fixed,
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document
2022-02-10 6:21 ` [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document Guodong Liu
@ 2022-02-10 14:47 ` Rob Herring
2022-02-14 3:03 ` Guodong Liu
2022-02-11 0:10 ` Linus Walleij
2022-02-11 12:28 ` Rob Herring
2 siblings, 1 reply; 13+ messages in thread
From: Rob Herring @ 2022-02-10 14:47 UTC (permalink / raw)
To: Guodong Liu
Cc: Linus Walleij, Sean Wang, linux-mediatek, Rob Herring,
linux-arm-kernel, linux-kernel,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
linux-gpio, Sean Wang, devicetree
On Thu, 10 Feb 2022 14:21:20 +0800, Guodong Liu wrote:
> 1. This patch adds pinctrl file for mt8186.
> 2. This patch adds mt8186 compatible node in binding document.
>
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> ---
> .../bindings/pinctrl/pinctrl-mt8186.yaml | 313 +++++
> include/dt-bindings/pinctrl/mt8186-pinfunc.h | 1174 +++++++++++++++++
> 2 files changed, 1487 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
> create mode 100644 include/dt-bindings/pinctrl/mt8186-pinfunc.h
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml: properties:reg-names: {'description': 'Gpio base register names.\n', 'items': [{'const': 'iocfg0'}, {'const': 'iocfg_bm'}, {'const': 'iocfg_bl'}, {'const': 'iocfg_br'}, {'const': 'iocfg_lm'}, {'const': 'iocfg_rb'}, {'const': 'iocfg_tl'}, {'const': 'eint'}], 'maxItems': 8} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml: ignoring, error in schema: properties: reg-names
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.example.dt.yaml:0:0: /example-0/pinctrl@10005000: failed to match any schema with compatible: ['mediatek,mt8186-pinctrl']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1590838
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document
2022-02-10 6:21 ` [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document Guodong Liu
2022-02-10 14:47 ` Rob Herring
@ 2022-02-11 0:10 ` Linus Walleij
2022-02-11 12:28 ` Rob Herring
2 siblings, 0 replies; 13+ messages in thread
From: Linus Walleij @ 2022-02-11 0:10 UTC (permalink / raw)
To: Guodong Liu
Cc: Rob Herring, Matthias Brugger, Sean Wang, Sean Wang, linux-gpio,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
On Thu, Feb 10, 2022 at 7:21 AM Guodong Liu <guodong.liu@mediatek.com> wrote:
>
> 1. This patch adds pinctrl file for mt8186.
> 2. This patch adds mt8186 compatible node in binding document.
>
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
I see complaints from Rob's robot so please address these
or explain why they appear.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document
2022-02-10 6:21 ` [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document Guodong Liu
2022-02-10 14:47 ` Rob Herring
2022-02-11 0:10 ` Linus Walleij
@ 2022-02-11 12:28 ` Rob Herring
2022-02-14 3:04 ` Guodong Liu
2 siblings, 1 reply; 13+ messages in thread
From: Rob Herring @ 2022-02-11 12:28 UTC (permalink / raw)
To: Guodong Liu
Cc: Linus Walleij, Matthias Brugger, Sean Wang, Sean Wang,
linux-gpio, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group
On Thu, Feb 10, 2022 at 02:21:20PM +0800, Guodong Liu wrote:
> 1. This patch adds pinctrl file for mt8186.
> 2. This patch adds mt8186 compatible node in binding document.
>
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> ---
> .../bindings/pinctrl/pinctrl-mt8186.yaml | 313 +++++
> include/dt-bindings/pinctrl/mt8186-pinfunc.h | 1174 +++++++++++++++++
> 2 files changed, 1487 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
> create mode 100644 include/dt-bindings/pinctrl/mt8186-pinfunc.h
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
> new file mode 100644
> index 000000000000..54c9508af922
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
> @@ -0,0 +1,313 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek MT8186 Pin Controller
> +
> +maintainers:
> + - Sean Wang <sean.wang@mediatek.com>
> +
> +description: |
> + The Mediatek's Pin controller is used to control SoC pins.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8186-pinctrl
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + description: |
> + Number of cells in GPIO specifier. Since the generic GPIO binding is used,
> + the amount of cells must be specified as 2. See the below
> + mentioned gpio binding representation for description of particular cells.
> + const: 2
> +
> + gpio-ranges:
> + description: gpio valid number range.
Don't need generic descriptions for common properties
> + maxItems: 1
> +
> + reg:
> + description: |
> + Physical address base for gpio base registers. There are 8 different GPIO
> + physical address base in mt8186.
> + maxItems: 8
> +
> + reg-names:
> + description: |
> + Gpio base register names.
> + items:
> + - const: "iocfg0"
> + - const: "iocfg_bm"
> + - const: "iocfg_bl"
> + - const: "iocfg_br"
> + - const: "iocfg_lm"
> + - const: "iocfg_rb"
> + - const: "iocfg_tl"
> + - const: "eint"
Don't need quotes
> + maxItems: 8
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 2
> +
> + interrupts:
> + description: The interrupt outputs to sysirq.
Drop.
> + maxItems: 1
> +
> + mediatek,rsel-resistance-in-si-unit:
> + type: boolean
> + description: |
> + Identifying i2c pins pull up/down type which is RSEL. It can support
> + RSEL define or si unit value(ohm) to set different resistance.
> +
> +# PIN CONFIGURATION NODES
> +patternProperties:
> + '-pins$':
> + type: object
> + additionalProperties: false
> + patternProperties:
> + '^pins':
> + type: object
> + additionalProperties: false
> + description: |
> + A pinctrl node should contain at least one subnodes representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to muxer
> + configuration, pullups, drive strength, input enable/disable and
> + input schmitt.
> + An example of using macro:
> + pincontroller {
> + /* GPIO0 set as multifunction GPIO0 */
> + gpio-pins {
> + pins {
> + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
> + }
> + };
> + /* GPIO128 set as multifunction SDA0 */
> + i2c0-pins {
> + pins {
> + pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
> + }
> + };
> + };
> + $ref: "pinmux-node.yaml"
> +
> + properties:
> + pinmux:
> + description: |
> + Integer array, represents gpio pin number and mux setting.
> + Supported pin number and mux varies for different SoCs, and are
> + defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
> + directly.
> +
> + drive-strength:
> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> +
> + mediatek,drive-strength-adv:
> + description: |
> + Describe the specific driving setup property.
> + For I2C pins, the existing generic driving setup can only support
> + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
> + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
> + driving setup, the existing generic setup will be disabled.
> + The specific driving setup is controlled by E1E0EN.
> + When E1=0/E0=0, the strength is 0.125mA.
> + When E1=0/E0=1, the strength is 0.25mA.
> + When E1=1/E0=0, the strength is 0.5mA.
> + When E1=1/E0=1, the strength is 1mA.
> + EN is used to enable or disable the specific driving setup.
> + Valid arguments are described as below:
> + 0: (E1, E0, EN) = (0, 0, 0)
> + 1: (E1, E0, EN) = (0, 0, 1)
> + 2: (E1, E0, EN) = (0, 1, 0)
> + 3: (E1, E0, EN) = (0, 1, 1)
> + 4: (E1, E0, EN) = (1, 0, 0)
> + 5: (E1, E0, EN) = (1, 0, 1)
> + 6: (E1, E0, EN) = (1, 1, 0)
> + 7: (E1, E0, EN) = (1, 1, 1)
> + So the valid arguments are from 0 to 7.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2, 3, 4, 5, 6, 7]
> +
> + bias-pull-down:
> + oneOf:
> + - enum: [100, 101, 102, 103]
> + - description: mt8186 pull down PUPD/R0/R1 type define value.
> + - enum: [200, 201, 202, 203, 204, 205, 206, 207]
> + - description: mt8186 pull down RSEL type define value.
> + - enum: [75000, 5000]
> + - description: mt8186 pull down RSEL type si unit value(ohm).
This should fail validation. All the description entries are True, so
oneOf will be False. Drop the '-' on description so the enum and
description are 1 entry.
> +
> + description: |
> + For pull down type is normal, it don't need add RSEL & R1R0 define
> + and resistance value.
> + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
> + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
> + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
> + "MTK_PUPD_SET_R1R0_11" define in mt8186.
> + For pull down type is RSEL, it can add RSEL define & resistance
> + value(ohm) to set different resistance by identifying property
> + "mediatek,rsel-resistance-in-si-unit".
> + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
> + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
> + & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
> + & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
> + define in mt8186. It can also support resistance value(ohm)
> + "75000" & "5000" in mt8186.
> + An example of using RSEL define:
Perhaps move this to the example.
> + pincontroller {
> + i2c0_pin {
> + pins {
> + pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
> + bias-pull-down = <MTK_PULL_SET_RSEL_001>;
> + }
> + };
> + };
> + An example of using si unit resistance value(ohm):
> + &pio {
> + mediatek,rsel-resistance-in-si-unit;
> + }
> + pincontroller {
> + i2c0_pin {
> + pins {
> + pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
> + bias-pull-down = <75000>;
> + }
> + };
> + };
> +
> + bias-pull-up:
> + oneOf:
> + - enum: [100, 101, 102, 103]
> + - description: mt8186 pull up PUPD/R0/R1 type define value.
> + - enum: [200, 201, 202, 203, 204, 205, 206, 207]
> + - description: mt8186 pull up RSEL type define value.
> + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
> + - description: mt8186 pull up RSEL type si unit value(ohm).
> +
> + description: |
> + For pull up type is normal, it don't need add RSEL & R1R0 define
> + and resistance value.
> + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
> + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
> + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
> + "MTK_PUPD_SET_R1R0_11" define in mt8186.
> + For pull up type is RSEL, it can add RSEL define & resistance
> + value(ohm) to set different resistance by identifying property
> + "mediatek,rsel-resistance-in-si-unit".
> + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
> + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
> + & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
> + & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
> + define in mt8186. It can also support resistance value(ohm)
> + "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" &
> + "75000" in mt8186.
> + An example of using RSEL define:
> + pincontroller {
> + i2c0-pins {
> + pins {
> + pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
> + bias-pull-up = <MTK_PULL_SET_RSEL_001>;
> + }
> + };
> + };
> + An example of using si unit resistance value(ohm):
> + &pio {
> + mediatek,rsel-resistance-in-si-unit;
> + }
> + pincontroller {
> + i2c0-pins {
> + pins {
> + pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
> + bias-pull-up = <1000>;
> + }
> + };
> + };
> +
> + bias-disable: true
> +
> + output-high: true
> +
> + output-low: true
> +
> + input-enable: true
> +
> + input-disable: true
> +
> + input-schmitt-enable: true
> +
> + input-schmitt-disable: true
> +
> + required:
> + - pinmux
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-controller
> + - '#interrupt-cells'
> + - gpio-controller
> + - '#gpio-cells'
> + - gpio-ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + pio: pinctrl@10005000 {
> + compatible = "mediatek,mt8186-pinctrl";
> + reg = <0x10005000 0x1000>,
> + <0x10002000 0x0200>,
> + <0x10002200 0x0200>,
> + <0x10002400 0x0200>,
> + <0x10002600 0x0200>,
> + <0x10002A00 0x0200>,
> + <0x10002c00 0x0200>,
> + <0x1000b000 0x1000>;
> + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
> + "iocfg_br", "iocfg_lm", "iocfg_rb",
> + "iocfg_tl", "eint";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pio 0 0 185>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
> + #interrupt-cells = <2>;
> +
> + pio-pins {
> + pins {
> + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
> + output-low;
> + };
> + };
> +
> + spi0-pins {
> + pins-spi {
> + pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>,
> + <PINMUX_GPIO1__FUNC_SPI0_CSB_B>,
> + <PINMUX_GPIO2__FUNC_SPI0_MO_B>;
> + bias-disable;
> + };
> + pins-spi-mi {
> + pinmux = <PINMUX_GPIO3__FUNC_SPI0_MI_B>;
> + bias-pull-down;
> + };
> + };
> +
> + i2c0-pins {
> + pins {
> + pinmux = <PINMUX_GPIO127__FUNC_SCL0>,
> + <PINMUX_GPIO128__FUNC_SDA0>;
> + bias-disable;
> + mediatek,drive-strength-adv = <7>;
> + };
> + };
> + };
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186
2022-02-10 8:57 ` AngeloGioacchino Del Regno
@ 2022-02-14 3:02 ` Guodong Liu
0 siblings, 0 replies; 13+ messages in thread
From: Guodong Liu @ 2022-02-14 3:02 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Linus Walleij, Rob Herring,
Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
-----Original Message-----
From: AngeloGioacchino Del Regno <
angelogioacchino.delregno@collabora.com>
To: Guodong Liu <guodong.liu@mediatek.com>, Linus Walleij <
linus.walleij@linaro.org>, Rob Herring <robh+dt@kernel.org>, Matthias
Brugger <matthias.bgg@gmail.com>, Sean Wang <sean.wang@kernel.org>
Cc: Sean Wang <sean.wang@mediatek.com>, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186
Date: Thu, 10 Feb 2022 09:57:03 +0100
Il 10/02/22 07:21, Guodong Liu ha scritto:
> This commit includes pinctrl driver for mt8186.
>
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> ---
> drivers/pinctrl/mediatek/Kconfig | 7 +
> drivers/pinctrl/mediatek/Makefile | 1 +
> drivers/pinctrl/mediatek/pinctrl-mt8186.c | 1313 ++++++++++
> drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h | 2186
> +++++++++++++++++
> 4 files changed, 3507 insertions(+)
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8186.c
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
>
> diff --git a/drivers/pinctrl/mediatek/Kconfig
> b/drivers/pinctrl/mediatek/Kconfig
> index 66db4ac5d169..8dca1ef04965 100644
> --- a/drivers/pinctrl/mediatek/Kconfig
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -147,6 +147,13 @@ config PINCTRL_MT8183
> default ARM64 && ARCH_MEDIATEK
> select PINCTRL_MTK_PARIS
>
> +config PINCTRL_MT8186
> + bool "Mediatek MT8186 pin control"
> + depends on OF
> + depends on ARM64 || COMPILE_TEST
> + default ARM64 && ARCH_MEDIATEK
> + select PINCTRL_MTK_PARIS
> +
> config PINCTRL_MT8192
> bool "Mediatek MT8192 pin control"
> depends on OF
> diff --git a/drivers/pinctrl/mediatek/Makefile
> b/drivers/pinctrl/mediatek/Makefile
> index 90f43bb9d9a7..31c3784c6089 100644
> --- a/drivers/pinctrl/mediatek/Makefile
> +++ b/drivers/pinctrl/mediatek/Makefile
> @@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-
> mt7986.o
> obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
> obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
> obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
> +obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
> obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
> obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
> obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8186.c
> b/drivers/pinctrl/mediatek/pinctrl-mt8186.c
> new file mode 100644
> index 000000000000..1e550b15b9d4
> --- /dev/null
> +++ b/drivers/pinctrl/mediatek/pinctrl-mt8186.c
> @@ -0,0 +1,1313 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + *
> + * Author: Guodong Liu <guodong.liu@mediatek.com>
> + *
> + */
> +
> +#include "pinctrl-mtk-mt8186.h"
> +#include "pinctrl-paris.h"
> +
> +/* MT8186 have multiple bases to program pin configuration listed as
> the below:
> + * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
> + * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
> + * iocfg[6]:0x10002C00.
> + * _i_based could be used to indicate what base the pin should be
> mapped into.
> + */
> +
> +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit,
> x_bits) \
> + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit,
> x_bits, \
> + 32, 0)
Please don't break this line: 84 columns is fine.
Hi Angelo
we will update it for next version.
Thanks
Guodong
> +
> +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs,
> s_bit, x_bits) \
> + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit,
> x_bits, \
> + 32, 1)
Same here.
Hi Angelo
we will update it for next version.
Thanks
Guodong
And with that fixed,
Reviewed-by: AngeloGioacchino Del Regno <
angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 3/3] pinctrl: canonical rsel resistance selection property
2022-02-10 8:50 ` AngeloGioacchino Del Regno
@ 2022-02-14 3:03 ` Guodong Liu
0 siblings, 0 replies; 13+ messages in thread
From: Guodong Liu @ 2022-02-14 3:03 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Linus Walleij, Rob Herring,
Matthias Brugger, Sean Wang
Cc: Sean Wang, linux-gpio, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group
-----Original Message-----
From: AngeloGioacchino Del Regno <
angelogioacchino.delregno@collabora.com>
To: Guodong Liu <guodong.liu@mediatek.com>, Linus Walleij <
linus.walleij@linaro.org>, Rob Herring <robh+dt@kernel.org>, Matthias
Brugger <matthias.bgg@gmail.com>, Sean Wang <sean.wang@kernel.org>
Cc: Sean Wang <sean.wang@mediatek.com>, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v3 3/3] pinctrl: canonical rsel resistance
selection property
Date: Thu, 10 Feb 2022 09:50:45 +0100
Il 10/02/22 07:21, Guodong Liu ha scritto:
> Change "mediatek,rsel_resistance_in_si_unit" to "mediatek,rsel-
> resistance-in-si-unit"
>
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Hello Guodong,
thanks for the patch!
However, you forgot to add the required Fixes tag to this one; this
patch
should be fixing fb34a9ae383a ("pinctrl: mediatek: support rsel
feature").
Please add the required tag.
Thanks,
Angelo
Hi Angelo
We will update it for next version.
Thanks
Guodong
> ---
> drivers/pinctrl/mediatek/pinctrl-paris.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c
> b/drivers/pinctrl/mediatek/pinctrl-paris.c
> index d4e02c5d74a8..38c0f0c4cf95 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-paris.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
> @@ -989,7 +989,7 @@ int mtk_paris_pinctrl_probe(struct
> platform_device *pdev,
> hw->nbase = hw->soc->nbase_names;
>
> if (of_find_property(hw->dev->of_node,
> - "mediatek,rsel_resistance_in_si_unit",
> NULL))
> + "mediatek,rsel-resistance-in-si-unit",
> NULL))
> hw->rsel_si_unit = true;
> else
> hw->rsel_si_unit = false;
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document
2022-02-10 14:47 ` Rob Herring
@ 2022-02-14 3:03 ` Guodong Liu
0 siblings, 0 replies; 13+ messages in thread
From: Guodong Liu @ 2022-02-14 3:03 UTC (permalink / raw)
To: Rob Herring
Cc: Linus Walleij, Sean Wang, linux-mediatek, Rob Herring,
linux-arm-kernel, linux-kernel,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
linux-gpio, Sean Wang, devicetree
-----Original Message-----
From: Rob Herring <robh@kernel.org>
To: Guodong Liu <guodong.liu@mediatek.com>
Cc: Linus Walleij <linus.walleij@linaro.org>, Sean Wang <
sean.wang@mediatek.com>, linux-mediatek@lists.infradead.org, Rob
Herring <robh+dt@kernel.org>, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Project_Global_Chrome_Upstream_Group@mediatek.com, Matthias Brugger <
matthias.bgg@gmail.com>, linux-gpio@vger.kernel.org, Sean Wang <
sean.wang@kernel.org>, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl
file and binding document
Date: Thu, 10 Feb 2022 08:47:52 -0600
On Thu, 10 Feb 2022 14:21:20 +0800, Guodong Liu wrote:
> 1. This patch adds pinctrl file for mt8186.
> 2. This patch adds mt8186 compatible node in binding document.
>
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> ---
> .../bindings/pinctrl/pinctrl-mt8186.yaml | 313 +++++
> include/dt-bindings/pinctrl/mt8186-pinfunc.h | 1174
> +++++++++++++++++
> 2 files changed, 1487 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
> create mode 100644 include/dt-bindings/pinctrl/mt8186-pinfunc.h
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-
review/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml:
properties:reg-names: {'description': 'Gpio base register names.\n',
'items': [{'const': 'iocfg0'}, {'const': 'iocfg_bm'}, {'const':
'iocfg_bl'}, {'const': 'iocfg_br'}, {'const': 'iocfg_lm'}, {'const':
'iocfg_rb'}, {'const': 'iocfg_tl'}, {'const': 'eint'}], 'maxItems': 8}
should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-
review/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml:
ignoring, error in schema: properties: reg-names
Documentation/devicetree/bindings/pinctrl/pinctrl-
mt8186.example.dt.yaml:0:0: /example-0/pinctrl@10005000: failed to
match any schema with compatible: ['mediatek,mt8186-pinctrl']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1590838
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
Hi Rob
Thank you fou your useful information, and we will update it for next
version.
Thanks
Guodong
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document
2022-02-11 12:28 ` Rob Herring
@ 2022-02-14 3:04 ` Guodong Liu
0 siblings, 0 replies; 13+ messages in thread
From: Guodong Liu @ 2022-02-14 3:04 UTC (permalink / raw)
To: Rob Herring
Cc: Linus Walleij, Matthias Brugger, Sean Wang, Sean Wang,
linux-gpio, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group
-----Original Message-----
From: Rob Herring <robh@kernel.org>
To: Guodong Liu <guodong.liu@mediatek.com>
Cc: Linus Walleij <linus.walleij@linaro.org>, Matthias Brugger <
matthias.bgg@gmail.com>, Sean Wang <sean.wang@kernel.org>, Sean Wang <
sean.wang@mediatek.com>, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl
file and binding document
Date: Fri, 11 Feb 2022 06:28:51 -0600
On Thu, Feb 10, 2022 at 02:21:20PM +0800, Guodong Liu wrote:
> 1. This patch adds pinctrl file for mt8186.
> 2. This patch adds mt8186 compatible node in binding document.
>
> Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
> ---
> .../bindings/pinctrl/pinctrl-mt8186.yaml | 313 +++++
> include/dt-bindings/pinctrl/mt8186-pinfunc.h | 1174
> +++++++++++++++++
> 2 files changed, 1487 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
> create mode 100644 include/dt-bindings/pinctrl/mt8186-pinfunc.h
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-
> mt8186.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-
> mt8186.yaml
> new file mode 100644
> index 000000000000..54c9508af922
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
> @@ -0,0 +1,313 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek MT8186 Pin Controller
> +
> +maintainers:
> + - Sean Wang <sean.wang@mediatek.com>
> +
> +description: |
> + The Mediatek's Pin controller is used to control SoC pins.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8186-pinctrl
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + description: |
> + Number of cells in GPIO specifier. Since the generic GPIO
> binding is used,
> + the amount of cells must be specified as 2. See the below
> + mentioned gpio binding representation for description of
> particular cells.
> + const: 2
> +
> + gpio-ranges:
> + description: gpio valid number range.
Don't need generic descriptions for common properties
Hi Rob
we will update it for next version.
Thanks
Guodong
> + maxItems: 1
> +
> + reg:
> + description: |
> + Physical address base for gpio base registers. There are 8
> different GPIO
> + physical address base in mt8186.
> + maxItems: 8
> +
> + reg-names:
> + description: |
> + Gpio base register names.
> + items:
> + - const: "iocfg0"
> + - const: "iocfg_bm"
> + - const: "iocfg_bl"
> + - const: "iocfg_br"
> + - const: "iocfg_lm"
> + - const: "iocfg_rb"
> + - const: "iocfg_tl"
> + - const: "eint"
Don't need quotes
Hi Rob
We will update it for next version.
Thanks
Guodong
> + maxItems: 8
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 2
> +
> + interrupts:
> + description: The interrupt outputs to sysirq.
Drop.
Hi Rob
We will update it for next version.
Thanks
Guodong
> + maxItems: 1
> +
> + mediatek,rsel-resistance-in-si-unit:
> + type: boolean
> + description: |
> + Identifying i2c pins pull up/down type which is RSEL. It can
> support
> + RSEL define or si unit value(ohm) to set different resistance.
> +
> +# PIN CONFIGURATION NODES
> +patternProperties:
> + '-pins$':
> + type: object
> + additionalProperties: false
> + patternProperties:
> + '^pins':
> + type: object
> + additionalProperties: false
> + description: |
> + A pinctrl node should contain at least one subnodes
> representing the
> + pinctrl groups available on the machine. Each subnode will
> list the
> + pins it needs, and how they should be configured, with
> regard to muxer
> + configuration, pullups, drive strength, input
> enable/disable and
> + input schmitt.
> + An example of using macro:
> + pincontroller {
> + /* GPIO0 set as multifunction GPIO0 */
> + gpio-pins {
> + pins {
> + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
> + }
> + };
> + /* GPIO128 set as multifunction SDA0 */
> + i2c0-pins {
> + pins {
> + pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
> + }
> + };
> + };
> + $ref: "pinmux-node.yaml"
> +
> + properties:
> + pinmux:
> + description: |
> + Integer array, represents gpio pin number and mux
> setting.
> + Supported pin number and mux varies for different
> SoCs, and are
> + defined as macros in dt-bindings/pinctrl/<soc>-
> pinfunc.h
> + directly.
> +
> + drive-strength:
> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> +
> + mediatek,drive-strength-adv:
> + description: |
> + Describe the specific driving setup property.
> + For I2C pins, the existing generic driving setup can
> only support
> + 2/4/6/8/10/12/14/16mA driving. But in specific driving
> setup, they
> + can support 0.125/0.25/0.5/1mA adjustment. If we
> enable specific
> + driving setup, the existing generic setup will be
> disabled.
> + The specific driving setup is controlled by E1E0EN.
> + When E1=0/E0=0, the strength is 0.125mA.
> + When E1=0/E0=1, the strength is 0.25mA.
> + When E1=1/E0=0, the strength is 0.5mA.
> + When E1=1/E0=1, the strength is 1mA.
> + EN is used to enable or disable the specific driving
> setup.
> + Valid arguments are described as below:
> + 0: (E1, E0, EN) = (0, 0, 0)
> + 1: (E1, E0, EN) = (0, 0, 1)
> + 2: (E1, E0, EN) = (0, 1, 0)
> + 3: (E1, E0, EN) = (0, 1, 1)
> + 4: (E1, E0, EN) = (1, 0, 0)
> + 5: (E1, E0, EN) = (1, 0, 1)
> + 6: (E1, E0, EN) = (1, 1, 0)
> + 7: (E1, E0, EN) = (1, 1, 1)
> + So the valid arguments are from 0 to 7.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2, 3, 4, 5, 6, 7]
> +
> + bias-pull-down:
> + oneOf:
> + - enum: [100, 101, 102, 103]
> + - description: mt8186 pull down PUPD/R0/R1 type define
> value.
> + - enum: [200, 201, 202, 203, 204, 205, 206, 207]
> + - description: mt8186 pull down RSEL type define
> value.
> + - enum: [75000, 5000]
> + - description: mt8186 pull down RSEL type si unit
> value(ohm).
This should fail validation. All the description entries are True, so
oneOf will be False. Drop the '-' on description so the enum and
description are 1 entry.
Hi Rob
We will update it for next version.
Thanks
Guodong
> +
> + description: |
> + For pull down type is normal, it don't need add RSEL &
> R1R0 define
> + and resistance value.
> + For pull down type is PUPD/R0/R1 type, it can add R1R0
> define to
> + set different resistance. It can support
> "MTK_PUPD_SET_R1R0_00" &
> + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
> + "MTK_PUPD_SET_R1R0_11" define in mt8186.
> + For pull down type is RSEL, it can add RSEL define &
> resistance
> + value(ohm) to set different resistance by identifying
> property
> + "mediatek,rsel-resistance-in-si-unit".
> + It can support "MTK_PULL_SET_RSEL_000" &
> "MTK_PULL_SET_RSEL_001"
> + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
> + & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
> + & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
> + define in mt8186. It can also support resistance
> value(ohm)
> + "75000" & "5000" in mt8186.
> + An example of using RSEL define:
Perhaps move this to the example.
Hi Rob
Typically, I2C will config this type of pins as : "bias-pull-up =
<MTK_PULL_SET_RSEL_001>;", so we just move partial "bias-pull-up"
description info to the example, and we will update it for next
version.
Thanks
Guodong
> + pincontroller {
> + i2c0_pin {
> + pins {
> + pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
> + bias-pull-down = <MTK_PULL_SET_RSEL_001>;
> + }
> + };
> + };
> + An example of using si unit resistance value(ohm):
> + &pio {
> + mediatek,rsel-resistance-in-si-unit;
> + }
> + pincontroller {
> + i2c0_pin {
> + pins {
> + pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
> + bias-pull-down = <75000>;
> + }
> + };
> + };
> +
> + bias-pull-up:
> + oneOf:
> + - enum: [100, 101, 102, 103]
> + - description: mt8186 pull up PUPD/R0/R1 type define
> value.
> + - enum: [200, 201, 202, 203, 204, 205, 206, 207]
> + - description: mt8186 pull up RSEL type define value.
> + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000,
> 75000]
> + - description: mt8186 pull up RSEL type si unit
> value(ohm).
> +
> + description: |
> + For pull up type is normal, it don't need add RSEL &
> R1R0 define
> + and resistance value.
> + For pull up type is PUPD/R0/R1 type, it can add R1R0
> define to
> + set different resistance. It can support
> "MTK_PUPD_SET_R1R0_00" &
> + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
> + "MTK_PUPD_SET_R1R0_11" define in mt8186.
> + For pull up type is RSEL, it can add RSEL define &
> resistance
> + value(ohm) to set different resistance by identifying
> property
> + "mediatek,rsel-resistance-in-si-unit".
> + It can support "MTK_PULL_SET_RSEL_000" &
> "MTK_PULL_SET_RSEL_001"
> + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
> + & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
> + & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
> + define in mt8186. It can also support resistance
> value(ohm)
> + "1000" & "1500" & "2000" & "3000" & "4000" & "5000" &
> "10000" &
> + "75000" in mt8186.
> + An example of using RSEL define:
> + pincontroller {
> + i2c0-pins {
> + pins {
> + pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
> + bias-pull-up = <MTK_PULL_SET_RSEL_001>;
> + }
> + };
> + };
> + An example of using si unit resistance value(ohm):
> + &pio {
> + mediatek,rsel-resistance-in-si-unit;
> + }
> + pincontroller {
> + i2c0-pins {
> + pins {
> + pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
> + bias-pull-up = <1000>;
> + }
> + };
> + };
> +
> + bias-disable: true
> +
> + output-high: true
> +
> + output-low: true
> +
> + input-enable: true
> +
> + input-disable: true
> +
> + input-schmitt-enable: true
> +
> + input-schmitt-disable: true
> +
> + required:
> + - pinmux
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-controller
> + - '#interrupt-cells'
> + - gpio-controller
> + - '#gpio-cells'
> + - gpio-ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + pio: pinctrl@10005000 {
> + compatible = "mediatek,mt8186-pinctrl";
> + reg = <0x10005000 0x1000>,
> + <0x10002000 0x0200>,
> + <0x10002200 0x0200>,
> + <0x10002400 0x0200>,
> + <0x10002600 0x0200>,
> + <0x10002A00 0x0200>,
> + <0x10002c00 0x0200>,
> + <0x1000b000 0x1000>;
> + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
> + "iocfg_br", "iocfg_lm", "iocfg_rb",
> + "iocfg_tl", "eint";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pio 0 0 185>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
> + #interrupt-cells = <2>;
> +
> + pio-pins {
> + pins {
> + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
> + output-low;
> + };
> + };
> +
> + spi0-pins {
> + pins-spi {
> + pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>,
> + <PINMUX_GPIO1__FUNC_SPI0_CSB_B>,
> + <PINMUX_GPIO2__FUNC_SPI0_MO_B>;
> + bias-disable;
> + };
> + pins-spi-mi {
> + pinmux = <PINMUX_GPIO3__FUNC_SPI0_MI_B>;
> + bias-pull-down;
> + };
> + };
> +
> + i2c0-pins {
> + pins {
> + pinmux = <PINMUX_GPIO127__FUNC_SCL0>,
> + <PINMUX_GPIO128__FUNC_SDA0>;
> + bias-disable;
> + mediatek,drive-strength-adv = <7>;
> + };
> + };
> + };
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-02-14 3:04 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-10 6:21 [PATCH v3 0/2] pinctrl: mediatek: Support pinctrl driver on mt8186 Guodong Liu
2022-02-10 6:21 ` [PATCH v3 1/3] dt-bindings: pinctrl: mt8186: add pinctrl file and binding document Guodong Liu
2022-02-10 14:47 ` Rob Herring
2022-02-14 3:03 ` Guodong Liu
2022-02-11 0:10 ` Linus Walleij
2022-02-11 12:28 ` Rob Herring
2022-02-14 3:04 ` Guodong Liu
2022-02-10 6:21 ` [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186 Guodong Liu
2022-02-10 8:57 ` AngeloGioacchino Del Regno
2022-02-14 3:02 ` Guodong Liu
2022-02-10 6:21 ` [PATCH v3 3/3] pinctrl: canonical rsel resistance selection property Guodong Liu
2022-02-10 8:50 ` AngeloGioacchino Del Regno
2022-02-14 3:03 ` Guodong Liu
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