From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Kishon Vijay Abraham I" <kishon@ti.com>,
"Xiaowei Bao" <xiaowei.bao@nxp.com>,
"Om Prakash Singh" <omp@nvidia.com>,
"Vidya Sagar" <vidyas@nvidia.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] PCI: designware-ep: Fix the access to DBI/iATU registers before enabling controller
Date: Thu, 10 Feb 2022 16:34:46 +0530 [thread overview]
Message-ID: <20220210110446.GD69529@thinkpad> (raw)
In-Reply-To: <1630473361-27198-3-git-send-email-hayashi.kunihiko@socionext.com>
On Wed, Sep 01, 2021 at 02:16:01PM +0900, Kunihiko Hayashi wrote:
> The driver using core_init_notifier, e.g. pcie-tegra194.c, runs according
> to the following sequence:
>
> probe()
> dw_pcie_ep_init()
>
> bind()
> dw_pcie_ep_start()
> enable_irq()
>
> (interrupt occurred)
> handler()
> [enable controller]
> dw_pcie_ep_init_complete()
> dw_pcie_ep_init_notify()
>
> After receiving an interrupt from RC, the handler enables the controller
> and the controller registers can be accessed.
> So accessing the registers should do in dw_pcie_ep_init_complete().
>
> Currently dw_pcie_ep_init() has functions dw_iatu_detect() and
> dw_pcie_ep_find_capability() that include accesses to DWC registers.
> As a result, accessing the registers before enabling the controller,
> the access will fail.
>
> The function dw_pcie_ep_init() shouldn't have any access to DWC registers
> if the controller is enabled after calling bind(). This moves access codes
> to DBI/iATU registers and depending variables from dw_pcie_ep_init() to
> dw_pcie_ep_init_complete().
>
> Cc: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: Vidya Sagar <vidyas@nvidia.com>
> Fixes: 6bfc9c3a2c70 ("PCI: designware-ep: Move the function of getting MSI capability forward")
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Acked-by: Om Prakash Singh <omp@nvidia.com>
> Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 81 +++++++++++++------------
> 1 file changed, 41 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 998b698..00ce83c 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
[...]
> int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> {
> int ret;
> - void *addr;
> - u8 func_no;
> struct resource *res;
> struct pci_epc *epc;
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> @@ -683,7 +721,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> struct platform_device *pdev = to_platform_device(dev);
> struct device_node *np = dev->of_node;
> const struct pci_epc_features *epc_features;
> - struct dw_pcie_ep_func *ep_func;
>
> INIT_LIST_HEAD(&ep->func_list);
>
> @@ -705,8 +742,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> }
> }
>
> - dw_pcie_iatu_detect(pci);
> -
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
> if (!res)
> return -EINVAL;
> @@ -714,26 +749,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> ep->phys_base = res->start;
> ep->addr_size = resource_size(res);
>
> - ep->ib_window_map = devm_kcalloc(dev,
> - BITS_TO_LONGS(pci->num_ib_windows),
> - sizeof(long),
> - GFP_KERNEL);
> - if (!ep->ib_window_map)
> - return -ENOMEM;
> -
> - ep->ob_window_map = devm_kcalloc(dev,
> - BITS_TO_LONGS(pci->num_ob_windows),
> - sizeof(long),
> - GFP_KERNEL);
> - if (!ep->ob_window_map)
> - return -ENOMEM;
> -
> - addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
> - GFP_KERNEL);
> - if (!addr)
> - return -ENOMEM;
> - ep->outbound_addr = addr;
> -
> if (pci->link_gen < 1)
> pci->link_gen = of_pci_get_max_link_speed(np);
>
> @@ -750,20 +765,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> if (ret < 0)
> epc->max_functions = 1;
>
> - for (func_no = 0; func_no < epc->max_functions; func_no++) {
> - ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
> - if (!ep_func)
> - return -ENOMEM;
> -
> - ep_func->func_no = func_no;
> - ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no,
> - PCI_CAP_ID_MSI);
> - ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no,
> - PCI_CAP_ID_MSIX);
> -
> - list_add_tail(&ep_func->list, &ep->func_list);
> - }
> -
> if (ep->ops->ep_init)
> ep->ops->ep_init(ep);
You also need to move ep_init() as it can have DBI access too.
Thanks,
Mani
>
> --
> 2.7.4
>
next prev parent reply other threads:[~2022-02-10 11:04 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-01 5:15 [PATCH v2 0/2] PCI: endpoint: Fix core_init_notifier feature Kunihiko Hayashi
2021-09-01 5:16 ` [PATCH v2 1/2] PCI: endpoint: pci-epf-test: register notifier if only core_init_notifier is enabled Kunihiko Hayashi
2021-12-03 4:35 ` Kishon Vijay Abraham I
2021-09-01 5:16 ` [PATCH v2 2/2] PCI: designware-ep: Fix the access to DBI/iATU registers before enabling controller Kunihiko Hayashi
2021-12-03 5:06 ` Kishon Vijay Abraham I
2021-12-06 11:23 ` Lorenzo Pieralisi
2022-01-05 10:43 ` Kunihiko Hayashi
2022-01-05 15:46 ` Manivannan Sadhasivam
2022-02-10 11:02 ` Manivannan Sadhasivam
2022-02-10 11:04 ` Manivannan Sadhasivam [this message]
2021-09-16 11:30 ` [PATCH v2 0/2] PCI: endpoint: Fix core_init_notifier feature Kunihiko Hayashi
2021-12-01 15:04 ` Lorenzo Pieralisi
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