From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Kishon Vijay Abraham I <kishon@ti.com>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Xiaowei Bao" <xiaowei.bao@nxp.com>,
"Om Prakash Singh" <omp@nvidia.com>,
"Vidya Sagar" <vidyas@nvidia.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] PCI: designware-ep: Fix the access to DBI/iATU registers before enabling controller
Date: Wed, 5 Jan 2022 19:43:04 +0900 [thread overview]
Message-ID: <f4037b9c-9957-8d4c-d2e0-63bb53d5e7ee@socionext.com> (raw)
In-Reply-To: <20211206112335.GA18520@lpieralisi>
Hi Kishon, Lorenzo,
Thank you and sorry for late reply.
On 2021/12/06 20:23, Lorenzo Pieralisi wrote:
> On Fri, Dec 03, 2021 at 10:36:00AM +0530, Kishon Vijay Abraham I wrote:
>> Hi Kunihiko,
>>
>> On 01/09/21 10:46 am, Kunihiko Hayashi wrote:
>>> The driver using core_init_notifier, e.g. pcie-tegra194.c, runs
> according
>>> to the following sequence:
>>>
>>> probe()
>>> dw_pcie_ep_init()
>>>
>>> bind()
>>> dw_pcie_ep_start()
>>> enable_irq()
>>>
>>> (interrupt occurred)
>>> handler()
>>> [enable controller]
>>> dw_pcie_ep_init_complete()
>>> dw_pcie_ep_init_notify()
>>>
>>> After receiving an interrupt from RC, the handler enables the
> controller
>>> and the controller registers can be accessed.
>>> So accessing the registers should do in dw_pcie_ep_init_complete().
>>>
>>> Currently dw_pcie_ep_init() has functions dw_iatu_detect() and
>>> dw_pcie_ep_find_capability() that include accesses to DWC registers.
>>> As a result, accessing the registers before enabling the controller,
>>> the access will fail.
>>>
>>> The function dw_pcie_ep_init() shouldn't have any access to DWC
> registers
>>> if the controller is enabled after calling bind(). This moves access
> codes
>>> to DBI/iATU registers and depending variables from dw_pcie_ep_init()
> to
>>> dw_pcie_ep_init_complete().
>>
>> Ideally pci_epc_create() should be the last step by the controller
>> driver before handing the control to the core EPC framework. Since
>> after this step the EPC framework can start invoking the epc_ops.
>>
>> Here more stuff is being added to dw_pcie_ep_init_complete() which is
>> required for epc_ops and this could result in aborts for platforms
>> which does not add core_init_notifier.
>
> This patch needs rework, I will mark the series as "Changes requested".
I understand that relocation of dwc register accesses isn't appropriate,
but I couldn't think of any other rework to dwc, and I confirmed
pcie-qcom-ep driver using core_init_notifier.
In pcie-qcom-ep driver, probe() enables clock and deasserts reset first,
and when PERST# interrupt arrives, the handler enables clock and deasserts
reset again. So, dw_pcie_ep_init() can access DBI registers.
In pcie-tegra194 driver, I think the issue will be solved if probe() also
handles clock and reset control. However, the driver has other register
access between core_clk, core_apb_rst, and core_rst controls.
I think that it's appropriate to leave this fix to the developer at this
point.
As this patch series, I'll resend 1/2 patch only and expect pcie-tegra194
driver to be fixed.
Thank you,
---
Best Regards
Kunihiko Hayashi
next prev parent reply other threads:[~2022-01-05 10:43 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-01 5:15 [PATCH v2 0/2] PCI: endpoint: Fix core_init_notifier feature Kunihiko Hayashi
2021-09-01 5:16 ` [PATCH v2 1/2] PCI: endpoint: pci-epf-test: register notifier if only core_init_notifier is enabled Kunihiko Hayashi
2021-12-03 4:35 ` Kishon Vijay Abraham I
2021-09-01 5:16 ` [PATCH v2 2/2] PCI: designware-ep: Fix the access to DBI/iATU registers before enabling controller Kunihiko Hayashi
2021-12-03 5:06 ` Kishon Vijay Abraham I
2021-12-06 11:23 ` Lorenzo Pieralisi
2022-01-05 10:43 ` Kunihiko Hayashi [this message]
2022-01-05 15:46 ` Manivannan Sadhasivam
2022-02-10 11:02 ` Manivannan Sadhasivam
2022-02-10 11:04 ` Manivannan Sadhasivam
2021-09-16 11:30 ` [PATCH v2 0/2] PCI: endpoint: Fix core_init_notifier feature Kunihiko Hayashi
2021-12-01 15:04 ` Lorenzo Pieralisi
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