From: <conor.dooley@microchip.com>
To: <linus.walleij@linaro.org>, <brgl@bgdev.pl>, <robh+dt@kernel.org>,
<jassisinghbrar@gmail.com>, <thierry.reding@gmail.com>,
<u.kleine-koenig@pengutronix.de>, <lee.jones@linaro.org>,
<a.zummo@towertech.it>, <alexandre.belloni@bootlin.com>,
<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <geert@linux-m68k.org>,
<krzysztof.kozlowski@canonical.com>, <linux-gpio@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-pwm@vger.kernel.org>, <linux-rtc@vger.kernel.org>,
<linux-riscv@lists.infradead.org>
Cc: <lewis.hanly@microchip.com>, <conor.dooley@microchip.com>,
<daire.mcnamara@microchip.com>, <ivan.griffin@microchip.com>,
<atishp@rivosinc.com>, Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH v7 08/11] riscv: dts: microchip: refactor icicle kit device tree
Date: Mon, 14 Feb 2022 13:58:38 +0000 [thread overview]
Message-ID: <20220214135840.168236-9-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com>
From: Conor Dooley <conor.dooley@microchip.com>
Assorted minor changes to the MPFS/Icicle kit device tree:
- rename serial to mmuart to match microchip documentation
- move phy0 inside mac1 node to match phy configuration
- add labels where missing (cpus, cache controller)
- add missing address cells & interrupts to MACs
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 37 ++++++-----
.../boot/dts/microchip/microchip-mpfs.dtsi | 65 +++++++++----------
2 files changed, 52 insertions(+), 50 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index ab803f71626a..c51bd7cf500f 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
@@ -13,11 +13,11 @@ / {
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
- ethernet0 = &emac1;
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
+ ethernet0 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
};
chosen {
@@ -39,19 +39,19 @@ &refclk {
clock-frequency = <600000000>;
};
-&serial0 {
+&mmuart0 {
status = "okay";
};
-&serial1 {
+&mmuart1 {
status = "okay";
};
-&serial2 {
+&mmuart2 {
status = "okay";
};
-&serial3 {
+&mmuart3 {
status = "okay";
};
@@ -61,7 +61,10 @@ &mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
+ cap-mmc-highspeed;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
@@ -72,22 +75,22 @@ &i2c2 {
status = "okay";
};
-&emac0 {
+&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
- phy0: ethernet-phy@8 {
- reg = <8>;
- ti,fifo-depth = <0x01>;
- };
};
-&emac1 {
+&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
- ti,fifo-depth = <0x01>;
+ ti,fifo-depth = <0x1>;
+ };
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ ti,fifo-depth = <0x1>;
};
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index c7d73756c9b8..62bd00092bcc 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
@@ -15,7 +15,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -33,7 +33,7 @@ cpu0_intc: interrupt-controller {
};
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -60,7 +60,7 @@ cpu1_intc: interrupt-controller {
};
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -87,7 +87,7 @@ cpu2_intc: interrupt-controller {
};
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -114,7 +114,7 @@ cpu3_intc: interrupt-controller {
};
};
- cpu@4 {
+ cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -152,8 +152,9 @@ soc {
compatible = "simple-bus";
ranges;
- cache-controller@2010000 {
+ cctrllr: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
+ reg = <0x0 0x2010000 0x0 0x1000>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
@@ -161,10 +162,9 @@ cache-controller@2010000 {
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1>, <2>, <3>;
- reg = <0x0 0x2010000 0x0 0x1000>;
};
- clint@2000000 {
+ clint: clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
@@ -174,6 +174,15 @@ clint@2000000 {
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
+ dma@3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>;
+ #dma-cells = <1>;
+ };
+
plic: interrupt-controller@c000000 {
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
@@ -188,15 +197,6 @@ plic: interrupt-controller@c000000 {
riscv,ndev = <186>;
};
- dma@3000000 {
- compatible = "sifive,fu540-c000-pdma";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic>;
- interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
- <30>;
- #dma-cells = <1>;
- };
-
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
@@ -204,7 +204,7 @@ clkcfg: clkcfg@20002000 {
#clock-cells = <1>;
};
- serial0: serial@20000000 {
+ mmuart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
@@ -216,7 +216,7 @@ serial0: serial@20000000 {
status = "disabled";
};
- serial1: serial@20100000 {
+ mmuart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
@@ -228,7 +228,7 @@ serial1: serial@20100000 {
status = "disabled";
};
- serial2: serial@20102000 {
+ mmuart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
@@ -240,7 +240,7 @@ serial2: serial@20102000 {
status = "disabled";
};
- serial3: serial@20104000 {
+ mmuart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
@@ -257,37 +257,36 @@ mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
- interrupts = <88>, <89>;
+ interrupts = <88>;
clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
- emac0: ethernet@20110000 {
+ mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupt-parent = <&plic>;
- interrupts = <64>, <65>, <66>, <67>;
+ interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
};
- emac1: ethernet@20112000 {
+ mac1: ethernet@20112000 {
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupt-parent = <&plic>;
- interrupts = <70>, <71>, <72>, <73>;
+ interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
- status = "disabled";
clock-names = "pclk", "hclk";
- #address-cells = <1>;
- #size-cells = <0>;
+ status = "disabled";
};
-
};
};
--
2.35.1
next prev parent reply other threads:[~2022-02-14 13:57 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-14 13:58 [PATCH v7 00/11] Update the Icicle Kit device tree conor.dooley
2022-02-14 13:58 ` [PATCH v7 01/11] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley
2022-02-14 13:58 ` [PATCH v7 02/11] dt-bindings: soc/microchip: add info about services to mpfs sysctrl conor.dooley
2022-02-21 7:40 ` Conor.Dooley
2022-02-22 21:39 ` Rob Herring
2022-02-14 13:58 ` [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley
2022-02-23 7:41 ` Conor.Dooley
2022-02-23 15:18 ` Alexandre Belloni
2022-02-23 15:25 ` Conor.Dooley
2022-02-23 20:20 ` Alexandre Belloni
2022-02-23 20:26 ` Conor Dooley
2022-02-14 13:58 ` [PATCH v7 04/11] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley
2022-02-14 13:58 ` [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding conor.dooley
2022-02-21 7:55 ` Conor.Dooley
2022-02-23 6:20 ` Uwe Kleine-König
2022-02-23 7:12 ` Krzysztof Kozlowski
2022-02-23 8:20 ` Uwe Kleine-König
2022-02-23 8:55 ` conor.dooley
2022-02-23 9:09 ` Lee Jones
2022-02-24 13:19 ` Thierry Reding
2022-02-14 13:58 ` [PATCH v7 06/11] riscv: dts: microchip: use clk defines for icicle kit conor.dooley
2022-02-14 13:58 ` [PATCH v7 07/11] riscv: dts: microchip: add fpga fabric section to " conor.dooley
2022-02-14 13:58 ` conor.dooley [this message]
2022-02-14 13:58 ` [PATCH v7 09/11] riscv: dts: microchip: update peripherals in icicle kit device tree conor.dooley
2022-02-14 13:58 ` [PATCH v7 10/11] riscv: dts: microchip: add new peripherals to " conor.dooley
2022-02-14 13:58 ` [PATCH v7 11/11] MAINTAINERS: update riscv/microchip entry conor.dooley
2022-02-23 20:48 ` [PATCH v7 00/11] Update the Icicle Kit device tree Conor Dooley
2022-03-10 7:07 ` Palmer Dabbelt
2022-03-10 7:35 ` Conor.Dooley
2022-03-11 7:59 ` Zong Li
2022-03-11 19:56 ` Conor Dooley
2022-03-16 6:51 ` Uwe Kleine-König
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