* [PATCH 1/3] ata: ahci: Rename board_ahci_mobile
@ 2022-02-16 2:59 Mario Limonciello
2022-02-16 2:59 ` [PATCH 2/3] ata: ahci: Rename `AHCI_HFLAG_IS_MOBILE` Mario Limonciello
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Mario Limonciello @ 2022-02-16 2:59 UTC (permalink / raw)
To: Damien Le Moal
Cc: open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, pmenzel, hdegoede, Mario Limonciello
This board definition was originally created for mobile devices to
designate default link power managmeent policy to influence runtime
power consumption.
As this is interesting for more than just mobile designs, rename the
board to `board_ahci_default_lpm` to make it clear it is about default
policy.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/ata/ahci.c | 96 +++++++++++++++++++++++-----------------------
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index ab5811ef5a53..67f3b3b23639 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -49,8 +49,8 @@ enum {
enum board_ids {
/* board IDs by feature in alphabetical order */
board_ahci,
+ board_ahci_default_lpm,
board_ahci_ign_iferr,
- board_ahci_mobile,
board_ahci_no_debounce_delay,
board_ahci_nomsi,
board_ahci_noncq,
@@ -135,7 +135,7 @@ static const struct ata_port_info ahci_port_info[] = {
.udma_mask = ATA_UDMA6,
.port_ops = &ahci_ops,
},
- [board_ahci_mobile] = {
+ [board_ahci_default_lpm] = {
AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
@@ -275,13 +275,13 @@ static const struct pci_device_id ahci_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
- { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
- { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
- { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
- { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
- { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
+ { PCI_VDEVICE(INTEL, 0x2929), board_ahci_default_lpm }, /* ICH9M */
+ { PCI_VDEVICE(INTEL, 0x292a), board_ahci_default_lpm }, /* ICH9M */
+ { PCI_VDEVICE(INTEL, 0x292b), board_ahci_default_lpm }, /* ICH9M */
+ { PCI_VDEVICE(INTEL, 0x292c), board_ahci_default_lpm }, /* ICH9M */
+ { PCI_VDEVICE(INTEL, 0x292f), board_ahci_default_lpm }, /* ICH9M */
{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
- { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
+ { PCI_VDEVICE(INTEL, 0x294e), board_ahci_default_lpm }, /* ICH9M */
{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
@@ -291,9 +291,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
- { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
+ { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_default_lpm }, /* PCH M AHCI */
{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
- { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
+ { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_default_lpm }, /* PCH M RAID */
{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
@@ -316,9 +316,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
- { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
+ { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_default_lpm }, /* CPT M AHCI */
{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
- { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
+ { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_default_lpm }, /* CPT M RAID */
{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
@@ -327,29 +327,29 @@ static const struct pci_device_id ahci_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG/Lewisburg RAID*/
{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
- { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
+ { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_default_lpm }, /* Panther M AHCI */
{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
- { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
+ { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_default_lpm }, /* Panther M RAID */
{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
- { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
+ { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_default_lpm }, /* Lynx M AHCI */
{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
- { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
+ { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_default_lpm }, /* Lynx M RAID */
{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
- { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
+ { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_default_lpm }, /* Lynx M RAID */
{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
- { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
- { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
- { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
- { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
- { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
- { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
- { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
- { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
- { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
- { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
+ { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_default_lpm }, /* Lynx M RAID */
+ { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_default_lpm }, /* Lynx LP AHCI */
+ { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_default_lpm }, /* Lynx LP AHCI */
+ { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_default_lpm }, /* Lynx LP RAID */
+ { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_default_lpm }, /* Lynx LP RAID */
+ { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_default_lpm }, /* Lynx LP RAID */
+ { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_default_lpm }, /* Lynx LP RAID */
+ { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_default_lpm }, /* Lynx LP RAID */
+ { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_default_lpm }, /* Lynx LP RAID */
+ { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_default_lpm }, /* Cannon Lake PCH-LP AHCI */
{ PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
{ PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
{ PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
@@ -381,26 +381,26 @@ static const struct pci_device_id ahci_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
{ PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
{ PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
- { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
- { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
- { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
- { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
+ { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_default_lpm }, /* Wildcat LP AHCI */
+ { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_default_lpm }, /* Wildcat LP RAID */
+ { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_default_lpm }, /* Wildcat LP RAID */
+ { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_default_lpm }, /* Wildcat LP RAID */
{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
- { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
+ { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_default_lpm }, /* 9 Series M AHCI */
{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
- { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
+ { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_default_lpm }, /* 9 Series M RAID */
{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
- { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
+ { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_default_lpm }, /* 9 Series M RAID */
{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
- { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
- { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
- { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
- { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
+ { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_default_lpm }, /* 9 Series M RAID */
+ { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_default_lpm }, /* Sunrise LP AHCI */
+ { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_default_lpm }, /* Sunrise LP RAID */
+ { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_default_lpm }, /* Sunrise LP RAID */
{ PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
- { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
+ { PCI_VDEVICE(INTEL, 0xa103), board_ahci_default_lpm }, /* Sunrise M AHCI */
{ PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
{ PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
- { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
+ { PCI_VDEVICE(INTEL, 0xa107), board_ahci_default_lpm }, /* Sunrise M RAID */
{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
{ PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
{ PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
@@ -413,13 +413,13 @@ static const struct pci_device_id ahci_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
{ PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
{ PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
- { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
- { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
- { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
- { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
- { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
- { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
- { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
+ { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_default_lpm }, /* Bay Trail AHCI */
+ { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_default_lpm }, /* Bay Trail AHCI */
+ { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_default_lpm }, /* Cherry Tr. AHCI */
+ { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_default_lpm }, /* ApolloLake AHCI */
+ { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_default_lpm }, /* Ice Lake LP AHCI */
+ { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_default_lpm }, /* Comet Lake PCH-U AHCI */
+ { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_default_lpm }, /* Comet Lake PCH RAID */
/* JMicron 360/1/3/5/6, match class to avoid IDE function */
{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
@@ -447,7 +447,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
{ PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
{ PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
- { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
+ { PCI_VDEVICE(AMD, 0x7901), board_ahci_default_lpm }, /* AMD Green Sardine */
/* AMD is using RAID class only for ahci controllers */
{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] ata: ahci: Rename `AHCI_HFLAG_IS_MOBILE`
2022-02-16 2:59 [PATCH 1/3] ata: ahci: Rename board_ahci_mobile Mario Limonciello
@ 2022-02-16 2:59 ` Mario Limonciello
2022-02-16 2:59 ` [PATCH 3/3] ata: ahci: Rename CONFIG_SATA_LPM_MOBILE_POLICY configuration item Mario Limonciello
2022-02-16 6:26 ` [PATCH 1/3] ata: ahci: Rename board_ahci_mobile Damien Le Moal
2 siblings, 0 replies; 7+ messages in thread
From: Mario Limonciello @ 2022-02-16 2:59 UTC (permalink / raw)
To: Damien Le Moal
Cc: open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, pmenzel, hdegoede, Mario Limonciello
`AHCI_HFLAG_IS_MOBILE` designates that a chipset should be using the
default link power management policy from a kernel configuration item.
As desktop chipsets may also be interested in this default policy
configuration, rename the flag to `AHCI_HFLAG_USE_LPM_POLICY` to more
accurately reflect that a chipset doesn't have to be mobile to adopt it.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/ata/ahci.c | 6 +++---
drivers/ata/ahci.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 67f3b3b23639..5be889de9b1e 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -136,7 +136,7 @@ static const struct ata_port_info ahci_port_info[] = {
.port_ops = &ahci_ops,
},
[board_ahci_default_lpm] = {
- AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
+ AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
@@ -1595,8 +1595,8 @@ static void ahci_update_initial_lpm_policy(struct ata_port *ap,
int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
- /* Ignore processing for non mobile platforms */
- if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
+ /* Ignore processing for chipsets that don't use policy */
+ if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
return;
/* user modified policy via module param */
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index eeac5482f1d1..1ad48e2fe573 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -235,7 +235,7 @@ enum {
AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */
AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
only registers */
- AHCI_HFLAG_IS_MOBILE = (1 << 25), /* mobile chipset, use
+ AHCI_HFLAG_USE_LPM_POLICY = (1 << 25), /* chipset that should use
SATA_MOBILE_LPM_POLICY
as default lpm_policy */
AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] ata: ahci: Rename CONFIG_SATA_LPM_MOBILE_POLICY configuration item
2022-02-16 2:59 [PATCH 1/3] ata: ahci: Rename board_ahci_mobile Mario Limonciello
2022-02-16 2:59 ` [PATCH 2/3] ata: ahci: Rename `AHCI_HFLAG_IS_MOBILE` Mario Limonciello
@ 2022-02-16 2:59 ` Mario Limonciello
2022-02-16 12:44 ` Hans de Goede
2022-02-16 6:26 ` [PATCH 1/3] ata: ahci: Rename board_ahci_mobile Damien Le Moal
2 siblings, 1 reply; 7+ messages in thread
From: Mario Limonciello @ 2022-02-16 2:59 UTC (permalink / raw)
To: Damien Le Moal
Cc: open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, pmenzel, hdegoede, Mario Limonciello
`CONFIG_SATA_LPM_MOBILE_POLICY` reflects a configuration to apply only to
mobile chipsets. As some desktop boards may want to use this policy by
default as well, rename the configuration item to `SATA_LPM_POLICY`.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/ata/Kconfig | 6 +++---
drivers/ata/ahci.c | 2 +-
drivers/ata/ahci.h | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index cb54631fd950..52c086f155f0 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -115,14 +115,14 @@ config SATA_AHCI
If unsure, say N.
-config SATA_MOBILE_LPM_POLICY
- int "Default SATA Link Power Management policy for mobile chipsets"
+config SATA_LPM_POLICY
+ int "Default SATA Link Power Management policy for supported chipsets"
range 0 4
default 0
depends on SATA_AHCI
help
Select the Default SATA Link Power Management (LPM) policy to use
- for mobile / laptop variants of chipsets / "South Bridges".
+ for certain chipsets / "South Bridges".
The value set has the following meanings:
0 => Keep firmware settings
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 5be889de9b1e..7a7fa1090bb0 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1592,7 +1592,7 @@ static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
static void ahci_update_initial_lpm_policy(struct ata_port *ap,
struct ahci_host_priv *hpriv)
{
- int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
+ int policy = CONFIG_SATA_LPM_POLICY;
/* Ignore processing for chipsets that don't use policy */
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 1ad48e2fe573..5badbaca05a0 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -236,7 +236,7 @@ enum {
AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
only registers */
AHCI_HFLAG_USE_LPM_POLICY = (1 << 25), /* chipset that should use
- SATA_MOBILE_LPM_POLICY
+ SATA_LPM_POLICY
as default lpm_policy */
AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
suspend/resume */
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] ata: ahci: Rename board_ahci_mobile
2022-02-16 2:59 [PATCH 1/3] ata: ahci: Rename board_ahci_mobile Mario Limonciello
2022-02-16 2:59 ` [PATCH 2/3] ata: ahci: Rename `AHCI_HFLAG_IS_MOBILE` Mario Limonciello
2022-02-16 2:59 ` [PATCH 3/3] ata: ahci: Rename CONFIG_SATA_LPM_MOBILE_POLICY configuration item Mario Limonciello
@ 2022-02-16 6:26 ` Damien Le Moal
2022-02-16 6:28 ` Limonciello, Mario
2 siblings, 1 reply; 7+ messages in thread
From: Damien Le Moal @ 2022-02-16 6:26 UTC (permalink / raw)
To: Mario Limonciello
Cc: open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, pmenzel, hdegoede
On 2/16/22 11:59, Mario Limonciello wrote:
> This board definition was originally created for mobile devices to
> designate default link power managmeent policy to influence runtime
> power consumption.
>
> As this is interesting for more than just mobile designs, rename the
> board to `board_ahci_default_lpm` to make it clear it is about default
> policy.
>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> drivers/ata/ahci.c | 96 +++++++++++++++++++++++-----------------------
> 1 file changed, 48 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
> index ab5811ef5a53..67f3b3b23639 100644
> --- a/drivers/ata/ahci.c
> +++ b/drivers/ata/ahci.c
> @@ -49,8 +49,8 @@ enum {
> enum board_ids {
> /* board IDs by feature in alphabetical order */
> board_ahci,
> + board_ahci_default_lpm,
> board_ahci_ign_iferr,
> - board_ahci_mobile,
> board_ahci_no_debounce_delay,
> board_ahci_nomsi,
> board_ahci_noncq,
> @@ -135,7 +135,7 @@ static const struct ata_port_info ahci_port_info[] = {
> .udma_mask = ATA_UDMA6,
> .port_ops = &ahci_ops,
> },
> - [board_ahci_mobile] = {
> + [board_ahci_default_lpm] = {
What about simply calling this "board_ahci_lpm" ? Shorter :)
> AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
> .flags = AHCI_FLAG_COMMON,
> .pio_mask = ATA_PIO4,
> @@ -275,13 +275,13 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
> { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
> { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
> - { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
> - { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
> - { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
> - { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
> - { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
> + { PCI_VDEVICE(INTEL, 0x2929), board_ahci_default_lpm }, /* ICH9M */
> + { PCI_VDEVICE(INTEL, 0x292a), board_ahci_default_lpm }, /* ICH9M */
> + { PCI_VDEVICE(INTEL, 0x292b), board_ahci_default_lpm }, /* ICH9M */
> + { PCI_VDEVICE(INTEL, 0x292c), board_ahci_default_lpm }, /* ICH9M */
> + { PCI_VDEVICE(INTEL, 0x292f), board_ahci_default_lpm }, /* ICH9M */
> { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
> - { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
> + { PCI_VDEVICE(INTEL, 0x294e), board_ahci_default_lpm }, /* ICH9M */
> { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
> { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
> { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
> @@ -291,9 +291,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
> { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
> { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
> - { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
> + { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_default_lpm }, /* PCH M AHCI */
> { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
> - { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
> + { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_default_lpm }, /* PCH M RAID */
> { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
> { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
> { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
> @@ -316,9 +316,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
> { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
> { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
> - { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
> + { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_default_lpm }, /* CPT M AHCI */
> { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
> - { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
> + { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_default_lpm }, /* CPT M RAID */
> { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
> { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
> { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
> @@ -327,29 +327,29 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG/Lewisburg RAID*/
> { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
> { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
> - { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
> + { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_default_lpm }, /* Panther M AHCI */
> { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
> { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
> { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
> - { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
> + { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_default_lpm }, /* Panther M RAID */
> { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
> { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
> - { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
> + { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_default_lpm }, /* Lynx M AHCI */
> { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
> - { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
> + { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_default_lpm }, /* Lynx M RAID */
> { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
> - { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
> + { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_default_lpm }, /* Lynx M RAID */
> { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
> - { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
> - { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
> - { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
> - { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
> - { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
> - { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
> - { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
> - { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
> - { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
> - { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
> + { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_default_lpm }, /* Lynx M RAID */
> + { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_default_lpm }, /* Lynx LP AHCI */
> + { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_default_lpm }, /* Lynx LP AHCI */
> + { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_default_lpm }, /* Lynx LP RAID */
> + { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_default_lpm }, /* Lynx LP RAID */
> + { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_default_lpm }, /* Lynx LP RAID */
> + { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_default_lpm }, /* Lynx LP RAID */
> + { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_default_lpm }, /* Lynx LP RAID */
> + { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_default_lpm }, /* Lynx LP RAID */
> + { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_default_lpm }, /* Cannon Lake PCH-LP AHCI */
> { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
> { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
> { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
> @@ -381,26 +381,26 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
> { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
> { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
> - { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
> - { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
> - { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
> - { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
> + { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_default_lpm }, /* Wildcat LP AHCI */
> + { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_default_lpm }, /* Wildcat LP RAID */
> + { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_default_lpm }, /* Wildcat LP RAID */
> + { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_default_lpm }, /* Wildcat LP RAID */
> { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
> - { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
> + { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_default_lpm }, /* 9 Series M AHCI */
> { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
> - { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
> + { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_default_lpm }, /* 9 Series M RAID */
> { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
> - { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
> + { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_default_lpm }, /* 9 Series M RAID */
> { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
> - { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
> - { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
> - { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
> - { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
> + { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_default_lpm }, /* 9 Series M RAID */
> + { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_default_lpm }, /* Sunrise LP AHCI */
> + { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_default_lpm }, /* Sunrise LP RAID */
> + { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_default_lpm }, /* Sunrise LP RAID */
> { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
> - { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
> + { PCI_VDEVICE(INTEL, 0xa103), board_ahci_default_lpm }, /* Sunrise M AHCI */
> { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
> { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
> - { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
> + { PCI_VDEVICE(INTEL, 0xa107), board_ahci_default_lpm }, /* Sunrise M RAID */
> { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
> { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
> { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
> @@ -413,13 +413,13 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
> { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
> { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
> - { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
> - { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
> - { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
> - { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
> - { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
> - { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
> - { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
> + { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_default_lpm }, /* Bay Trail AHCI */
> + { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_default_lpm }, /* Bay Trail AHCI */
> + { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_default_lpm }, /* Cherry Tr. AHCI */
> + { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_default_lpm }, /* ApolloLake AHCI */
> + { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_default_lpm }, /* Ice Lake LP AHCI */
> + { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_default_lpm }, /* Comet Lake PCH-U AHCI */
> + { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_default_lpm }, /* Comet Lake PCH RAID */
>
> /* JMicron 360/1/3/5/6, match class to avoid IDE function */
> { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
> @@ -447,7 +447,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
> { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
> { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
> - { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
> + { PCI_VDEVICE(AMD, 0x7901), board_ahci_default_lpm }, /* AMD Green Sardine */
> /* AMD is using RAID class only for ahci controllers */
> { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
> PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 1/3] ata: ahci: Rename board_ahci_mobile
2022-02-16 6:26 ` [PATCH 1/3] ata: ahci: Rename board_ahci_mobile Damien Le Moal
@ 2022-02-16 6:28 ` Limonciello, Mario
0 siblings, 0 replies; 7+ messages in thread
From: Limonciello, Mario @ 2022-02-16 6:28 UTC (permalink / raw)
To: Damien Le Moal
Cc: open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, pmenzel, hdegoede
[Public]
> -----Original Message-----
> From: Damien Le Moal <damien.lemoal@opensource.wdc.com>
> Sent: Wednesday, February 16, 2022 00:27
> To: Limonciello, Mario <Mario.Limonciello@amd.com>
> Cc: open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers) <linux-
> ide@vger.kernel.org>; open list <linux-kernel@vger.kernel.org>;
> pmenzel@molgen.mpg.de; hdegoede@redhat.com
> Subject: Re: [PATCH 1/3] ata: ahci: Rename board_ahci_mobile
>
> On 2/16/22 11:59, Mario Limonciello wrote:
> > This board definition was originally created for mobile devices to
> > designate default link power managmeent policy to influence runtime
> > power consumption.
> >
> > As this is interesting for more than just mobile designs, rename the
> > board to `board_ahci_default_lpm` to make it clear it is about default
> > policy.
> >
> > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> > ---
> > drivers/ata/ahci.c | 96 +++++++++++++++++++++++-----------------------
> > 1 file changed, 48 insertions(+), 48 deletions(-)
> >
> > diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
> > index ab5811ef5a53..67f3b3b23639 100644
> > --- a/drivers/ata/ahci.c
> > +++ b/drivers/ata/ahci.c
> > @@ -49,8 +49,8 @@ enum {
> > enum board_ids {
> > /* board IDs by feature in alphabetical order */
> > board_ahci,
> > + board_ahci_default_lpm,
> > board_ahci_ign_iferr,
> > - board_ahci_mobile,
> > board_ahci_no_debounce_delay,
> > board_ahci_nomsi,
> > board_ahci_noncq,
> > @@ -135,7 +135,7 @@ static const struct ata_port_info ahci_port_info[] = {
> > .udma_mask = ATA_UDMA6,
> > .port_ops = &ahci_ops,
> > },
> > - [board_ahci_mobile] = {
> > + [board_ahci_default_lpm] = {
>
> What about simply calling this "board_ahci_lpm" ? Shorter :)
Thanks!
I like it. I'll switch that in v2 after I get some more feedback on the rest of the series.
>
>
> > AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
> > .flags = AHCI_FLAG_COMMON,
> > .pio_mask = ATA_PIO4,
> > @@ -275,13 +275,13 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> > { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
> > { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
> > { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
> > - { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
> > - { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
> > - { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
> > - { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
> > - { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
> > + { PCI_VDEVICE(INTEL, 0x2929), board_ahci_default_lpm }, /* ICH9M
> */
> > + { PCI_VDEVICE(INTEL, 0x292a), board_ahci_default_lpm }, /* ICH9M
> */
> > + { PCI_VDEVICE(INTEL, 0x292b), board_ahci_default_lpm }, /* ICH9M
> */
> > + { PCI_VDEVICE(INTEL, 0x292c), board_ahci_default_lpm }, /* ICH9M
> */
> > + { PCI_VDEVICE(INTEL, 0x292f), board_ahci_default_lpm }, /* ICH9M
> */
> > { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
> > - { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
> > + { PCI_VDEVICE(INTEL, 0x294e), board_ahci_default_lpm }, /* ICH9M
> */
> > { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
> > { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
> > { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
> > @@ -291,9 +291,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> > { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
> > { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
> > { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
> > - { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI
> */
> > + { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_default_lpm }, /* PCH M
> AHCI */
> > { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
> > - { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID
> */
> > + { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_default_lpm }, /* PCH M
> RAID */
> > { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
> > { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
> > { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
> > @@ -316,9 +316,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> > { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
> > { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
> > { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
> > - { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI
> */
> > + { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_default_lpm }, /* CPT M
> AHCI */
> > { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
> > - { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID
> */
> > + { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_default_lpm }, /* CPT M
> RAID */
> > { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
> > { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
> > { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
> > @@ -327,29 +327,29 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> > { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG/Lewisburg
> RAID*/
> > { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
> > { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI
> */
> > - { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M
> AHCI */
> > + { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_default_lpm }, /* Panther
> M AHCI */
> > { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID
> */
> > { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID
> */
> > { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID
> */
> > - { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_default_lpm }, /* Panther
> M RAID */
> > { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID
> */
> > { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
> > - { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI
> */
> > + { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_default_lpm }, /* Lynx M
> AHCI */
> > { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
> > - { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID
> */
> > + { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_default_lpm }, /* Lynx M
> RAID */
> > { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
> > - { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID
> */
> > + { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_default_lpm }, /* Lynx M
> RAID */
> > { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
> > - { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID
> */
> > - { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI
> */
> > - { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI
> */
> > - { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID
> */
> > - { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID
> */
> > - { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID
> */
> > - { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID
> */
> > - { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID
> */
> > - { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID
> */
> > - { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake
> PCH-LP AHCI */
> > + { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_default_lpm }, /* Lynx M
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_default_lpm }, /* Lynx LP
> AHCI */
> > + { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_default_lpm }, /* Lynx LP
> AHCI */
> > + { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_default_lpm }, /* Lynx LP
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_default_lpm }, /* Lynx LP
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_default_lpm }, /* Lynx LP
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_default_lpm }, /* Lynx LP
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_default_lpm }, /* Lynx LP
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_default_lpm }, /* Lynx LP
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_default_lpm }, /* Cannon
> Lake PCH-LP AHCI */
> > { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
> > { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
> > { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
> > @@ -381,26 +381,26 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> > { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
> > { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
> > { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
> > - { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP
> AHCI */
> > - { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP
> RAID */
> > - { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP
> RAID */
> > - { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_default_lpm }, /* Wildcat
> LP AHCI */
> > + { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_default_lpm }, /* Wildcat
> LP RAID */
> > + { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_default_lpm }, /* Wildcat
> LP RAID */
> > + { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_default_lpm }, /* Wildcat
> LP RAID */
> > { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
> > - { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M
> AHCI */
> > + { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_default_lpm }, /* 9 Series
> M AHCI */
> > { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
> > - { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_default_lpm }, /* 9 Series
> M RAID */
> > { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
> > - { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_default_lpm }, /* 9 Series
> M RAID */
> > { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
> > - { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M
> RAID */
> > - { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP
> AHCI */
> > - { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP
> RAID */
> > - { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP
> RAID */
> > + { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_default_lpm }, /* 9 Series
> M RAID */
> > + { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_default_lpm }, /* Sunrise
> LP AHCI */
> > + { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_default_lpm }, /* Sunrise
> LP RAID */
> > + { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_default_lpm }, /* Sunrise
> LP RAID */
> > { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI
> */
> > - { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M
> AHCI */
> > + { PCI_VDEVICE(INTEL, 0xa103), board_ahci_default_lpm }, /* Sunrise
> M AHCI */
> > { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID
> */
> > { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID
> */
> > - { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M
> RAID */
> > + { PCI_VDEVICE(INTEL, 0xa107), board_ahci_default_lpm }, /* Sunrise
> M RAID */
> > { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID
> */
> > { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
> > { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
> > @@ -413,13 +413,13 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> > { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H
> RAID */
> > { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID
> */
> > { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V
> RAID */
> > - { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI
> */
> > - { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI
> */
> > - { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr.
> AHCI */
> > - { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake
> AHCI */
> > - { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP
> AHCI */
> > - { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake
> PCH-U AHCI */
> > - { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake
> PCH RAID */
> > + { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_default_lpm }, /* Bay Trail
> AHCI */
> > + { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_default_lpm }, /* Bay Trail
> AHCI */
> > + { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_default_lpm }, /* Cherry
> Tr. AHCI */
> > + { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_default_lpm }, /*
> ApolloLake AHCI */
> > + { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_default_lpm }, /* Ice Lake
> LP AHCI */
> > + { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_default_lpm }, /* Comet
> Lake PCH-U AHCI */
> > + { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_default_lpm }, /* Comet
> Lake PCH RAID */
> >
> > /* JMicron 360/1/3/5/6, match class to avoid IDE function */
> > { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID,
> PCI_ANY_ID,
> > @@ -447,7 +447,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> > { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
> > { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /*
> AMD Hudson-2 (AHCI mode) */
> > { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
> > - { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green
> Sardine */
> > + { PCI_VDEVICE(AMD, 0x7901), board_ahci_default_lpm }, /* AMD
> Green Sardine */
> > /* AMD is using RAID class only for ahci controllers */
> > { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
> > PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
>
>
> --
> Damien Le Moal
> Western Digital Research
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] ata: ahci: Rename CONFIG_SATA_LPM_MOBILE_POLICY configuration item
2022-02-16 2:59 ` [PATCH 3/3] ata: ahci: Rename CONFIG_SATA_LPM_MOBILE_POLICY configuration item Mario Limonciello
@ 2022-02-16 12:44 ` Hans de Goede
2022-02-16 13:41 ` Limonciello, Mario
0 siblings, 1 reply; 7+ messages in thread
From: Hans de Goede @ 2022-02-16 12:44 UTC (permalink / raw)
To: Mario Limonciello, Damien Le Moal
Cc: open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, pmenzel
Hi,
On 2/16/22 03:59, Mario Limonciello wrote:
> `CONFIG_SATA_LPM_MOBILE_POLICY` reflects a configuration to apply only to
> mobile chipsets. As some desktop boards may want to use this policy by
> default as well, rename the configuration item to `SATA_LPM_POLICY`.
>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> drivers/ata/Kconfig | 6 +++---
> drivers/ata/ahci.c | 2 +-
> drivers/ata/ahci.h | 2 +-
> 3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index cb54631fd950..52c086f155f0 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -115,14 +115,14 @@ config SATA_AHCI
>
> If unsure, say N.
>
> -config SATA_MOBILE_LPM_POLICY
> - int "Default SATA Link Power Management policy for mobile chipsets"
> +config SATA_LPM_POLICY
Maybe "config SATA_DEFAULT_LPM_POLICY" at least that matches the summary text better ?
> + int "Default SATA Link Power Management policy for supported chipsets"
> range 0 4
> default 0
> depends on SATA_AHCI
> help
> Select the Default SATA Link Power Management (LPM) policy to use
> - for mobile / laptop variants of chipsets / "South Bridges".
> + for certain chipsets / "South Bridges".
Maybe:
for chipsets where using a different default policy then max_performance
is deemed desirable.
Yeah no, that IMHO is no good either, but "certain" also is very much
not helpful in this help text.
Looking at this patch I'm starting to think that maybe the maybe mobile was not
that bad of a name after all :)
Maybe for v2 do s/mobile/low_power/ in each of the patches instead?
Regards,
Hans
>
> The value set has the following meanings:
> 0 => Keep firmware settings
> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
> index 5be889de9b1e..7a7fa1090bb0 100644
> --- a/drivers/ata/ahci.c
> +++ b/drivers/ata/ahci.c
> @@ -1592,7 +1592,7 @@ static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
> static void ahci_update_initial_lpm_policy(struct ata_port *ap,
> struct ahci_host_priv *hpriv)
> {
> - int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
> + int policy = CONFIG_SATA_LPM_POLICY;
>
>
> /* Ignore processing for chipsets that don't use policy */
> diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
> index 1ad48e2fe573..5badbaca05a0 100644
> --- a/drivers/ata/ahci.h
> +++ b/drivers/ata/ahci.h
> @@ -236,7 +236,7 @@ enum {
> AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
> only registers */
> AHCI_HFLAG_USE_LPM_POLICY = (1 << 25), /* chipset that should use
> - SATA_MOBILE_LPM_POLICY
> + SATA_LPM_POLICY
> as default lpm_policy */
> AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
> suspend/resume */
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] ata: ahci: Rename CONFIG_SATA_LPM_MOBILE_POLICY configuration item
2022-02-16 12:44 ` Hans de Goede
@ 2022-02-16 13:41 ` Limonciello, Mario
0 siblings, 0 replies; 7+ messages in thread
From: Limonciello, Mario @ 2022-02-16 13:41 UTC (permalink / raw)
To: Hans de Goede, Damien Le Moal
Cc: open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, pmenzel
On 2/16/2022 06:44, Hans de Goede wrote:
> Hi,
>
> On 2/16/22 03:59, Mario Limonciello wrote:
>> `CONFIG_SATA_LPM_MOBILE_POLICY` reflects a configuration to apply only to
>> mobile chipsets. As some desktop boards may want to use this policy by
>> default as well, rename the configuration item to `SATA_LPM_POLICY`.
>>
>> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
>> ---
>> drivers/ata/Kconfig | 6 +++---
>> drivers/ata/ahci.c | 2 +-
>> drivers/ata/ahci.h | 2 +-
>> 3 files changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
>> index cb54631fd950..52c086f155f0 100644
>> --- a/drivers/ata/Kconfig
>> +++ b/drivers/ata/Kconfig
>> @@ -115,14 +115,14 @@ config SATA_AHCI
>>
>> If unsure, say N.
>>
>> -config SATA_MOBILE_LPM_POLICY
>> - int "Default SATA Link Power Management policy for mobile chipsets"
>> +config SATA_LPM_POLICY
>
> Maybe "config SATA_DEFAULT_LPM_POLICY" at least that matches the summary text better ?
>
>> + int "Default SATA Link Power Management policy for supported chipsets"
>> range 0 4
>> default 0
>> depends on SATA_AHCI
>> help
>> Select the Default SATA Link Power Management (LPM) policy to use
>> - for mobile / laptop variants of chipsets / "South Bridges".
>> + for certain chipsets / "South Bridges".
>
> Maybe:
>
> for chipsets where using a different default policy then max_performance
> is deemed desirable.
>
> Yeah no, that IMHO is no good either, but "certain" also is very much
> not helpful in this help text.
>
> Looking at this patch I'm starting to think that maybe the maybe mobile was not
> that bad of a name after all :)
>
> Maybe for v2 do s/mobile/low_power/ in each of the patches instead?
Sure, I'll do that and see how everything looks and reads.
>
> Regards,
>
> Hans
>
>
>
>
>
>
>
>
>
>
>
>>
>> The value set has the following meanings:
>> 0 => Keep firmware settings
>> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
>> index 5be889de9b1e..7a7fa1090bb0 100644
>> --- a/drivers/ata/ahci.c
>> +++ b/drivers/ata/ahci.c
>> @@ -1592,7 +1592,7 @@ static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
>> static void ahci_update_initial_lpm_policy(struct ata_port *ap,
>> struct ahci_host_priv *hpriv)
>> {
>> - int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
>> + int policy = CONFIG_SATA_LPM_POLICY;
>>
>>
>> /* Ignore processing for chipsets that don't use policy */
>> diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
>> index 1ad48e2fe573..5badbaca05a0 100644
>> --- a/drivers/ata/ahci.h
>> +++ b/drivers/ata/ahci.h
>> @@ -236,7 +236,7 @@ enum {
>> AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
>> only registers */
>> AHCI_HFLAG_USE_LPM_POLICY = (1 << 25), /* chipset that should use
>> - SATA_MOBILE_LPM_POLICY
>> + SATA_LPM_POLICY
>> as default lpm_policy */
>> AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
>> suspend/resume */
>>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-02-16 13:41 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-16 2:59 [PATCH 1/3] ata: ahci: Rename board_ahci_mobile Mario Limonciello
2022-02-16 2:59 ` [PATCH 2/3] ata: ahci: Rename `AHCI_HFLAG_IS_MOBILE` Mario Limonciello
2022-02-16 2:59 ` [PATCH 3/3] ata: ahci: Rename CONFIG_SATA_LPM_MOBILE_POLICY configuration item Mario Limonciello
2022-02-16 12:44 ` Hans de Goede
2022-02-16 13:41 ` Limonciello, Mario
2022-02-16 6:26 ` [PATCH 1/3] ata: ahci: Rename board_ahci_mobile Damien Le Moal
2022-02-16 6:28 ` Limonciello, Mario
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