[PATCH v2] arm64: kexec: Support the case of VA_BITS=39 in trans_pgd_idmap_page()

[PATCH v2] arm64: kexec: Support the case of VA_BITS=39 in trans_pgd_idmap_page()

[cgel.zte]

From: sihao <si.hao@zte.com.cn>

fsl64() may get different values due to different physical addresses. Is
it possible to confirm the value of max_msb with CONFIG_ARM64_VA_BITS?

Reported-by: sihao <si.hao@zte.com.cn>
Signed-off-by: sihao <si.hao@zte.com.cn>
Reviewed-by: CatalinMarinas <catalin.marinas@arm.com>
---
Changes in V1:

Refer to: https://lore.kernel.org/lkml/20220121065216.1001021-1-si.hao@zte.com.cn/

When the values of CONFIG_ARM64_VA_BITS and CONFIG_ARM64_PA_BITS are not
equal, the following panic occurs when kexec is executed. 
This happens because trans_pgd_idmap_page() does not support VA_BITS=39.
So the patch supports the case of VA_BITS=39.

 arch/arm64/mm/trans_pgd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/mm/trans_pgd.c b/arch/arm64/mm/trans_pgd.c
index d7da8ca40d2e..23c74f9c5790 100644
--- a/arch/arm64/mm/trans_pgd.c
+++ b/arch/arm64/mm/trans_pgd.c
@@ -232,7 +232,7 @@ int trans_pgd_idmap_page(struct trans_pgd_info *info, phys_addr_t *trans_ttbr0,
 {
 	phys_addr_t dst_addr = virt_to_phys(page);
 	unsigned long pfn = __phys_to_pfn(dst_addr);
-	int max_msb = (dst_addr & GENMASK(52, 48)) ? 51 : 47;
+	int max_msb = VA_BITS - 1;
 	int bits_mapped = PAGE_SHIFT - 4;
 	unsigned long level_mask, prev_level_entry, *levels[4];
 	int this_level, index, level_lsb, level_msb;
-- 
2.25.1

Re: [PATCH v2] arm64: kexec: Support the case of VA_BITS=39 in trans_pgd_idmap_page()

[Catalin Marinas]

On Thu, Feb 17, 2022 at 08:37:34AM +0000, cgel.zte@gmail.com wrote:
> From: sihao <si.hao@zte.com.cn>
> 
> fsl64() may get different values due to different physical addresses. Is
> it possible to confirm the value of max_msb with CONFIG_ARM64_VA_BITS?
> 
> Reported-by: sihao <si.hao@zte.com.cn>
> Signed-off-by: sihao <si.hao@zte.com.cn>
> Reviewed-by: CatalinMarinas <catalin.marinas@arm.com>

I have not reviewed this patch yet, so this line shouldn't be here. I'll
have a look next week.

Thanks.

-- 
Catalin