* [RFC PATCH 0/6] Add Sstc extension support
@ 2022-02-28 9:42 Atish Patra
2022-02-28 9:42 ` [RFC PATCH 1/6] RISC-V: Add SSTC extension CSR details Atish Patra
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Atish Patra @ 2022-02-28 9:42 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Atish Patra, kvm-riscv, Anup Patel,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
This series implements Sstc extension support which was ratified recently.
Before the Sstc extension, an SBI call is necessary to generate timer
interrupts as only M-mode have access to the timecompare registers. Thus,
there is significant latency to generate timer interrupts at kernel.
For virtualized enviornments, its even worse as the KVM handles the SBI call
and uses a software timer to emulate the timecomapre register.
Sstc extension solves both these problems by defining a stimecmp/vstimecmp
at supervisor (host/guest) level. It allows kernel to program a timer and
recieve interrupt without supervisor execution enviornment (M-mode/HS mode)
intervention.
To maintain backward compatibility, KVM directly updates the vstimecmp
if older kernel without sstc support is running in guest. Similary, the
M-mode firmware(OpenSBI) uses stimecmp for older kernel without sstc support.
The PATCH 1 & 2 enables the basic infrastructure around Sstc extension while
PATCH 3 lets kernel use the Sstc extension if it is available in hardware.
PATCH 4 & 5 adds the infrastructure for KVM to use sstc while PATCH 6 actually
uses the Sstc extension if available.
This series has been tested on Qemu(RV32 & RV64) with additional patches in
OpenSBI[2] and Qemu[3]. This series can also be found at [4].
[1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view
[2] https://github.com/atishp04/opensbi/tree/sstc_v1
[3] https://github.com/atishp04/qemu/tree/sstc_v1
[3] https://github.com/atishp04/linux/tree/sstc_v1
Atish Patra (6):
RISC-V: Add SSTC extension CSR details
RISC-V: Enable sstc extension parsing from DT
RISC-V: Prefer sstc extension if available
RISC-V: Restrict the isa field in config register to base extensions
RISC-V: KVM: Introduce ISA extension register
RISC-V: KVM: Support sstc extension
arch/riscv/include/asm/csr.h | 11 ++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/kvm_host.h | 4 +
arch/riscv/include/asm/kvm_vcpu_timer.h | 3 +-
arch/riscv/include/asm/timex.h | 2 +
arch/riscv/include/uapi/asm/kvm.h | 22 ++++
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 4 +-
arch/riscv/kvm/main.c | 8 ++
arch/riscv/kvm/vcpu.c | 111 ++++++++++++++++++-
arch/riscv/kvm/vcpu_sbi_replace.c | 10 +-
arch/riscv/kvm/vcpu_timer.c | 136 +++++++++++++++++++++++-
drivers/clocksource/timer-riscv.c | 22 +++-
13 files changed, 323 insertions(+), 12 deletions(-)
--
2.30.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [RFC PATCH 1/6] RISC-V: Add SSTC extension CSR details
2022-02-28 9:42 [RFC PATCH 0/6] Add Sstc extension support Atish Patra
@ 2022-02-28 9:42 ` Atish Patra
2022-02-28 9:42 ` [RFC PATCH 2/6] RISC-V: Enable sstc extension parsing from DT Atish Patra
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Atish Patra @ 2022-02-28 9:42 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Atish Patra, kvm-riscv, Anup Patel,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
This patch just introduces the required CSR fields related to the
SSTC extension.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/csr.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index ae711692eec9..8f37c063a205 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -165,6 +165,9 @@
#define CSR_SIP 0x144
#define CSR_SATP 0x180
+#define CSR_STIMECMP 0x14D
+#define CSR_STIMECMPH 0x15D
+
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
#define CSR_VSTVEC 0x205
@@ -174,6 +177,8 @@
#define CSR_VSTVAL 0x243
#define CSR_VSIP 0x244
#define CSR_VSATP 0x280
+#define CSR_VSTIMECMP 0x24D
+#define CSR_VSTIMECMPH 0x25D
#define CSR_HSTATUS 0x600
#define CSR_HEDELEG 0x602
@@ -189,6 +194,8 @@
#define CSR_HTINST 0x64a
#define CSR_HGATP 0x680
#define CSR_HGEIP 0xe12
+#define CSR_HENVCFG 0x60A
+#define CSR_HENVCFGH 0x61A
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
@@ -247,6 +254,10 @@
#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
+/* ENVCFG related bits */
+#define HENVCFG_STCE 63
+#define HENVCFGH_STCE 31
+
#ifndef __ASSEMBLY__
#define csr_swap(csr, val) \
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC PATCH 2/6] RISC-V: Enable sstc extension parsing from DT
2022-02-28 9:42 [RFC PATCH 0/6] Add Sstc extension support Atish Patra
2022-02-28 9:42 ` [RFC PATCH 1/6] RISC-V: Add SSTC extension CSR details Atish Patra
@ 2022-02-28 9:42 ` Atish Patra
2022-02-28 9:42 ` [RFC PATCH 3/6] RISC-V: Prefer sstc extension if available Atish Patra
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Atish Patra @ 2022-02-28 9:42 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Atish Patra, kvm-riscv, Anup Patel,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
The ISA extension framework now allows parsing any multi-letter
ISA extension.
Enable that for sstc extension.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 4 +++-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 691fc9c8099b..7335e9138fb7 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -51,6 +51,7 @@ extern unsigned long elf_hwcap;
* available logical extension id.
*/
enum riscv_isa_ext_id {
+ RISCV_ISA_EXT_SSTC = RISCV_ISA_EXT_BASE,
RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 031ad15a059f..7568c7084a52 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -71,6 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node)
}
static struct riscv_isa_ext_data isa_ext_arr[] = {
+ __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
};
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f3a4b0619aa0..1d8a06575cea 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -192,8 +192,10 @@ void __init riscv_fill_hwcap(void)
if (!ext_long) {
this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
set_bit(*ext - 'a', this_isa);
- }
+ } else {
+ SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
#undef SET_ISA_EXT_MAP
+ }
}
/*
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC PATCH 3/6] RISC-V: Prefer sstc extension if available
2022-02-28 9:42 [RFC PATCH 0/6] Add Sstc extension support Atish Patra
2022-02-28 9:42 ` [RFC PATCH 1/6] RISC-V: Add SSTC extension CSR details Atish Patra
2022-02-28 9:42 ` [RFC PATCH 2/6] RISC-V: Enable sstc extension parsing from DT Atish Patra
@ 2022-02-28 9:42 ` Atish Patra
2022-02-28 9:42 ` [RFC PATCH 4/6] RISC-V: Restrict the isa field in config register to base extensions Atish Patra
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Atish Patra @ 2022-02-28 9:42 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Atish Patra, kvm-riscv, Anup Patel,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
RISC-V ISA has sstc extension which allows updating the next clock event
via a CSR (stimecmp) instead of an SBI call. This should happen dynamically
if sstc extension is available. Otherwise, it will fallback to SBI call
to maintain backward compatibility.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/timex.h | 2 ++
drivers/clocksource/timer-riscv.c | 22 +++++++++++++++++++++-
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
index 507cae273bc6..dc0ffed04ea1 100644
--- a/arch/riscv/include/asm/timex.h
+++ b/arch/riscv/include/asm/timex.h
@@ -48,6 +48,8 @@ static inline unsigned long random_get_entropy(void)
#else /* CONFIG_RISCV_M_MODE */
+extern struct static_key_false cpu_sstc_available;
+#define cpu_sstc_ext_available static_branch_likely(&cpu_sstc_available)
static inline cycles_t get_cycles(void)
{
return csr_read(CSR_TIME);
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 1767f8bf2013..f032da8a4272 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -23,11 +23,25 @@
#include <asm/sbi.h>
#include <asm/timex.h>
+DEFINE_STATIC_KEY_FALSE(cpu_sstc_available);
+EXPORT_SYMBOL(cpu_sstc_available);
+
static int riscv_clock_next_event(unsigned long delta,
struct clock_event_device *ce)
{
+ uint64_t next_tval = get_cycles64() + delta;
+
csr_set(CSR_IE, IE_TIE);
- sbi_set_timer(get_cycles64() + delta);
+ if (cpu_sstc_ext_available) {
+#if __riscv_xlen == 32
+ csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
+ csr_write(CSR_STIMECMPH, next_tval >> 32);
+#else
+ csr_write(CSR_STIMECMP, get_cycles64() + delta);
+#endif
+ } else
+ sbi_set_timer(get_cycles64() + delta);
+
return 0;
}
@@ -165,6 +179,12 @@ static int __init riscv_timer_init_dt(struct device_node *n)
if (error)
pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
error);
+
+ if (riscv_isa_extension_available(NULL, SSTC)) {
+ pr_info("S-mode timer interrupt mode is available via sstc extension\n");
+ static_branch_enable(&cpu_sstc_available);
+ }
+
return error;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC PATCH 4/6] RISC-V: Restrict the isa field in config register to base extensions
2022-02-28 9:42 [RFC PATCH 0/6] Add Sstc extension support Atish Patra
` (2 preceding siblings ...)
2022-02-28 9:42 ` [RFC PATCH 3/6] RISC-V: Prefer sstc extension if available Atish Patra
@ 2022-02-28 9:42 ` Atish Patra
2022-02-28 9:42 ` [RFC PATCH 5/6] RISC-V: KVM: Introduce ISA extension register Atish Patra
2022-02-28 9:42 ` [RFC PATCH 6/6] RISC-V: KVM: Support sstc extension Atish Patra
5 siblings, 0 replies; 7+ messages in thread
From: Atish Patra @ 2022-02-28 9:42 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Atish Patra, kvm-riscv, Anup Patel,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
The isa field in config register is meant only for single letter base ISA
extensions. Multi-letter extensions can not be encoded here as it will
exceed the size of ULONG easily in future.
Only allow single letter extensions (0-25) to be encoded in that field.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu.c | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index f808ad1ce500..aa9f5a5c57d8 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -47,6 +47,7 @@ struct kvm_sregs {
/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
struct kvm_riscv_config {
+ /* This is a bitmap of all the single letter base ISA extensions */
unsigned long isa;
};
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 624166004e36..7a07dba504f8 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -182,13 +182,14 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
KVM_REG_SIZE_MASK |
KVM_REG_RISCV_CONFIG);
unsigned long reg_val;
+ unsigned long isa_mask = GENMASK(25, 0);
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
return -EINVAL;
switch (reg_num) {
case KVM_REG_RISCV_CONFIG_REG(isa):
- reg_val = vcpu->arch.isa;
+ reg_val = vcpu->arch.isa & isa_mask;
break;
default:
return -EINVAL;
@@ -209,6 +210,7 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
KVM_REG_SIZE_MASK |
KVM_REG_RISCV_CONFIG);
unsigned long reg_val;
+ unsigned long isa_mask = GENMASK(25, 0);
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
return -EINVAL;
@@ -219,7 +221,7 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
switch (reg_num) {
case KVM_REG_RISCV_CONFIG_REG(isa):
if (!vcpu->arch.ran_atleast_once) {
- vcpu->arch.isa = reg_val;
+ vcpu->arch.isa = reg_val & isa_mask;
vcpu->arch.isa &= riscv_isa_extension_base(NULL);
vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED;
kvm_riscv_vcpu_fp_reset(vcpu);
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC PATCH 5/6] RISC-V: KVM: Introduce ISA extension register
2022-02-28 9:42 [RFC PATCH 0/6] Add Sstc extension support Atish Patra
` (3 preceding siblings ...)
2022-02-28 9:42 ` [RFC PATCH 4/6] RISC-V: Restrict the isa field in config register to base extensions Atish Patra
@ 2022-02-28 9:42 ` Atish Patra
2022-02-28 9:42 ` [RFC PATCH 6/6] RISC-V: KVM: Support sstc extension Atish Patra
5 siblings, 0 replies; 7+ messages in thread
From: Atish Patra @ 2022-02-28 9:42 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Atish Patra, kvm-riscv, Anup Patel,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
Currently, there is no provision for vmm (qemu-kvm or kvmtool) to
query about multiple-letter ISA extensions. The config register
is only used for base single letter ISA extensions.
A new ISA extension register is added that will allow the vmm
to query about any ISA extension one at a time. It is enabled for
both single letter or multi-letter ISA extensions. The ISA extension
register is useful to if the vmm requires to retrieve/set single
extension while the config register should be used if all the base
ISA extension required to retrieve or set.
For any multi-letter ISA extensions, the new register interface
must be used.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/uapi/asm/kvm.h | 20 ++++++
arch/riscv/kvm/vcpu.c | 101 ++++++++++++++++++++++++++++++
2 files changed, 121 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index aa9f5a5c57d8..e01678aa2a55 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -83,6 +83,23 @@ struct kvm_riscv_timer {
__u64 state;
};
+/**
+ * ISA extension IDs specific to KVM. This is not the same as the host ISA
+ * extension IDs as that is internal to the host and should not be exposed
+ * to the guest. This should always be contiguous to keep the mapping simple
+ * in KVM implementation.
+ */
+enum KVM_RISCV_ISA_EXT_ID {
+ KVM_RISCV_ISA_EXT_A = 0,
+ KVM_RISCV_ISA_EXT_C,
+ KVM_RISCV_ISA_EXT_D,
+ KVM_RISCV_ISA_EXT_F,
+ KVM_RISCV_ISA_EXT_H,
+ KVM_RISCV_ISA_EXT_I,
+ KVM_RISCV_ISA_EXT_M,
+ KVM_RISCV_ISA_EXT_MAX,
+};
+
/* Possible states for kvm_riscv_timer */
#define KVM_RISCV_TIMER_STATE_OFF 0
#define KVM_RISCV_TIMER_STATE_ON 1
@@ -124,6 +141,9 @@ struct kvm_riscv_timer {
#define KVM_REG_RISCV_FP_D_REG(name) \
(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
+/* ISA Extension registers are mapped as type 7 */
+#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
+
#endif
#endif /* __LINUX_KVM_RISCV_H */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 7a07dba504f8..c314c40be313 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -364,6 +364,103 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu,
return 0;
}
+/* Mapping between KVM ISA Extension ID & Host ISA extension ID */
+static unsigned long kvm_isa_ext_arr[] = {
+ RISCV_ISA_EXT_a,
+ RISCV_ISA_EXT_c,
+ RISCV_ISA_EXT_d,
+ RISCV_ISA_EXT_f,
+ RISCV_ISA_EXT_h,
+ RISCV_ISA_EXT_i,
+ RISCV_ISA_EXT_m,
+};
+
+static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg)
+{
+ unsigned long __user *uaddr =
+ (unsigned long __user *)(unsigned long)reg->addr;
+ unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
+ KVM_REG_SIZE_MASK |
+ KVM_REG_RISCV_ISA_EXT);
+ unsigned long reg_val = 0;
+ unsigned long host_isa_ext;
+
+ if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
+ return -EINVAL;
+
+ if (reg_num >= KVM_RISCV_ISA_EXT_MAX || reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
+ return -EINVAL;
+
+ host_isa_ext = kvm_isa_ext_arr[reg_num];
+ if (__riscv_isa_extension_available(NULL, host_isa_ext))
+ reg_val = 1; /* Mark the given extension as available */
+
+ if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg)
+{
+ unsigned long __user *uaddr =
+ (unsigned long __user *)(unsigned long)reg->addr;
+ unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
+ KVM_REG_SIZE_MASK |
+ KVM_REG_RISCV_ISA_EXT);
+ unsigned long reg_val;
+ unsigned long host_isa_ext;
+ unsigned long host_isa_ext_mask;
+
+ if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
+ return -EINVAL;
+
+ if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
+ return -EINVAL;
+
+ if (reg_num >= KVM_RISCV_ISA_EXT_MAX || reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
+ return -EINVAL;
+
+ if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
+ return -EFAULT;
+
+ host_isa_ext = kvm_isa_ext_arr[reg_num];
+ if (!__riscv_isa_extension_available(NULL, host_isa_ext))
+ return -EOPNOTSUPP;
+
+ if (host_isa_ext >= RISCV_ISA_EXT_BASE &&
+ host_isa_ext < RISCV_ISA_EXT_MAX) {
+ /** Multi-letter ISA extension. Currently there is no provision
+ * to enable/disable the multi-letter ISA extensions for guests.
+ * Return success if the request is to enable any ISA extension
+ * that is available in the hardware.
+ * Return -EOPNOTSUPP otherwise.
+ */
+ if (!reg_val)
+ return -EOPNOTSUPP;
+ else
+ return 0;
+ }
+
+ /* Single letter base ISA extension */
+ if (!vcpu->arch.ran_atleast_once) {
+ host_isa_ext_mask = reg_val ? (1 << host_isa_ext) : ~(1 << host_isa_ext);
+ if (!reg_val)
+ vcpu->arch.isa &= host_isa_ext_mask;
+ else
+ vcpu->arch.isa |= host_isa_ext_mask;
+ vcpu->arch.isa &= riscv_isa_extension_base(NULL);
+ vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED;
+ kvm_riscv_vcpu_fp_reset(vcpu);
+ } else {
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
const struct kvm_one_reg *reg)
{
@@ -381,6 +478,8 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
KVM_REG_RISCV_FP_D);
+ else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
+ return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
return -EINVAL;
}
@@ -402,6 +501,8 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
KVM_REG_RISCV_FP_D);
+ else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
+ return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
return -EINVAL;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RFC PATCH 6/6] RISC-V: KVM: Support sstc extension
2022-02-28 9:42 [RFC PATCH 0/6] Add Sstc extension support Atish Patra
` (4 preceding siblings ...)
2022-02-28 9:42 ` [RFC PATCH 5/6] RISC-V: KVM: Introduce ISA extension register Atish Patra
@ 2022-02-28 9:42 ` Atish Patra
5 siblings, 0 replies; 7+ messages in thread
From: Atish Patra @ 2022-02-28 9:42 UTC (permalink / raw)
To: linux-kernel
Cc: Atish Patra, Albert Ou, Atish Patra, kvm-riscv, Anup Patel,
Damien Le Moal, devicetree, Jisheng Zhang, Krzysztof Kozlowski,
linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring
Sstc extension allows the guest to program the vstimecmp CSR directly
instead of making an SBI call to the hypervisor to program the next
event. The timer interrupt is also directly injected to the guest by
the hardware in this case. To maintain backward compatibility, the
hypervisors also update the vstimecmp in an SBI set_time call if
the hardware supports it. Thus, the older kernels in guest also
take advantage of the sstc extension.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/kvm_host.h | 4 +
arch/riscv/include/asm/kvm_vcpu_timer.h | 3 +-
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/main.c | 8 ++
arch/riscv/kvm/vcpu.c | 4 +-
arch/riscv/kvm/vcpu_sbi_replace.c | 10 +-
arch/riscv/kvm/vcpu_timer.c | 136 +++++++++++++++++++++++-
7 files changed, 158 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 99ef6a120617..fb8c993ba022 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -135,6 +135,7 @@ struct kvm_vcpu_csr {
unsigned long hvip;
unsigned long vsatp;
unsigned long scounteren;
+ u64 vstimecmp;
};
struct kvm_vcpu_arch {
@@ -179,6 +180,9 @@ struct kvm_vcpu_arch {
/* VCPU Timer */
struct kvm_vcpu_timer timer;
+ /* VCPU Timer for vstimecmp */
+ struct kvm_vcpu_timer vstimer;
+
/* MMIO instruction details */
struct kvm_mmio_decode mmio_decode;
diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h
index 375281eb49e0..10715b81db86 100644
--- a/arch/riscv/include/asm/kvm_vcpu_timer.h
+++ b/arch/riscv/include/asm/kvm_vcpu_timer.h
@@ -39,6 +39,7 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu);
int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu);
int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu);
void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu);
+void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu);
int kvm_riscv_guest_timer_init(struct kvm *kvm);
-
+bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu);
#endif
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index e01678aa2a55..c7c313272c0b 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -97,6 +97,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_H,
KVM_RISCV_ISA_EXT_I,
KVM_RISCV_ISA_EXT_M,
+ KVM_RISCV_ISA_EXT_SSTC,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
index 2e5ca43c8c49..8485f59d2db3 100644
--- a/arch/riscv/kvm/main.c
+++ b/arch/riscv/kvm/main.c
@@ -13,6 +13,7 @@
#include <asm/csr.h>
#include <asm/hwcap.h>
#include <asm/sbi.h>
+#include <asm/timex.h>
long kvm_arch_dev_ioctl(struct file *filp,
unsigned int ioctl, unsigned long arg)
@@ -50,6 +51,13 @@ int kvm_arch_hardware_enable(void)
csr_write(CSR_HIDELEG, hideleg);
csr_write(CSR_HCOUNTEREN, -1UL);
+ if (cpu_sstc_ext_available) {
+#ifdef CONFIG_64BIT
+ csr_write(CSR_HENVCFG, 1UL<<HENVCFG_STCE);
+#else
+ csr_write(CSR_HENVCFGH, 1UL<<HENVCFGH_STCE);
+#endif
+ }
csr_write(CSR_HVIP, 0);
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index c314c40be313..dda1fc950178 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -141,7 +141,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
{
- return kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER);
+ return kvm_riscv_vcpu_timer_pending(vcpu);
}
void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
@@ -373,6 +373,7 @@ static unsigned long kvm_isa_ext_arr[] = {
RISCV_ISA_EXT_h,
RISCV_ISA_EXT_i,
RISCV_ISA_EXT_m,
+ RISCV_ISA_EXT_SSTC,
};
static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
@@ -756,6 +757,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
vcpu->arch.isa);
kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);
+ kvm_riscv_vcpu_timer_save(vcpu);
csr_write(CSR_HGATP, 0);
csr->vsstatus = csr_read(CSR_VSSTATUS);
diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c
index 1bc0608a5bfd..e34fc9e1f41b 100644
--- a/arch/riscv/kvm/vcpu_sbi_replace.c
+++ b/arch/riscv/kvm/vcpu_sbi_replace.c
@@ -30,7 +30,15 @@ static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
#else
next_cycle = (u64)cp->a0;
#endif
- kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle);
+ if (cpu_sstc_ext_available) {
+#if __riscv_xlen == 32
+ csr_write(CSR_VSTIMECMP, next_cycle & 0xFFFFFFFF);
+ csr_write(CSR_VSTIMECMPH, next_cycle >> 32);
+#else
+ csr_write(CSR_VSTIMECMP, next_cycle);
+#endif
+ } else
+ kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle);
return ret;
}
diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c
index 5c4c37ff2d48..5647c234fea3 100644
--- a/arch/riscv/kvm/vcpu_timer.c
+++ b/arch/riscv/kvm/vcpu_timer.c
@@ -14,6 +14,7 @@
#include <asm/csr.h>
#include <asm/delay.h>
#include <asm/kvm_vcpu_timer.h>
+#include <asm/timex.h>
static u64 kvm_riscv_current_cycles(struct kvm_guest_timer *gt)
{
@@ -88,10 +89,66 @@ int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
return 0;
}
+static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer *h)
+{
+ u64 delta_ns;
+ struct kvm_vcpu_timer *vst = container_of(h, struct kvm_vcpu_timer, hrt);
+ struct kvm_vcpu *vcpu = container_of(vst, struct kvm_vcpu, arch.vstimer);
+ struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
+
+ if (kvm_riscv_current_cycles(gt) < vst->next_cycles) {
+ delta_ns = kvm_riscv_delta_cycles2ns(vst->next_cycles, gt, vst);
+ hrtimer_forward_now(&vst->hrt, ktime_set(0, delta_ns));
+ return HRTIMER_RESTART;
+ }
+
+ vst->next_set = false;
+ kvm_vcpu_kick(vcpu);
+
+ return HRTIMER_NORESTART;
+}
+
+bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_timer *vst = &vcpu->arch.vstimer;
+ struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
+ u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp;
+
+ if (!kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, vst) ||
+ kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER))
+ return true;
+ else
+ return false;
+}
+
+static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_timer *vst = &vcpu->arch.vstimer;
+ struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
+ u64 delta_ns;
+ u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp;
+
+ if (!vst->init_done)
+ return;
+
+ delta_ns = kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, vst);
+ if (delta_ns) {
+ vst->next_cycles = vstimecmp_val;
+ hrtimer_start(&vst->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL);
+ vst->next_set = true;
+ }
+}
+
+static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu)
+{
+ kvm_riscv_vcpu_timer_cancel(&vcpu->arch.vstimer);
+}
+
int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu,
const struct kvm_one_reg *reg)
{
struct kvm_vcpu_timer *t = &vcpu->arch.timer;
+ struct kvm_vcpu_timer *vst = &vcpu->arch.vstimer;
struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
@@ -112,7 +169,10 @@ int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu,
reg_val = kvm_riscv_current_cycles(gt);
break;
case KVM_REG_RISCV_TIMER_REG(compare):
- reg_val = t->next_cycles;
+ if (cpu_sstc_ext_available)
+ reg_val = vst->next_cycles;
+ else
+ reg_val = t->next_cycles;
break;
case KVM_REG_RISCV_TIMER_REG(state):
reg_val = (t->next_set) ? KVM_RISCV_TIMER_STATE_ON :
@@ -132,6 +192,7 @@ int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu,
const struct kvm_one_reg *reg)
{
struct kvm_vcpu_timer *t = &vcpu->arch.timer;
+ struct kvm_vcpu_timer *vst = &vcpu->arch.vstimer;
struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
@@ -156,7 +217,10 @@ int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu,
gt->time_delta = reg_val - get_cycles64();
break;
case KVM_REG_RISCV_TIMER_REG(compare):
- t->next_cycles = reg_val;
+ if (cpu_sstc_ext_available)
+ vst->next_cycles = reg_val;
+ else
+ t->next_cycles = reg_val;
break;
case KVM_REG_RISCV_TIMER_REG(state):
if (reg_val == KVM_RISCV_TIMER_STATE_ON)
@@ -175,8 +239,9 @@ int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu,
int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu)
{
struct kvm_vcpu_timer *t = &vcpu->arch.timer;
+ struct kvm_vcpu_timer *vst = &vcpu->arch.vstimer;
- if (t->init_done)
+ if (t->init_done || vst->init_done)
return -EINVAL;
hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
@@ -184,6 +249,11 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu)
t->init_done = true;
t->next_set = false;
+ hrtimer_init(&vst->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ vst->hrt.function = kvm_riscv_vcpu_vstimer_expired;
+ vst->init_done = true;
+ vst->next_set = false;
+
return 0;
}
@@ -194,15 +264,21 @@ int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu)
ret = kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
vcpu->arch.timer.init_done = false;
+ ret = kvm_riscv_vcpu_timer_cancel(&vcpu->arch.vstimer);
+ vcpu->arch.vstimer.init_done = false;
+
return ret;
}
int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu)
{
- return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
+ kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
+ kvm_riscv_vcpu_timer_cancel(&vcpu->arch.vstimer);
+
+ return 0;
}
-void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
+static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu)
{
struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
@@ -214,6 +290,56 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
#endif
}
+void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_timer *vst;
+ struct kvm_vcpu_csr *csr;
+
+ kvm_riscv_vcpu_update_timedelta(vcpu);
+
+ if (!cpu_sstc_ext_available)
+ return;
+
+ vst = &vcpu->arch.vstimer;
+ csr = &vcpu->arch.guest_csr;
+#ifdef CONFIG_64BIT
+ csr_write(CSR_VSTIMECMP, csr->vstimecmp);
+#else
+ csr_write(CSR_VSTIMECMP, (u32)csr->vstimecmp);
+ csr_write(CSR_VSTIMECMPH, (u32)(csr->vstimecmp >> 32));
+#endif
+
+ /* vstimer should be enabled for the remaining operations */
+ if (unlikely(!vst->init_done))
+ return;
+
+ if (kvm_vcpu_is_blocking(vcpu))
+ kvm_riscv_vcpu_timer_blocking(vcpu);
+}
+
+void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_csr *csr;
+ struct kvm_vcpu_timer *vst;
+
+ if (!cpu_sstc_ext_available)
+ return;
+
+ csr = &vcpu->arch.guest_csr;
+ vst = &vcpu->arch.vstimer;
+#ifdef CONFIG_64BIT
+ csr->vstimecmp = csr_read(CSR_VSTIMECMP);
+#else
+ csr->vstimecmp = csr_read(CSR_VSTIMECMP);
+ csr->vstimecmp |= (u64)csr_read(CSR_VSTIMECMPH) >> 32;
+#endif
+ /* vstimer should be enabled for the remaining operations */
+ if (unlikely(!vst->init_done))
+ return;
+
+ kvm_riscv_vcpu_timer_unblocking(vcpu);
+}
+
int kvm_riscv_guest_timer_init(struct kvm *kvm)
{
struct kvm_guest_timer *gt = &kvm->arch.timer;
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-02-28 9:43 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-28 9:42 [RFC PATCH 0/6] Add Sstc extension support Atish Patra
2022-02-28 9:42 ` [RFC PATCH 1/6] RISC-V: Add SSTC extension CSR details Atish Patra
2022-02-28 9:42 ` [RFC PATCH 2/6] RISC-V: Enable sstc extension parsing from DT Atish Patra
2022-02-28 9:42 ` [RFC PATCH 3/6] RISC-V: Prefer sstc extension if available Atish Patra
2022-02-28 9:42 ` [RFC PATCH 4/6] RISC-V: Restrict the isa field in config register to base extensions Atish Patra
2022-02-28 9:42 ` [RFC PATCH 5/6] RISC-V: KVM: Introduce ISA extension register Atish Patra
2022-02-28 9:42 ` [RFC PATCH 6/6] RISC-V: KVM: Support sstc extension Atish Patra
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