From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-media@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Frank Rowand <frowand.list@gmail.com>,
Maxime Ripard <mripard@kernel.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Subject: [PATCH v3 7/8] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
Date: Wed, 2 Mar 2022 22:10:59 +0100 [thread overview]
Message-ID: <20220302211100.65264-8-paul.kocialkowski@bootlin.com> (raw)
In-Reply-To: <20220302211100.65264-1-paul.kocialkowski@bootlin.com>
MIPI CSI-2 is supported on the A83T with a dedicated controller that
covers both the protocol and D-PHY. It can be connected to the CSI
interface as a V4L2 subdev through the fwnode graph.
This is not done by default since connecting the bridge without a
subdev attached to it will cause a failure on the CSI driver.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 82fdb04122ca..ecf9f3b2c0c0 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1064,6 +1064,32 @@ csi: camera@1cb0000 {
status = "disabled";
};
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-a83t-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_MIPI_CSI>,
+ <&ccu CLK_CSI_MISC>;
+ clock-names = "bus", "mod", "mipi", "misc";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
hdmi: hdmi@1ee0000 {
compatible = "allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee0000 0x10000>;
--
2.35.1
next prev parent reply other threads:[~2022-03-02 21:11 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-02 21:10 [PATCH v3 0/8] Allwinner A31/A83T MIPI CSI-2 and A31 ISP / Platform Support Paul Kocialkowski
2022-03-02 21:10 ` [PATCH RFC v3 1/8] of: Mark interconnects property supplier as optional Paul Kocialkowski
2022-03-07 23:21 ` Rob Herring
2022-03-08 3:34 ` Saravana Kannan
2022-07-27 12:06 ` Maxime Ripard
2022-07-27 16:06 ` Saravana Kannan
2022-07-27 17:17 ` Paul Kocialkowski
2022-07-27 18:07 ` Saravana Kannan
2022-03-02 21:10 ` [PATCH v3 2/8] dt-bindings: interconnect: sunxi: Add V3s mbus compatible Paul Kocialkowski
2022-03-07 23:21 ` Rob Herring
2022-04-10 3:51 ` Samuel Holland
2022-03-02 21:10 ` [PATCH v3 3/8] clk: sunxi-ng: v3s: Export MBUS and DRAM clocks to the public header Paul Kocialkowski
2022-04-10 3:51 ` Samuel Holland
2022-03-02 21:10 ` [PATCH v3 4/8] ARM: dts: sun8i: v3s: Add mbus node to represent the interconnect Paul Kocialkowski
2022-04-10 3:51 ` Samuel Holland
2022-03-02 21:10 ` [PATCH v3 5/8] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support Paul Kocialkowski
2022-03-02 21:10 ` [PATCH v3 6/8] ARM: dts: sun8i: v3s: Add support for the ISP Paul Kocialkowski
2022-03-02 21:10 ` Paul Kocialkowski [this message]
2022-03-02 21:11 ` [PATCH NOT FOR MERGE v3 8/8] ARM: dts: sun8i: a83t: bananapi-m3: Enable MIPI CSI-2 with OV8865 Paul Kocialkowski
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