[PATCH 0/2] Add support for hwrng on PolarFire SoC

[PATCH 0/2] Add support for hwrng on PolarFire SoC

[conor.dooley]

From: Conor Dooley <conor.dooley@microchip.com>

As it says on the tin, add support for the hardware rng on PolarFire
SoC, which is accessed via the system controller. While we're at it,
add the rng driver to the list of files included as part of the SoC
support in MAINTAINERS.

Base commit is in arm/soc branch of the soc tree as the hwrng driver
depends on the system controller, which is to be introduced via that
tree in 5.18

Conor Dooley (2):
  hwrng: mpfs - add polarfire soc hwrng support
  MAINTAINERS: update PolarFire SoC support

 MAINTAINERS                       |   1 +
 drivers/char/hw_random/Kconfig    |  13 ++++
 drivers/char/hw_random/Makefile   |   1 +
 drivers/char/hw_random/mpfs-rng.c | 103 ++++++++++++++++++++++++++++++
 4 files changed, 118 insertions(+)
 create mode 100644 drivers/char/hw_random/mpfs-rng.c


base-commit: a483b1b232e616d0095a59b987ffc739bc1b56bc
-- 
2.35.1

[PATCH 1/2] hwrng: mpfs - add polarfire soc hwrng support

[conor.dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Add a driver to access the hardware random number generator on the
Polarfire SoC. The hwrng can only be accessed via the system controller,
so use the mailbox interface the system controller exposes to access the
hwrng.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/char/hw_random/Kconfig    |  13 ++++
 drivers/char/hw_random/Makefile   |   1 +
 drivers/char/hw_random/mpfs-rng.c | 103 ++++++++++++++++++++++++++++++
 3 files changed, 117 insertions(+)
 create mode 100644 drivers/char/hw_random/mpfs-rng.c

diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 9704963f9d50..69f1fd538589 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -385,6 +385,19 @@ config HW_RANDOM_PIC32
 
 	  If unsure, say Y.
 
+config HW_RANDOM_POLARFIRE_SOC
+	tristate "Microchip PolarFire SoC Random Number Generator support"
+	depends on HW_RANDOM && POLARFIRE_SOC_SYS_CTRL
+	help
+	  This driver provides kernel-side support for the Random Number
+	  Generator hardware found on PolarFire SoC (MPFS).
+
+	  To compile this driver as a module, choose M here. The
+	  module will be called mfps_rng.
+
+	  If unsure, say N.
+
+
 config HW_RANDOM_MESON
 	tristate "Amlogic Meson Random Number Generator support"
 	depends on HW_RANDOM
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 584d47ba32f7..3e948cf04476 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -46,3 +46,4 @@ obj-$(CONFIG_HW_RANDOM_CCTRNG) += cctrng.o
 obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
 obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
 obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
+obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
diff --git a/drivers/char/hw_random/mpfs-rng.c b/drivers/char/hw_random/mpfs-rng.c
new file mode 100644
index 000000000000..a103c765d021
--- /dev/null
+++ b/drivers/char/hw_random/mpfs-rng.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Microchip PolarFire SoC (MPFS) hardware random driver
+ *
+ * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
+ *
+ * Author: Conor Dooley <conor.dooley@microchip.com>
+ */
+
+#include <linux/module.h>
+#include <linux/hw_random.h>
+#include <linux/platform_device.h>
+#include <soc/microchip/mpfs.h>
+
+#define CMD_OPCODE	0x21
+#define CMD_DATA_SIZE	0U
+#define CMD_DATA	NULL
+#define MBOX_OFFSET	0U
+#define RESP_OFFSET	0U
+#define RNG_RESP_BYTES	32U
+
+struct mpfs_rng {
+	struct mpfs_sys_controller *sys_controller;
+	struct hwrng rng;
+};
+
+static int mpfs_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+	struct mpfs_rng *rng_priv = container_of(rng, struct mpfs_rng, rng);
+	u32 response_msg[RNG_RESP_BYTES / sizeof(u32)];
+	unsigned int count = 0, copy_size_bytes;
+	int ret;
+
+	struct mpfs_mss_response response = {
+		.resp_status = 0U,
+		.resp_msg = (u32 *)response_msg,
+		.resp_size = RNG_RESP_BYTES
+	};
+	struct mpfs_mss_msg msg = {
+		.cmd_opcode = CMD_OPCODE,
+		.cmd_data_size = CMD_DATA_SIZE,
+		.response = &response,
+		.cmd_data = CMD_DATA,
+		.mbox_offset = MBOX_OFFSET,
+		.resp_offset = RESP_OFFSET
+	};
+
+	while (count < max) {
+		ret = mpfs_blocking_transaction(rng_priv->sys_controller, &msg);
+		if (ret)
+			return ret;
+
+		copy_size_bytes = max - count > RNG_RESP_BYTES ? RNG_RESP_BYTES : max - count;
+		memcpy(buf + count, response_msg, copy_size_bytes);
+
+		count += copy_size_bytes;
+		if (!wait)
+			break;
+	}
+
+	return count;
+}
+
+static int mpfs_rng_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mpfs_rng *rng_priv;
+	int ret;
+
+	rng_priv = devm_kzalloc(dev, sizeof(*rng_priv), GFP_KERNEL);
+	if (!rng_priv)
+		return -ENOMEM;
+
+	rng_priv->sys_controller =  mpfs_sys_controller_get(&pdev->dev);
+	if (IS_ERR(rng_priv->sys_controller))
+		return dev_err_probe(dev, PTR_ERR(rng_priv->sys_controller),
+				     "Failed to register system controller hwrng sub device\n");
+
+	rng_priv->rng.read = mpfs_rng_read;
+	rng_priv->rng.name = pdev->name;
+
+	platform_set_drvdata(pdev, rng_priv);
+
+	ret = devm_hwrng_register(&pdev->dev, &rng_priv->rng);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "Failed to register MPFS hwrng\n");
+
+	dev_info(&pdev->dev, "Registered MPFS hwrng\n");
+
+	return 0;
+}
+
+static struct platform_driver mpfs_rng_driver = {
+	.driver = {
+		.name = "mpfs-rng",
+	},
+	.probe = mpfs_rng_probe,
+};
+module_platform_driver(mpfs_rng_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_DESCRIPTION("PolarFire SoC (MPFS) hardware random driver");
-- 
2.35.1

[PATCH 2/2] MAINTAINERS: update PolarFire SoC support

[conor.dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Add mpfs-rng to the list of files included in PolarFire SoC support.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 573e5ee54162..dfbd076bddb6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16589,6 +16589,7 @@ RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
 M:	Lewis Hanly <lewis.hanly@microchip.com>
 L:	linux-riscv@lists.infradead.org
 S:	Supported
+F:	drivers/char/hw_random/mpfs-rng.c
 F:	drivers/mailbox/mailbox-mpfs.c
 F:	drivers/soc/microchip/
 F:	include/soc/microchip/mpfs.h
-- 
2.35.1

Re: [PATCH 1/2] hwrng: mpfs - add polarfire soc hwrng support

[Dominik Brodowski]

Am Mon, Mar 07, 2022 at 03:40:23PM +0000 schrieb conor.dooley@microchip.com:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Add a driver to access the hardware random number generator on the
> Polarfire SoC. The hwrng can only be accessed via the system controller,
> so use the mailbox interface the system controller exposes to access the
> hwrng.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  drivers/char/hw_random/Kconfig    |  13 ++++
>  drivers/char/hw_random/Makefile   |   1 +
>  drivers/char/hw_random/mpfs-rng.c | 103 ++++++++++++++++++++++++++++++
>  3 files changed, 117 insertions(+)
>  create mode 100644 drivers/char/hw_random/mpfs-rng.c
> 
> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
> index 9704963f9d50..69f1fd538589 100644
> --- a/drivers/char/hw_random/Kconfig
> +++ b/drivers/char/hw_random/Kconfig
> @@ -385,6 +385,19 @@ config HW_RANDOM_PIC32
>  
>  	  If unsure, say Y.
>  
> +config HW_RANDOM_POLARFIRE_SOC
> +	tristate "Microchip PolarFire SoC Random Number Generator support"
> +	depends on HW_RANDOM && POLARFIRE_SOC_SYS_CTRL
> +	help
> +	  This driver provides kernel-side support for the Random Number
> +	  Generator hardware found on PolarFire SoC (MPFS).
> +
> +	  To compile this driver as a module, choose M here. The
> +	  module will be called mfps_rng.
> +
> +	  If unsure, say N.
> +
> +
>  config HW_RANDOM_MESON
>  	tristate "Amlogic Meson Random Number Generator support"
>  	depends on HW_RANDOM
> diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
> index 584d47ba32f7..3e948cf04476 100644
> --- a/drivers/char/hw_random/Makefile
> +++ b/drivers/char/hw_random/Makefile
> @@ -46,3 +46,4 @@ obj-$(CONFIG_HW_RANDOM_CCTRNG) += cctrng.o
>  obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
>  obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
>  obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
> +obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
> diff --git a/drivers/char/hw_random/mpfs-rng.c b/drivers/char/hw_random/mpfs-rng.c
> new file mode 100644
> index 000000000000..a103c765d021
> --- /dev/null
> +++ b/drivers/char/hw_random/mpfs-rng.c
> @@ -0,0 +1,103 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Microchip PolarFire SoC (MPFS) hardware random driver
> + *
> + * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
> + *
> + * Author: Conor Dooley <conor.dooley@microchip.com>
> + */
> +
> +#include <linux/module.h>
> +#include <linux/hw_random.h>
> +#include <linux/platform_device.h>
> +#include <soc/microchip/mpfs.h>
> +
> +#define CMD_OPCODE	0x21
> +#define CMD_DATA_SIZE	0U
> +#define CMD_DATA	NULL
> +#define MBOX_OFFSET	0U
> +#define RESP_OFFSET	0U
> +#define RNG_RESP_BYTES	32U
> +
> +struct mpfs_rng {
> +	struct mpfs_sys_controller *sys_controller;
> +	struct hwrng rng;
> +};
> +
> +static int mpfs_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
> +{
> +	struct mpfs_rng *rng_priv = container_of(rng, struct mpfs_rng, rng);
> +	u32 response_msg[RNG_RESP_BYTES / sizeof(u32)];
> +	unsigned int count = 0, copy_size_bytes;
> +	int ret;
> +
> +	struct mpfs_mss_response response = {
> +		.resp_status = 0U,
> +		.resp_msg = (u32 *)response_msg,
> +		.resp_size = RNG_RESP_BYTES
> +	};
> +	struct mpfs_mss_msg msg = {
> +		.cmd_opcode = CMD_OPCODE,
> +		.cmd_data_size = CMD_DATA_SIZE,
> +		.response = &response,
> +		.cmd_data = CMD_DATA,
> +		.mbox_offset = MBOX_OFFSET,
> +		.resp_offset = RESP_OFFSET
> +	};
> +
> +	while (count < max) {
> +		ret = mpfs_blocking_transaction(rng_priv->sys_controller, &msg);
> +		if (ret)
> +			return ret;
> +
> +		copy_size_bytes = max - count > RNG_RESP_BYTES ? RNG_RESP_BYTES : max - count;
> +		memcpy(buf + count, response_msg, copy_size_bytes);
> +
> +		count += copy_size_bytes;
> +		if (!wait)
> +			break;
> +	}
> +
> +	return count;
> +}
> +
> +static int mpfs_rng_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct mpfs_rng *rng_priv;
> +	int ret;
> +
> +	rng_priv = devm_kzalloc(dev, sizeof(*rng_priv), GFP_KERNEL);
> +	if (!rng_priv)
> +		return -ENOMEM;
> +
> +	rng_priv->sys_controller =  mpfs_sys_controller_get(&pdev->dev);
> +	if (IS_ERR(rng_priv->sys_controller))
> +		return dev_err_probe(dev, PTR_ERR(rng_priv->sys_controller),
> +				     "Failed to register system controller hwrng sub device\n");
> +
> +	rng_priv->rng.read = mpfs_rng_read;
> +	rng_priv->rng.name = pdev->name;

Is there also some quality estimation, or should this hwrng only be trusted
if it passes validation by userspace?

Thanks,
	Dominik

Re: [PATCH 1/2] hwrng: mpfs - add polarfire soc hwrng support

[Conor.Dooley]

On 08/03/2022 07:55, Dominik Brodowski wrote:
> [You don't often get email from linux@dominikbrodowski.net. Learn why this is important at http://aka.ms/LearnAboutSenderIdentification.]
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am Mon, Mar 07, 2022 at 03:40:23PM +0000 schrieb conor.dooley@microchip.com:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> Add a driver to access the hardware random number generator on the
>> Polarfire SoC. The hwrng can only be accessed via the system controller,
>> so use the mailbox interface the system controller exposes to access the
>> hwrng.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>>   drivers/char/hw_random/Kconfig    |  13 ++++
>>   drivers/char/hw_random/Makefile   |   1 +
>>   drivers/char/hw_random/mpfs-rng.c | 103 ++++++++++++++++++++++++++++++
>>   3 files changed, 117 insertions(+)
>>   create mode 100644 drivers/char/hw_random/mpfs-rng.c
>>
>> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
>> index 9704963f9d50..69f1fd538589 100644
>> --- a/drivers/char/hw_random/Kconfig
>> +++ b/drivers/char/hw_random/Kconfig
>> @@ -385,6 +385,19 @@ config HW_RANDOM_PIC32
>>
>>          If unsure, say Y.
>>
>> +config HW_RANDOM_POLARFIRE_SOC
>> +     tristate "Microchip PolarFire SoC Random Number Generator support"
>> +     depends on HW_RANDOM && POLARFIRE_SOC_SYS_CTRL
>> +     help
>> +       This driver provides kernel-side support for the Random Number
>> +       Generator hardware found on PolarFire SoC (MPFS).
>> +
>> +       To compile this driver as a module, choose M here. The
>> +       module will be called mfps_rng.
>> +
>> +       If unsure, say N.
>> +
>> +
>>   config HW_RANDOM_MESON
>>        tristate "Amlogic Meson Random Number Generator support"
>>        depends on HW_RANDOM
>> diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
>> index 584d47ba32f7..3e948cf04476 100644
>> --- a/drivers/char/hw_random/Makefile
>> +++ b/drivers/char/hw_random/Makefile
>> @@ -46,3 +46,4 @@ obj-$(CONFIG_HW_RANDOM_CCTRNG) += cctrng.o
>>   obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
>>   obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
>>   obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
>> +obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
>> diff --git a/drivers/char/hw_random/mpfs-rng.c b/drivers/char/hw_random/mpfs-rng.c
>> new file mode 100644
>> index 000000000000..a103c765d021
>> --- /dev/null
>> +++ b/drivers/char/hw_random/mpfs-rng.c
>> @@ -0,0 +1,103 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Microchip PolarFire SoC (MPFS) hardware random driver
>> + *
>> + * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
>> + *
>> + * Author: Conor Dooley <conor.dooley@microchip.com>
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/hw_random.h>
>> +#include <linux/platform_device.h>
>> +#include <soc/microchip/mpfs.h>
>> +
>> +#define CMD_OPCODE   0x21
>> +#define CMD_DATA_SIZE        0U
>> +#define CMD_DATA     NULL
>> +#define MBOX_OFFSET  0U
>> +#define RESP_OFFSET  0U
>> +#define RNG_RESP_BYTES       32U
>> +
>> +struct mpfs_rng {
>> +     struct mpfs_sys_controller *sys_controller;
>> +     struct hwrng rng;
>> +};
>> +
>> +static int mpfs_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
>> +{
>> +     struct mpfs_rng *rng_priv = container_of(rng, struct mpfs_rng, rng);
>> +     u32 response_msg[RNG_RESP_BYTES / sizeof(u32)];
>> +     unsigned int count = 0, copy_size_bytes;
>> +     int ret;
>> +
>> +     struct mpfs_mss_response response = {
>> +             .resp_status = 0U,
>> +             .resp_msg = (u32 *)response_msg,
>> +             .resp_size = RNG_RESP_BYTES
>> +     };
>> +     struct mpfs_mss_msg msg = {
>> +             .cmd_opcode = CMD_OPCODE,
>> +             .cmd_data_size = CMD_DATA_SIZE,
>> +             .response = &response,
>> +             .cmd_data = CMD_DATA,
>> +             .mbox_offset = MBOX_OFFSET,
>> +             .resp_offset = RESP_OFFSET
>> +     };
>> +
>> +     while (count < max) {
>> +             ret = mpfs_blocking_transaction(rng_priv->sys_controller, &msg);
>> +             if (ret)
>> +                     return ret;
>> +
>> +             copy_size_bytes = max - count > RNG_RESP_BYTES ? RNG_RESP_BYTES : max - count;
>> +             memcpy(buf + count, response_msg, copy_size_bytes);
>> +
>> +             count += copy_size_bytes;
>> +             if (!wait)
>> +                     break;
>> +     }
>> +
>> +     return count;
>> +}
>> +
>> +static int mpfs_rng_probe(struct platform_device *pdev)
>> +{
>> +     struct device *dev = &pdev->dev;
>> +     struct mpfs_rng *rng_priv;
>> +     int ret;
>> +
>> +     rng_priv = devm_kzalloc(dev, sizeof(*rng_priv), GFP_KERNEL);
>> +     if (!rng_priv)
>> +             return -ENOMEM;
>> +
>> +     rng_priv->sys_controller =  mpfs_sys_controller_get(&pdev->dev);
>> +     if (IS_ERR(rng_priv->sys_controller))
>> +             return dev_err_probe(dev, PTR_ERR(rng_priv->sys_controller),
>> +                                  "Failed to register system controller hwrng sub device\n");
>> +
>> +     rng_priv->rng.read = mpfs_rng_read;
>> +     rng_priv->rng.name = pdev->name;
> 
> Is there also some quality estimation, or should this hwrng only be trusted
> if it passes validation by userspace?

There should be a quality estimation, I'll add one in v2.
Thanks,
Conor.

Re: [PATCH 0/2] Add support for hwrng on PolarFire SoC

[Conor Dooley]

There's an error in the probe function's reference counting.
Will fix that along with the quality estimation in v2.

Can safely ignore this version of the series.

Thanks,
Conor.

On 07/03/2022 15:40, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> As it says on the tin, add support for the hardware rng on PolarFire
> SoC, which is accessed via the system controller. While we're at it,
> add the rng driver to the list of files included as part of the SoC
> support in MAINTAINERS.
> 
> Base commit is in arm/soc branch of the soc tree as the hwrng driver
> depends on the system controller, which is to be introduced via that
> tree in 5.18
> 
> Conor Dooley (2):
>    hwrng: mpfs - add polarfire soc hwrng support
>    MAINTAINERS: update PolarFire SoC support
> 
>   MAINTAINERS                       |   1 +
>   drivers/char/hw_random/Kconfig    |  13 ++++
>   drivers/char/hw_random/Makefile   |   1 +
>   drivers/char/hw_random/mpfs-rng.c | 103 ++++++++++++++++++++++++++++++
>   4 files changed, 118 insertions(+)
>   create mode 100644 drivers/char/hw_random/mpfs-rng.c
> 
> 
> base-commit: a483b1b232e616d0095a59b987ffc739bc1b56bc